text
string | meta
dict |
|---|---|
glabel func_80980E24
/* 037B4 80980E24 27BDFFB8 */ addiu $sp, $sp, 0xFFB8 ## $sp = FFFFFFB8
/* 037B8 80980E28 AFBF001C */ sw $ra, 0x001C($sp)
/* 037BC 80980E2C AFB00018 */ sw $s0, 0x0018($sp)
/* 037C0 80980E30 AFA40048 */ sw $a0, 0x0048($sp)
/* 037C4 80980E34 AFA5004C */ sw $a1, 0x004C($sp)
/* 037C8 80980E38 8CB00000 */ lw $s0, 0x0000($a1) ## 00000000
/* 037CC 80980E3C 3C068098 */ lui $a2, %hi(D_80982810) ## $a2 = 80980000
/* 037D0 80980E40 24C62810 */ addiu $a2, $a2, %lo(D_80982810) ## $a2 = 80982810
/* 037D4 80980E44 27A40030 */ addiu $a0, $sp, 0x0030 ## $a0 = FFFFFFE8
/* 037D8 80980E48 24070402 */ addiu $a3, $zero, 0x0402 ## $a3 = 00000402
/* 037DC 80980E4C 0C031AB1 */ jal func_800C6AC4
/* 037E0 80980E50 02002825 */ or $a1, $s0, $zero ## $a1 = 00000000
/* 037E4 80980E54 0C024F46 */ jal func_80093D18
/* 037E8 80980E58 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 037EC 80980E5C 8E0202C0 */ lw $v0, 0x02C0($s0) ## 000002C0
/* 037F0 80980E60 3C18DA38 */ lui $t8, 0xDA38 ## $t8 = DA380000
/* 037F4 80980E64 37180002 */ ori $t8, $t8, 0x0002 ## $t8 = DA380002
/* 037F8 80980E68 244F0008 */ addiu $t7, $v0, 0x0008 ## $t7 = 00000008
/* 037FC 80980E6C AE0F02C0 */ sw $t7, 0x02C0($s0) ## 000002C0
/* 03800 80980E70 3C058098 */ lui $a1, %hi(D_80982828) ## $a1 = 80980000
/* 03804 80980E74 AC580000 */ sw $t8, 0x0000($v0) ## 00000000
/* 03808 80980E78 24A52828 */ addiu $a1, $a1, %lo(D_80982828) ## $a1 = 80982828
/* 0380C 80980E7C 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 03810 80980E80 24060404 */ addiu $a2, $zero, 0x0404 ## $a2 = 00000404
/* 03814 80980E84 0C0346A2 */ jal Matrix_NewMtx
/* 03818 80980E88 AFA2002C */ sw $v0, 0x002C($sp)
/* 0381C 80980E8C 8FA3002C */ lw $v1, 0x002C($sp)
/* 03820 80980E90 3C090600 */ lui $t1, 0x0600 ## $t1 = 06000000
/* 03824 80980E94 25297630 */ addiu $t1, $t1, 0x7630 ## $t1 = 06007630
/* 03828 80980E98 AC620004 */ sw $v0, 0x0004($v1) ## 00000004
/* 0382C 80980E9C 8E0202C0 */ lw $v0, 0x02C0($s0) ## 000002C0
/* 03830 80980EA0 3C08DE00 */ lui $t0, 0xDE00 ## $t0 = DE000000
/* 03834 80980EA4 3C0BD838 */ lui $t3, 0xD838 ## $t3 = D8380000
/* 03838 80980EA8 24590008 */ addiu $t9, $v0, 0x0008 ## $t9 = 00000008
/* 0383C 80980EAC AE1902C0 */ sw $t9, 0x02C0($s0) ## 000002C0
/* 03840 80980EB0 AC490004 */ sw $t1, 0x0004($v0) ## 00000004
/* 03844 80980EB4 AC480000 */ sw $t0, 0x0000($v0) ## 00000000
/* 03848 80980EB8 8E0202C0 */ lw $v0, 0x02C0($s0) ## 000002C0
/* 0384C 80980EBC 356B0002 */ ori $t3, $t3, 0x0002 ## $t3 = D8380002
/* 03850 80980EC0 240C0040 */ addiu $t4, $zero, 0x0040 ## $t4 = 00000040
/* 03854 80980EC4 244A0008 */ addiu $t2, $v0, 0x0008 ## $t2 = 00000008
/* 03858 80980EC8 AE0A02C0 */ sw $t2, 0x02C0($s0) ## 000002C0
/* 0385C 80980ECC 3C068098 */ lui $a2, %hi(D_80982840) ## $a2 = 80980000
/* 03860 80980ED0 24C62840 */ addiu $a2, $a2, %lo(D_80982840) ## $a2 = 80982840
/* 03864 80980ED4 27A40030 */ addiu $a0, $sp, 0x0030 ## $a0 = FFFFFFE8
/* 03868 80980ED8 02002825 */ or $a1, $s0, $zero ## $a1 = 00000000
/* 0386C 80980EDC 24070408 */ addiu $a3, $zero, 0x0408 ## $a3 = 00000408
/* 03870 80980EE0 AC4C0004 */ sw $t4, 0x0004($v0) ## 00000004
/* 03874 80980EE4 0C031AD5 */ jal func_800C6B54
/* 03878 80980EE8 AC4B0000 */ sw $t3, 0x0000($v0) ## 00000000
/* 0387C 80980EEC 8FBF001C */ lw $ra, 0x001C($sp)
/* 03880 80980EF0 8FB00018 */ lw $s0, 0x0018($sp)
/* 03884 80980EF4 27BD0048 */ addiu $sp, $sp, 0x0048 ## $sp = 00000000
/* 03888 80980EF8 03E00008 */ jr $ra
/* 0388C 80980EFC 00000000 */ nop
|
{
"language": "Assembly"
}
|
#! /usr/bin/env perl
# Copyright 2011-2016 The OpenSSL Project Authors. All Rights Reserved.
#
# Licensed under the OpenSSL license (the "License"). You may not use
# this file except in compliance with the License. You can obtain a copy
# in the file LICENSE in the source distribution or at
# https://www.openssl.org/source/license.html
# ====================================================================
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
# details see http://www.openssl.org/~appro/cryptogams/.
# ====================================================================
# September 2011
#
# Assembler helpers for Padlock engine. Compared to original engine
# version relying on inline assembler and compiled with gcc 3.4.6 it
# was measured to provide ~100% improvement on misaligned data in ECB
# mode and ~75% in CBC mode. For aligned data improvement can be
# observed for short inputs only, e.g. 45% for 64-byte messages in
# ECB mode, 20% in CBC. Difference in performance for aligned vs.
# misaligned data depends on misalignment and is either ~1.8x or 2.9x.
# These are approximately same factors as for hardware support, so
# there is little reason to rely on the latter. On the contrary, it
# might actually hurt performance in mixture of aligned and misaligned
# buffers, because a) if you choose to flip 'align' flag in control
# word on per-buffer basis, then you'd have to reload key context,
# which incurs penalty; b) if you choose to set 'align' flag
# permanently, it limits performance even for aligned data to ~1/2.
# All above mentioned results were collected on 1.5GHz C7. Nano on the
# other hand handles unaligned data more gracefully. Depending on
# algorithm and how unaligned data is, hardware can be up to 70% more
# efficient than below software alignment procedures, nor does 'align'
# flag have affect on aligned performance [if has any meaning at all].
# Therefore suggestion is to unconditionally set 'align' flag on Nano
# for optimal performance.
$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
push(@INC,"${dir}","${dir}../../crypto/perlasm");
require "x86asm.pl";
$output=pop;
open STDOUT,">$output";
&asm_init($ARGV[0],$0);
%PADLOCK_PREFETCH=(ecb=>128, cbc=>64); # prefetch errata
$PADLOCK_CHUNK=512; # Must be a power of 2 larger than 16
$ctx="edx";
$out="edi";
$inp="esi";
$len="ecx";
$chunk="ebx";
&function_begin_B("padlock_capability");
&push ("ebx");
&pushf ();
&pop ("eax");
&mov ("ecx","eax");
&xor ("eax",1<<21);
&push ("eax");
&popf ();
&pushf ();
&pop ("eax");
&xor ("ecx","eax");
&xor ("eax","eax");
&bt ("ecx",21);
&jnc (&label("noluck"));
&cpuid ();
&xor ("eax","eax");
&cmp ("ebx","0x".unpack("H*",'tneC'));
&jne (&label("noluck"));
&cmp ("edx","0x".unpack("H*",'Hrua'));
&jne (&label("noluck"));
&cmp ("ecx","0x".unpack("H*",'slua'));
&jne (&label("noluck"));
&mov ("eax",0xC0000000);
&cpuid ();
&mov ("edx","eax");
&xor ("eax","eax");
&cmp ("edx",0xC0000001);
&jb (&label("noluck"));
&mov ("eax",1);
&cpuid ();
&or ("eax",0x0f);
&xor ("ebx","ebx");
&and ("eax",0x0fff);
&cmp ("eax",0x06ff); # check for Nano
&sete ("bl");
&mov ("eax",0xC0000001);
&push ("ebx");
&cpuid ();
&pop ("ebx");
&mov ("eax","edx");
&shl ("ebx",4); # bit#4 denotes Nano
&and ("eax",0xffffffef);
&or ("eax","ebx")
&set_label("noluck");
&pop ("ebx");
&ret ();
&function_end_B("padlock_capability")
&function_begin_B("padlock_key_bswap");
&mov ("edx",&wparam(0));
&mov ("ecx",&DWP(240,"edx"));
&set_label("bswap_loop");
&mov ("eax",&DWP(0,"edx"));
&bswap ("eax");
&mov (&DWP(0,"edx"),"eax");
&lea ("edx",&DWP(4,"edx"));
&sub ("ecx",1);
&jnz (&label("bswap_loop"));
&ret ();
&function_end_B("padlock_key_bswap");
# This is heuristic key context tracing. At first one
# believes that one should use atomic swap instructions,
# but it's not actually necessary. Point is that if
# padlock_saved_context was changed by another thread
# after we've read it and before we compare it with ctx,
# our key *shall* be reloaded upon thread context switch
# and we are therefore set in either case...
&static_label("padlock_saved_context");
&function_begin_B("padlock_verify_context");
&mov ($ctx,&wparam(0));
&lea ("eax",($::win32 or $::coff) ? &DWP(&label("padlock_saved_context")) :
&DWP(&label("padlock_saved_context")."-".&label("verify_pic_point")));
&pushf ();
&call ("_padlock_verify_ctx");
&set_label("verify_pic_point");
&lea ("esp",&DWP(4,"esp"));
&ret ();
&function_end_B("padlock_verify_context");
&function_begin_B("_padlock_verify_ctx");
&add ("eax",&DWP(0,"esp")) if(!($::win32 or $::coff));# &padlock_saved_context
&bt (&DWP(4,"esp"),30); # eflags
&jnc (&label("verified"));
&cmp ($ctx,&DWP(0,"eax"));
&je (&label("verified"));
&pushf ();
&popf ();
&set_label("verified");
&mov (&DWP(0,"eax"),$ctx);
&ret ();
&function_end_B("_padlock_verify_ctx");
&function_begin_B("padlock_reload_key");
&pushf ();
&popf ();
&ret ();
&function_end_B("padlock_reload_key");
&function_begin_B("padlock_aes_block");
&push ("edi");
&push ("esi");
&push ("ebx");
&mov ($out,&wparam(0)); # must be 16-byte aligned
&mov ($inp,&wparam(1)); # must be 16-byte aligned
&mov ($ctx,&wparam(2));
&mov ($len,1);
&lea ("ebx",&DWP(32,$ctx)); # key
&lea ($ctx,&DWP(16,$ctx)); # control word
&data_byte(0xf3,0x0f,0xa7,0xc8); # rep xcryptecb
&pop ("ebx");
&pop ("esi");
&pop ("edi");
&ret ();
&function_end_B("padlock_aes_block");
sub generate_mode {
my ($mode,$opcode) = @_;
# int padlock_$mode_encrypt(void *out, const void *inp,
# struct padlock_cipher_data *ctx, size_t len);
&function_begin("padlock_${mode}_encrypt");
&mov ($out,&wparam(0));
&mov ($inp,&wparam(1));
&mov ($ctx,&wparam(2));
&mov ($len,&wparam(3));
&test ($ctx,15);
&jnz (&label("${mode}_abort"));
&test ($len,15);
&jnz (&label("${mode}_abort"));
&lea ("eax",($::win32 or $::coff) ? &DWP(&label("padlock_saved_context")) :
&DWP(&label("padlock_saved_context")."-".&label("${mode}_pic_point")));
&pushf ();
&cld ();
&call ("_padlock_verify_ctx");
&set_label("${mode}_pic_point");
&lea ($ctx,&DWP(16,$ctx)); # control word
&xor ("eax","eax");
if ($mode eq "ctr32") {
&movq ("mm0",&QWP(-16,$ctx)); # load [upper part of] counter
} else {
&xor ("ebx","ebx");
&test (&DWP(0,$ctx),1<<5); # align bit in control word
&jnz (&label("${mode}_aligned"));
&test ($out,0x0f);
&setz ("al"); # !out_misaligned
&test ($inp,0x0f);
&setz ("bl"); # !inp_misaligned
&test ("eax","ebx");
&jnz (&label("${mode}_aligned"));
&neg ("eax");
}
&mov ($chunk,$PADLOCK_CHUNK);
¬ ("eax"); # out_misaligned?-1:0
&lea ("ebp",&DWP(-24,"esp"));
&cmp ($len,$chunk);
&cmovc ($chunk,$len); # chunk=len>PADLOCK_CHUNK?PADLOCK_CHUNK:len
&and ("eax",$chunk); # out_misaligned?chunk:0
&mov ($chunk,$len);
&neg ("eax");
&and ($chunk,$PADLOCK_CHUNK-1); # chunk=len%PADLOCK_CHUNK
&lea ("esp",&DWP(0,"eax","ebp")); # alloca
&mov ("eax",$PADLOCK_CHUNK);
&cmovz ($chunk,"eax"); # chunk=chunk?:PADLOCK_CHUNK
&mov ("eax","ebp");
&and ("ebp",-16);
&and ("esp",-16);
&mov (&DWP(16,"ebp"),"eax");
if ($PADLOCK_PREFETCH{$mode}) {
&cmp ($len,$chunk);
&ja (&label("${mode}_loop"));
&mov ("eax",$inp); # check if prefetch crosses page
&cmp ("ebp","esp");
&cmove ("eax",$out);
&add ("eax",$len);
&neg ("eax");
&and ("eax",0xfff); # distance to page boundary
&cmp ("eax",$PADLOCK_PREFETCH{$mode});
&mov ("eax",-$PADLOCK_PREFETCH{$mode});
&cmovae ("eax",$chunk); # mask=distance<prefetch?-prefetch:-1
&and ($chunk,"eax");
&jz (&label("${mode}_unaligned_tail"));
}
&jmp (&label("${mode}_loop"));
&set_label("${mode}_loop",16);
&mov (&DWP(0,"ebp"),$out); # save parameters
&mov (&DWP(4,"ebp"),$inp);
&mov (&DWP(8,"ebp"),$len);
&mov ($len,$chunk);
&mov (&DWP(12,"ebp"),$chunk); # chunk
if ($mode eq "ctr32") {
&mov ("ecx",&DWP(-4,$ctx));
&xor ($out,$out);
&mov ("eax",&DWP(-8,$ctx)); # borrow $len
&set_label("${mode}_prepare");
&mov (&DWP(12,"esp",$out),"ecx");
&bswap ("ecx");
&movq (&QWP(0,"esp",$out),"mm0");
&inc ("ecx");
&mov (&DWP(8,"esp",$out),"eax");
&bswap ("ecx");
&lea ($out,&DWP(16,$out));
&cmp ($out,$chunk);
&jb (&label("${mode}_prepare"));
&mov (&DWP(-4,$ctx),"ecx");
&lea ($inp,&DWP(0,"esp"));
&lea ($out,&DWP(0,"esp"));
&mov ($len,$chunk);
} else {
&test ($out,0x0f); # out_misaligned
&cmovnz ($out,"esp");
&test ($inp,0x0f); # inp_misaligned
&jz (&label("${mode}_inp_aligned"));
&shr ($len,2);
&data_byte(0xf3,0xa5); # rep movsl
&sub ($out,$chunk);
&mov ($len,$chunk);
&mov ($inp,$out);
&set_label("${mode}_inp_aligned");
}
&lea ("eax",&DWP(-16,$ctx)); # ivp
&lea ("ebx",&DWP(16,$ctx)); # key
&shr ($len,4); # len/=AES_BLOCK_SIZE
&data_byte(0xf3,0x0f,0xa7,$opcode); # rep xcrypt*
if ($mode !~ /ecb|ctr/) {
&movaps ("xmm0",&QWP(0,"eax"));
&movaps (&QWP(-16,$ctx),"xmm0"); # copy [or refresh] iv
}
&mov ($out,&DWP(0,"ebp")); # restore parameters
&mov ($chunk,&DWP(12,"ebp"));
if ($mode eq "ctr32") {
&mov ($inp,&DWP(4,"ebp"));
&xor ($len,$len);
&set_label("${mode}_xor");
&movups ("xmm1",&QWP(0,$inp,$len));
&lea ($len,&DWP(16,$len));
&pxor ("xmm1",&QWP(-16,"esp",$len));
&movups (&QWP(-16,$out,$len),"xmm1");
&cmp ($len,$chunk);
&jb (&label("${mode}_xor"));
} else {
&test ($out,0x0f);
&jz (&label("${mode}_out_aligned"));
&mov ($len,$chunk);
&lea ($inp,&DWP(0,"esp"));
&shr ($len,2);
&data_byte(0xf3,0xa5); # rep movsl
&sub ($out,$chunk);
&set_label("${mode}_out_aligned");
&mov ($inp,&DWP(4,"ebp"));
}
&mov ($len,&DWP(8,"ebp"));
&add ($out,$chunk);
&add ($inp,$chunk);
&sub ($len,$chunk);
&mov ($chunk,$PADLOCK_CHUNK);
if (!$PADLOCK_PREFETCH{$mode}) {
&jnz (&label("${mode}_loop"));
} else {
&jz (&label("${mode}_break"));
&cmp ($len,$chunk);
&jae (&label("${mode}_loop"));
&set_label("${mode}_unaligned_tail");
&xor ("eax","eax");
&cmp ("esp","ebp");
&cmove ("eax",$len);
&sub ("esp","eax"); # alloca
&mov ("eax", $out); # save parameters
&mov ($chunk,$len);
&shr ($len,2);
&lea ($out,&DWP(0,"esp"));
&data_byte(0xf3,0xa5); # rep movsl
&mov ($inp,"esp");
&mov ($out,"eax"); # restore parameters
&mov ($len,$chunk);
&jmp (&label("${mode}_loop"));
&set_label("${mode}_break",16);
}
if ($mode ne "ctr32") {
&cmp ("esp","ebp");
&je (&label("${mode}_done"));
}
&pxor ("xmm0","xmm0");
&lea ("eax",&DWP(0,"esp"));
&set_label("${mode}_bzero");
&movaps (&QWP(0,"eax"),"xmm0");
&lea ("eax",&DWP(16,"eax"));
&cmp ("ebp","eax");
&ja (&label("${mode}_bzero"));
&set_label("${mode}_done");
&mov ("ebp",&DWP(16,"ebp"));
&lea ("esp",&DWP(24,"ebp"));
if ($mode ne "ctr32") {
&jmp (&label("${mode}_exit"));
&set_label("${mode}_aligned",16);
if ($PADLOCK_PREFETCH{$mode}) {
&lea ("ebp",&DWP(0,$inp,$len));
&neg ("ebp");
&and ("ebp",0xfff); # distance to page boundary
&xor ("eax","eax");
&cmp ("ebp",$PADLOCK_PREFETCH{$mode});
&mov ("ebp",$PADLOCK_PREFETCH{$mode}-1);
&cmovae ("ebp","eax");
&and ("ebp",$len); # remainder
&sub ($len,"ebp");
&jz (&label("${mode}_aligned_tail"));
}
&lea ("eax",&DWP(-16,$ctx)); # ivp
&lea ("ebx",&DWP(16,$ctx)); # key
&shr ($len,4); # len/=AES_BLOCK_SIZE
&data_byte(0xf3,0x0f,0xa7,$opcode); # rep xcrypt*
if ($mode ne "ecb") {
&movaps ("xmm0",&QWP(0,"eax"));
&movaps (&QWP(-16,$ctx),"xmm0"); # copy [or refresh] iv
}
if ($PADLOCK_PREFETCH{$mode}) {
&test ("ebp","ebp");
&jz (&label("${mode}_exit"));
&set_label("${mode}_aligned_tail");
&mov ($len,"ebp");
&lea ("ebp",&DWP(-24,"esp"));
&mov ("esp","ebp");
&mov ("eax","ebp");
&sub ("esp",$len);
&and ("ebp",-16);
&and ("esp",-16);
&mov (&DWP(16,"ebp"),"eax");
&mov ("eax", $out); # save parameters
&mov ($chunk,$len);
&shr ($len,2);
&lea ($out,&DWP(0,"esp"));
&data_byte(0xf3,0xa5); # rep movsl
&mov ($inp,"esp");
&mov ($out,"eax"); # restore parameters
&mov ($len,$chunk);
&jmp (&label("${mode}_loop"));
}
&set_label("${mode}_exit"); }
&mov ("eax",1);
&lea ("esp",&DWP(4,"esp")); # popf
&emms () if ($mode eq "ctr32");
&set_label("${mode}_abort");
&function_end("padlock_${mode}_encrypt");
}
&generate_mode("ecb",0xc8);
&generate_mode("cbc",0xd0);
&generate_mode("cfb",0xe0);
&generate_mode("ofb",0xe8);
&generate_mode("ctr32",0xc8); # yes, it implements own CTR with ECB opcode,
# because hardware CTR was introduced later
# and even has errata on certain C7 stepping.
# own implementation *always* works, though
# ~15% slower than dedicated hardware...
&function_begin_B("padlock_xstore");
&push ("edi");
&mov ("edi",&wparam(0));
&mov ("edx",&wparam(1));
&data_byte(0x0f,0xa7,0xc0); # xstore
&pop ("edi");
&ret ();
&function_end_B("padlock_xstore");
&function_begin_B("_win32_segv_handler");
&mov ("eax",1); # ExceptionContinueSearch
&mov ("edx",&wparam(0)); # *ExceptionRecord
&mov ("ecx",&wparam(2)); # *ContextRecord
&cmp (&DWP(0,"edx"),0xC0000005) # ExceptionRecord->ExceptionCode == STATUS_ACCESS_VIOLATION
&jne (&label("ret"));
&add (&DWP(184,"ecx"),4); # skip over rep sha*
&mov ("eax",0); # ExceptionContinueExecution
&set_label("ret");
&ret ();
&function_end_B("_win32_segv_handler");
&safeseh("_win32_segv_handler") if ($::win32);
&function_begin_B("padlock_sha1_oneshot");
&push ("edi");
&push ("esi");
&xor ("eax","eax");
&mov ("edi",&wparam(0));
&mov ("esi",&wparam(1));
&mov ("ecx",&wparam(2));
if ($::win32 or $::coff) {
&push (&::islabel("_win32_segv_handler"));
&data_byte(0x64,0xff,0x30); # push %fs:(%eax)
&data_byte(0x64,0x89,0x20); # mov %esp,%fs:(%eax)
}
&mov ("edx","esp"); # put aside %esp
&add ("esp",-128); # 32 is enough but spec says 128
&movups ("xmm0",&QWP(0,"edi")); # copy-in context
&and ("esp",-16);
&mov ("eax",&DWP(16,"edi"));
&movaps (&QWP(0,"esp"),"xmm0");
&mov ("edi","esp");
&mov (&DWP(16,"esp"),"eax");
&xor ("eax","eax");
&data_byte(0xf3,0x0f,0xa6,0xc8); # rep xsha1
&movaps ("xmm0",&QWP(0,"esp"));
&mov ("eax",&DWP(16,"esp"));
&mov ("esp","edx"); # restore %esp
if ($::win32 or $::coff) {
&data_byte(0x64,0x8f,0x05,0,0,0,0); # pop %fs:0
&lea ("esp",&DWP(4,"esp"));
}
&mov ("edi",&wparam(0));
&movups (&QWP(0,"edi"),"xmm0"); # copy-out context
&mov (&DWP(16,"edi"),"eax");
&pop ("esi");
&pop ("edi");
&ret ();
&function_end_B("padlock_sha1_oneshot");
&function_begin_B("padlock_sha1_blocks");
&push ("edi");
&push ("esi");
&mov ("edi",&wparam(0));
&mov ("esi",&wparam(1));
&mov ("edx","esp"); # put aside %esp
&mov ("ecx",&wparam(2));
&add ("esp",-128);
&movups ("xmm0",&QWP(0,"edi")); # copy-in context
&and ("esp",-16);
&mov ("eax",&DWP(16,"edi"));
&movaps (&QWP(0,"esp"),"xmm0");
&mov ("edi","esp");
&mov (&DWP(16,"esp"),"eax");
&mov ("eax",-1);
&data_byte(0xf3,0x0f,0xa6,0xc8); # rep xsha1
&movaps ("xmm0",&QWP(0,"esp"));
&mov ("eax",&DWP(16,"esp"));
&mov ("esp","edx"); # restore %esp
&mov ("edi",&wparam(0));
&movups (&QWP(0,"edi"),"xmm0"); # copy-out context
&mov (&DWP(16,"edi"),"eax");
&pop ("esi");
&pop ("edi");
&ret ();
&function_end_B("padlock_sha1_blocks");
&function_begin_B("padlock_sha256_oneshot");
&push ("edi");
&push ("esi");
&xor ("eax","eax");
&mov ("edi",&wparam(0));
&mov ("esi",&wparam(1));
&mov ("ecx",&wparam(2));
if ($::win32 or $::coff) {
&push (&::islabel("_win32_segv_handler"));
&data_byte(0x64,0xff,0x30); # push %fs:(%eax)
&data_byte(0x64,0x89,0x20); # mov %esp,%fs:(%eax)
}
&mov ("edx","esp"); # put aside %esp
&add ("esp",-128);
&movups ("xmm0",&QWP(0,"edi")); # copy-in context
&and ("esp",-16);
&movups ("xmm1",&QWP(16,"edi"));
&movaps (&QWP(0,"esp"),"xmm0");
&mov ("edi","esp");
&movaps (&QWP(16,"esp"),"xmm1");
&xor ("eax","eax");
&data_byte(0xf3,0x0f,0xa6,0xd0); # rep xsha256
&movaps ("xmm0",&QWP(0,"esp"));
&movaps ("xmm1",&QWP(16,"esp"));
&mov ("esp","edx"); # restore %esp
if ($::win32 or $::coff) {
&data_byte(0x64,0x8f,0x05,0,0,0,0); # pop %fs:0
&lea ("esp",&DWP(4,"esp"));
}
&mov ("edi",&wparam(0));
&movups (&QWP(0,"edi"),"xmm0"); # copy-out context
&movups (&QWP(16,"edi"),"xmm1");
&pop ("esi");
&pop ("edi");
&ret ();
&function_end_B("padlock_sha256_oneshot");
&function_begin_B("padlock_sha256_blocks");
&push ("edi");
&push ("esi");
&mov ("edi",&wparam(0));
&mov ("esi",&wparam(1));
&mov ("ecx",&wparam(2));
&mov ("edx","esp"); # put aside %esp
&add ("esp",-128);
&movups ("xmm0",&QWP(0,"edi")); # copy-in context
&and ("esp",-16);
&movups ("xmm1",&QWP(16,"edi"));
&movaps (&QWP(0,"esp"),"xmm0");
&mov ("edi","esp");
&movaps (&QWP(16,"esp"),"xmm1");
&mov ("eax",-1);
&data_byte(0xf3,0x0f,0xa6,0xd0); # rep xsha256
&movaps ("xmm0",&QWP(0,"esp"));
&movaps ("xmm1",&QWP(16,"esp"));
&mov ("esp","edx"); # restore %esp
&mov ("edi",&wparam(0));
&movups (&QWP(0,"edi"),"xmm0"); # copy-out context
&movups (&QWP(16,"edi"),"xmm1");
&pop ("esi");
&pop ("edi");
&ret ();
&function_end_B("padlock_sha256_blocks");
&function_begin_B("padlock_sha512_blocks");
&push ("edi");
&push ("esi");
&mov ("edi",&wparam(0));
&mov ("esi",&wparam(1));
&mov ("ecx",&wparam(2));
&mov ("edx","esp"); # put aside %esp
&add ("esp",-128);
&movups ("xmm0",&QWP(0,"edi")); # copy-in context
&and ("esp",-16);
&movups ("xmm1",&QWP(16,"edi"));
&movups ("xmm2",&QWP(32,"edi"));
&movups ("xmm3",&QWP(48,"edi"));
&movaps (&QWP(0,"esp"),"xmm0");
&mov ("edi","esp");
&movaps (&QWP(16,"esp"),"xmm1");
&movaps (&QWP(32,"esp"),"xmm2");
&movaps (&QWP(48,"esp"),"xmm3");
&data_byte(0xf3,0x0f,0xa6,0xe0); # rep xsha512
&movaps ("xmm0",&QWP(0,"esp"));
&movaps ("xmm1",&QWP(16,"esp"));
&movaps ("xmm2",&QWP(32,"esp"));
&movaps ("xmm3",&QWP(48,"esp"));
&mov ("esp","edx"); # restore %esp
&mov ("edi",&wparam(0));
&movups (&QWP(0,"edi"),"xmm0"); # copy-out context
&movups (&QWP(16,"edi"),"xmm1");
&movups (&QWP(32,"edi"),"xmm2");
&movups (&QWP(48,"edi"),"xmm3");
&pop ("esi");
&pop ("edi");
&ret ();
&function_end_B("padlock_sha512_blocks");
&asciz ("VIA Padlock x86 module, CRYPTOGAMS by <appro\@openssl.org>");
&align (16);
&dataseg();
# Essentially this variable belongs in thread local storage.
# Having this variable global on the other hand can only cause
# few bogus key reloads [if any at all on signle-CPU system],
# so we accept the penalty...
&set_label("padlock_saved_context",4);
&data_word(0);
&asm_finish();
close STDOUT;
|
{
"language": "Assembly"
}
|
; RUN: llc < %s -filetype=obj | llvm-readobj - --codeview | FileCheck %s
; RUN: llc < %s | llvm-mc -filetype=obj --triple=x86_64-windows | llvm-readobj - --codeview | FileCheck %s
; RUN: llc < %s | FileCheck %s --check-prefix=ASM-INLINE-COMMENTS
;
; Command to generate function-options.ll
; $ clang++ class-options-common.cpp -S -emit-llvm -g -gcodeview -o class-options-common.ll
; // Basically, there are two Property (class-options) expectations on each type:
; // One for class forwarding reference, the other for class definition.
;
; #define DEFINE_FUNCTION(T) \
; T Func_##T(T &arg) { return arg; };
;
; class EmptyClass {}; // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasUniqueName
; DEFINE_FUNCTION(EmptyClass);
;
; class ExplicitCtorClass { // Expect CO = ForwardReference | HasUniqueName
; // Expect CO = HasConstructorOrDestructor | HasUniqueName
; public:
; explicit ExplicitCtorClass();
; };
; DEFINE_FUNCTION(ExplicitCtorClass);
;
; class DefaultedCtorClass { // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasUniqueName
; public:
; DefaultedCtorClass() = default;
; };
; DEFINE_FUNCTION(DefaultedCtorClass);
;
; class DefaultArgumentCtorClass { // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasConstructorOrDestructor | HasUniqueName
; public:
; DefaultArgumentCtorClass(int x = 0);
; };
; DEFINE_FUNCTION(DefaultArgumentCtorClass);
;
; class UserDtorClass { // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasConstructorOrDestructor| HasUniqueName
; public:
; ~UserDtorClass() {}
; };
; DEFINE_FUNCTION(UserDtorClass);
;
; class DefaultedDtorClass { // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasUniqueName
; public:
; ~DefaultedDtorClass() = default;
; };
; DEFINE_FUNCTION(DefaultedDtorClass);
;
; class AClass : public ExplicitCtorClass { // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasConstructorOrDestructor | HasUniqueName
; };
; DEFINE_FUNCTION(AClass);
;
; class BClass { static int x; }; // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasUniqueName
; DEFINE_FUNCTION(BClass);
;
; struct Foo { // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasUniqueName
; Foo() = default;
; Foo(const Foo &o) = default;
; int m;
; } f;
;
; struct Bar { // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasConstructorOrDestructor | HasUniqueName
; int m = 0;
; } b;
;
; struct AStruct {}; // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasUniqueName
; DEFINE_FUNCTION(AStruct);
;
; struct BStruct { BStruct(); }; // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasConstructorOrDestructor | HasUniqueName
; DEFINE_FUNCTION(BStruct);
;
; void S() {
; struct ComplexStruct { // Expect: CO = ForwardReference | HasUniqueName | Scoped
; // Expect: CO = ContainsNestedClass | HasConstructorOrDestructor | HasUniqueName | Scoped
;
;
; struct S {}; // Expect: CO = ForwardReference | HasUniqueName | Nested | Scoped
; // Expect: CO = HasUniqueName | Nested | Scoped
;
; S s;
; };
; ComplexStruct s;
; }
;
; union AUnion {}; // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasUniqueName | Sealed
; DEFINE_FUNCTION(AUnion);
;
; union BUnion { BUnion() = default; }; // Expect: CO = ForwardReference | HasUniqueName
; // Expect: CO = HasUniqueName | Sealed
; DEFINE_FUNCTION(BUnion);
;
; void U() {
; union ComplexUnion { // Note clang not yiled 'HasUniqueName' for this type, but MSVC does.
; // Expect: CO = ForwardReference | Scoped
; // Expect: CO = ContainsNestedClass | Scoped | Sealed
;
; union NestedUnion { int x; }; // Note clang not yiled 'HasUniqueName' for this type, but MSVC does.
; // Expect: CO = ForwardReference | Nested | Scoped
; // Expect: CO = Nested | Scoped | Sealed
; NestedUnion a;
; int b;
; };
; ComplexUnion c;
; }
; CHECK: Format: COFF-x86-64
; CHECK: Arch: x86_64
; CHECK: AddressSize: 64bit
; CHECK: CodeViewTypes [
; CHECK: Section: .debug$T ({{.*}})
; CHECK: Magic: 0x4
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: EmptyClass
; CHECK: LinkageName: .?AVEmptyClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x200)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: EmptyClass
; CHECK: LinkageName: .?AVEmptyClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: ExplicitCtorClass
; CHECK: LinkageName: .?AVExplicitCtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x202)
; CHECK: HasConstructorOrDestructor (0x2)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: ExplicitCtorClass
; CHECK: LinkageName: .?AVExplicitCtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: DefaultedCtorClass
; CHECK: LinkageName: .?AVDefaultedCtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x200)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: DefaultedCtorClass
; CHECK: LinkageName: .?AVDefaultedCtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: DefaultArgumentCtorClass
; CHECK: LinkageName: .?AVDefaultArgumentCtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x202)
; CHECK: HasConstructorOrDestructor (0x2)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: DefaultArgumentCtorClass
; CHECK: LinkageName: .?AVDefaultArgumentCtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: UserDtorClass
; CHECK: LinkageName: .?AVUserDtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x202)
; CHECK: HasConstructorOrDestructor (0x2)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: UserDtorClass
; CHECK: LinkageName: .?AVUserDtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: DefaultedDtorClass
; CHECK: LinkageName: .?AVDefaultedDtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x200)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: DefaultedDtorClass
; CHECK: LinkageName: .?AVDefaultedDtorClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: AClass
; CHECK: LinkageName: .?AVAClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x202)
; CHECK: HasConstructorOrDestructor (0x2)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: AClass
; CHECK: LinkageName: .?AVAClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: BClass
; CHECK: LinkageName: .?AVBClass@@
; CHECK: }
; CHECK: Class (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_CLASS (0x1504)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x200)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: BClass
; CHECK: LinkageName: .?AVBClass@@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: AStruct
; CHECK: LinkageName: .?AUAStruct@@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x200)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: AStruct
; CHECK: LinkageName: .?AUAStruct@@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: BStruct
; CHECK: LinkageName: .?AUBStruct@@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x202)
; CHECK: HasConstructorOrDestructor (0x2)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: BStruct
; CHECK: LinkageName: .?AUBStruct@@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x380)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: Scoped (0x100)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: S::ComplexStruct
; CHECK: LinkageName: .?AUComplexStruct@?1??S@@YAXXZ@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x388)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: Nested (0x8)
; CHECK: Scoped (0x100)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: S::ComplexStruct::S
; CHECK: LinkageName: .?AUS@ComplexStruct@?1??0@YAXXZ@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 2
; CHECK: Properties [ (0x310)
; CHECK: ContainsNestedClass (0x10)
; CHECK: HasUniqueName (0x200)
; CHECK: Scoped (0x100)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: S::ComplexStruct
; CHECK: LinkageName: .?AUComplexStruct@?1??S@@YAXXZ@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x308)
; CHECK: HasUniqueName (0x200)
; CHECK: Nested (0x8)
; CHECK: Scoped (0x100)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 1
; CHECK: Name: S::ComplexStruct::S
; CHECK: LinkageName: .?AUS@ComplexStruct@?1??0@YAXXZ@
; CHECK: }
; CHECK: Union (0x1067) {
; CHECK: TypeLeafKind: LF_UNION (0x1506)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: AUnion
; CHECK: LinkageName: .?ATAUnion@@
; CHECK: }
; CHECK: Union (0x106B) {
; CHECK: TypeLeafKind: LF_UNION (0x1506)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x600)
; CHECK: HasUniqueName (0x200)
; CHECK: Sealed (0x400)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: SizeOf: 1
; CHECK: Name: AUnion
; CHECK: LinkageName: .?ATAUnion@@
; CHECK: }
; CHECK: Union (0x106E) {
; CHECK: TypeLeafKind: LF_UNION (0x1506)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: BUnion
; CHECK: LinkageName: .?ATBUnion@@
; CHECK: }
; CHECK: Union (0x1075) {
; CHECK: TypeLeafKind: LF_UNION (0x1506)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x600)
; CHECK: HasUniqueName (0x200)
; CHECK: Sealed (0x400)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: SizeOf: 1
; CHECK: Name: BUnion
; CHECK: LinkageName: .?ATBUnion@@
; CHECK: }
; CHECK: Union (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_UNION (0x1506)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x380)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: Scoped (0x100)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: U::ComplexUnion
; CHECK: LinkageName: .?ATComplexUnion@?1??U@@YAXXZ@
; CHECK: }
; CHECK: Union (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_UNION (0x1506)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x388)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: Nested (0x8)
; CHECK: Scoped (0x100)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: U::ComplexUnion::NestedUnion
; CHECK: LinkageName: .?ATNestedUnion@ComplexUnion@?1??U@@YAXXZ@
; CHECK: }
; CHECK: Union (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_UNION (0x1506)
; CHECK: MemberCount: 3
; CHECK: Properties [ (0x710)
; CHECK: ContainsNestedClass (0x10)
; CHECK: HasUniqueName (0x200)
; CHECK: Scoped (0x100)
; CHECK: Sealed (0x400)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: SizeOf: 4
; CHECK: Name: U::ComplexUnion
; CHECK: LinkageName: .?ATComplexUnion@?1??U@@YAXXZ@
; CHECK: }
; CHECK: Union (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_UNION (0x1506)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x708)
; CHECK: HasUniqueName (0x200)
; CHECK: Nested (0x8)
; CHECK: Scoped (0x100)
; CHECK: Sealed (0x400)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: SizeOf: 4
; CHECK: Name: U::ComplexUnion::NestedUnion
; CHECK: LinkageName: .?ATNestedUnion@ComplexUnion@?1??U@@YAXXZ@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: Foo
; CHECK: LinkageName: .?AUFoo@@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 3
; CHECK: Properties [ (0x200)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 4
; CHECK: Name: Foo
; CHECK: LinkageName: .?AUFoo@@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 0
; CHECK: Properties [ (0x280)
; CHECK: ForwardReference (0x80)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: 0x0
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 0
; CHECK: Name: Bar
; CHECK: LinkageName: .?AUBar@@
; CHECK: }
; CHECK: Struct (0x{{.*}}) {
; CHECK: TypeLeafKind: LF_STRUCTURE (0x1505)
; CHECK: MemberCount: 1
; CHECK: Properties [ (0x202)
; CHECK: HasConstructorOrDestructor (0x2)
; CHECK: HasUniqueName (0x200)
; CHECK: ]
; CHECK: FieldList: <field list> (0x{{.*}})
; CHECK: DerivedFrom: 0x0
; CHECK: VShape: 0x0
; CHECK: SizeOf: 4
; CHECK: Name: Bar
; CHECK: LinkageName: .?AUBar@@
; CHECK: }
; CHECK: ]
; ASM-INLINE-COMMENTS: # MethodOverloadList (0x1088)
; ASM-INLINE-COMMENTS: .short 0x12 # Record length
; ASM-INLINE-COMMENTS: .short 0x1206 # Record kind: LF_METHODLIST
; ASM-INLINE-COMMENTS: .short 0x3 # Method
; ASM-INLINE-COMMENTS: # Attrs: Public
; ASM-INLINE-COMMENTS: .short 0x0
; ASM-INLINE-COMMENTS: .long 0x1083 # Type: void Foo::()
; ASM-INLINE-COMMENTS: .short 0x3 # Attrs: Public
; ASM-INLINE-COMMENTS: .short 0x0
; ASM-INLINE-COMMENTS: .long 0x1087 # Type: void Foo::(const Foo&)
; ModuleID = 'class-options-common.cpp'
source_filename = "class-options.cpp"
target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-windows-msvc19.15.26729"
%struct.Foo = type { i32 }
%struct.Bar = type { i32 }
%class.EmptyClass = type { i8 }
%class.ExplicitCtorClass = type { i8 }
%class.DefaultedCtorClass = type { i8 }
%class.DefaultArgumentCtorClass = type { i8 }
%class.UserDtorClass = type { i8 }
%class.DefaultedDtorClass = type { i8 }
%class.AClass = type { i8 }
%class.BClass = type { i8 }
%struct.AStruct = type { i8 }
%struct.BStruct = type { i8 }
%struct.ComplexStruct = type { %"struct.S()::ComplexStruct::S" }
%"struct.S()::ComplexStruct::S" = type { i8 }
%union.AUnion = type { i8 }
%union.BUnion = type { i8 }
%union.ComplexUnion = type { %"union.U()::ComplexUnion::NestedUnion" }
%"union.U()::ComplexUnion::NestedUnion" = type { i32 }
@"?f@@3UFoo@@A" = dso_local global %struct.Foo zeroinitializer, align 4, !dbg !0
@"?b@@3UBar@@A" = dso_local global %struct.Bar zeroinitializer, align 4, !dbg !6
; Function Attrs: noinline nounwind optnone uwtable
define dso_local i8 @"?Func_EmptyClass@@YA?AVEmptyClass@@AEAV1@@Z"(%class.EmptyClass* dereferenceable(1) %arg) #0 !dbg !30 {
entry:
%retval = alloca %class.EmptyClass, align 1
%arg.addr = alloca %class.EmptyClass*, align 8
store %class.EmptyClass* %arg, %class.EmptyClass** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %class.EmptyClass** %arg.addr, metadata !35, metadata !DIExpression()), !dbg !36
%0 = load %class.EmptyClass*, %class.EmptyClass** %arg.addr, align 8, !dbg !36
%coerce.dive = getelementptr inbounds %class.EmptyClass, %class.EmptyClass* %retval, i32 0, i32 0, !dbg !36
%1 = load i8, i8* %coerce.dive, align 1, !dbg !36
ret i8 %1, !dbg !36
}
; Function Attrs: nounwind readnone speculatable
declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?Func_ExplicitCtorClass@@YA?AVExplicitCtorClass@@AEAV1@@Z"(%class.ExplicitCtorClass* noalias sret %agg.result, %class.ExplicitCtorClass* dereferenceable(1) %arg) #0 !dbg !37 {
entry:
%arg.addr = alloca %class.ExplicitCtorClass*, align 8
store %class.ExplicitCtorClass* %arg, %class.ExplicitCtorClass** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %class.ExplicitCtorClass** %arg.addr, metadata !47, metadata !DIExpression()), !dbg !48
%0 = load %class.ExplicitCtorClass*, %class.ExplicitCtorClass** %arg.addr, align 8, !dbg !48
ret void, !dbg !48
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?Func_DefaultedCtorClass@@YA?AVDefaultedCtorClass@@AEAV1@@Z"(%class.DefaultedCtorClass* noalias sret %agg.result, %class.DefaultedCtorClass* dereferenceable(1) %arg) #0 !dbg !49 {
entry:
%arg.addr = alloca %class.DefaultedCtorClass*, align 8
store %class.DefaultedCtorClass* %arg, %class.DefaultedCtorClass** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %class.DefaultedCtorClass** %arg.addr, metadata !59, metadata !DIExpression()), !dbg !60
%0 = load %class.DefaultedCtorClass*, %class.DefaultedCtorClass** %arg.addr, align 8, !dbg !60
ret void, !dbg !60
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?Func_DefaultArgumentCtorClass@@YA?AVDefaultArgumentCtorClass@@AEAV1@@Z"(%class.DefaultArgumentCtorClass* noalias sret %agg.result, %class.DefaultArgumentCtorClass* dereferenceable(1) %arg) #0 !dbg !61 {
entry:
%arg.addr = alloca %class.DefaultArgumentCtorClass*, align 8
store %class.DefaultArgumentCtorClass* %arg, %class.DefaultArgumentCtorClass** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %class.DefaultArgumentCtorClass** %arg.addr, metadata !71, metadata !DIExpression()), !dbg !72
%0 = load %class.DefaultArgumentCtorClass*, %class.DefaultArgumentCtorClass** %arg.addr, align 8, !dbg !72
ret void, !dbg !72
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?Func_UserDtorClass@@YA?AVUserDtorClass@@AEAV1@@Z"(%class.UserDtorClass* noalias sret %agg.result, %class.UserDtorClass* dereferenceable(1) %arg) #0 !dbg !73 {
entry:
%arg.addr = alloca %class.UserDtorClass*, align 8
store %class.UserDtorClass* %arg, %class.UserDtorClass** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %class.UserDtorClass** %arg.addr, metadata !83, metadata !DIExpression()), !dbg !84
%0 = load %class.UserDtorClass*, %class.UserDtorClass** %arg.addr, align 8, !dbg !84
ret void, !dbg !84
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?Func_DefaultedDtorClass@@YA?AVDefaultedDtorClass@@AEAV1@@Z"(%class.DefaultedDtorClass* noalias sret %agg.result, %class.DefaultedDtorClass* dereferenceable(1) %arg) #0 !dbg !85 {
entry:
%arg.addr = alloca %class.DefaultedDtorClass*, align 8
store %class.DefaultedDtorClass* %arg, %class.DefaultedDtorClass** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %class.DefaultedDtorClass** %arg.addr, metadata !95, metadata !DIExpression()), !dbg !96
%0 = load %class.DefaultedDtorClass*, %class.DefaultedDtorClass** %arg.addr, align 8, !dbg !96
ret void, !dbg !96
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?Func_AClass@@YA?AVAClass@@AEAV1@@Z"(%class.AClass* noalias sret %agg.result, %class.AClass* dereferenceable(1) %arg) #0 !dbg !97 {
entry:
%arg.addr = alloca %class.AClass*, align 8
store %class.AClass* %arg, %class.AClass** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %class.AClass** %arg.addr, metadata !104, metadata !DIExpression()), !dbg !105
%0 = load %class.AClass*, %class.AClass** %arg.addr, align 8, !dbg !105
ret void, !dbg !105
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local i8 @"?Func_BClass@@YA?AVBClass@@AEAV1@@Z"(%class.BClass* dereferenceable(1) %arg) #0 !dbg !106 {
entry:
%retval = alloca %class.BClass, align 1
%arg.addr = alloca %class.BClass*, align 8
store %class.BClass* %arg, %class.BClass** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %class.BClass** %arg.addr, metadata !113, metadata !DIExpression()), !dbg !114
%0 = load %class.BClass*, %class.BClass** %arg.addr, align 8, !dbg !114
%coerce.dive = getelementptr inbounds %class.BClass, %class.BClass* %retval, i32 0, i32 0, !dbg !114
%1 = load i8, i8* %coerce.dive, align 1, !dbg !114
ret i8 %1, !dbg !114
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local i8 @"?Func_AStruct@@YA?AUAStruct@@AEAU1@@Z"(%struct.AStruct* dereferenceable(1) %arg) #0 !dbg !115 {
entry:
%retval = alloca %struct.AStruct, align 1
%arg.addr = alloca %struct.AStruct*, align 8
store %struct.AStruct* %arg, %struct.AStruct** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %struct.AStruct** %arg.addr, metadata !120, metadata !DIExpression()), !dbg !121
%0 = load %struct.AStruct*, %struct.AStruct** %arg.addr, align 8, !dbg !121
%coerce.dive = getelementptr inbounds %struct.AStruct, %struct.AStruct* %retval, i32 0, i32 0, !dbg !121
%1 = load i8, i8* %coerce.dive, align 1, !dbg !121
ret i8 %1, !dbg !121
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?Func_BStruct@@YA?AUBStruct@@AEAU1@@Z"(%struct.BStruct* noalias sret %agg.result, %struct.BStruct* dereferenceable(1) %arg) #0 !dbg !122 {
entry:
%arg.addr = alloca %struct.BStruct*, align 8
store %struct.BStruct* %arg, %struct.BStruct** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %struct.BStruct** %arg.addr, metadata !132, metadata !DIExpression()), !dbg !133
%0 = load %struct.BStruct*, %struct.BStruct** %arg.addr, align 8, !dbg !133
ret void, !dbg !133
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?S@@YAXXZ"() #0 !dbg !134 {
entry:
%s = alloca %struct.ComplexStruct, align 1
call void @llvm.dbg.declare(metadata %struct.ComplexStruct* %s, metadata !137, metadata !DIExpression()), !dbg !142
ret void, !dbg !143
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local i8 @"?Func_AUnion@@YA?ATAUnion@@AEAT1@@Z"(%union.AUnion* dereferenceable(1) %arg) #0 !dbg !144 {
entry:
%retval = alloca %union.AUnion, align 1
%arg.addr = alloca %union.AUnion*, align 8
store %union.AUnion* %arg, %union.AUnion** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %union.AUnion** %arg.addr, metadata !149, metadata !DIExpression()), !dbg !150
%0 = load %union.AUnion*, %union.AUnion** %arg.addr, align 8, !dbg !150
%coerce.dive = getelementptr inbounds %union.AUnion, %union.AUnion* %retval, i32 0, i32 0, !dbg !150
%1 = load i8, i8* %coerce.dive, align 1, !dbg !150
ret i8 %1, !dbg !150
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?Func_BUnion@@YA?ATBUnion@@AEAT1@@Z"(%union.BUnion* noalias sret %agg.result, %union.BUnion* dereferenceable(1) %arg) #0 !dbg !151 {
entry:
%arg.addr = alloca %union.BUnion*, align 8
store %union.BUnion* %arg, %union.BUnion** %arg.addr, align 8
call void @llvm.dbg.declare(metadata %union.BUnion** %arg.addr, metadata !161, metadata !DIExpression()), !dbg !162
%0 = load %union.BUnion*, %union.BUnion** %arg.addr, align 8, !dbg !162
ret void, !dbg !162
}
; Function Attrs: noinline nounwind optnone uwtable
define dso_local void @"?U@@YAXXZ"() #0 !dbg !163 {
entry:
%c = alloca %union.ComplexUnion, align 4
call void @llvm.dbg.declare(metadata %union.ComplexUnion* %c, metadata !164, metadata !DIExpression()), !dbg !172
ret void, !dbg !173
}
attributes #0 = { noinline nounwind optnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone speculatable }
!llvm.dbg.cu = !{!2}
!llvm.module.flags = !{!25, !26, !27, !28}
!llvm.ident = !{!29}
!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
!1 = distinct !DIGlobalVariable(name: "f", linkageName: "?f@@3UFoo@@A", scope: !2, file: !8, line: 60, type: !13, isLocal: false, isDefinition: true)
!2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, producer: "clang version 8.0.0 ", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, nameTableKind: None)
!3 = !DIFile(filename: "class-options-common.cpp", directory: "D:\5Cupstream\5Cllvm\5Ctest\5CDebugInfo\5CCOFF", checksumkind: CSK_MD5, checksum: "73d5c55a09899333f27526ae5ea8c878")
!4 = !{}
!5 = !{!0, !6}
!6 = !DIGlobalVariableExpression(var: !7, expr: !DIExpression())
!7 = distinct !DIGlobalVariable(name: "b", linkageName: "?b@@3UBar@@A", scope: !2, file: !8, line: 65, type: !9, isLocal: false, isDefinition: true)
!8 = !DIFile(filename: "class-options.cpp", directory: "D:\5Cupstream\5Cllvm\5Ctest\5CDebugInfo\5CCOFF")
!9 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Bar", file: !8, line: 62, size: 32, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !10, identifier: ".?AUBar@@")
!10 = !{!11}
!11 = !DIDerivedType(tag: DW_TAG_member, name: "m", scope: !9, file: !8, line: 64, baseType: !12, size: 32)
!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Foo", file: !8, line: 55, size: 32, flags: DIFlagTypePassByValue, elements: !14, identifier: ".?AUFoo@@")
!14 = !{!15, !16, !20}
!15 = !DIDerivedType(tag: DW_TAG_member, name: "m", scope: !13, file: !8, line: 59, baseType: !12, size: 32)
!16 = !DISubprogram(name: "Foo", scope: !13, file: !8, line: 57, type: !17, isLocal: false, isDefinition: false, scopeLine: 57, flags: DIFlagPrototyped, isOptimized: false)
!17 = !DISubroutineType(types: !18)
!18 = !{null, !19}
!19 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
!20 = !DISubprogram(name: "Foo", scope: !13, file: !8, line: 58, type: !21, isLocal: false, isDefinition: false, scopeLine: 58, flags: DIFlagPrototyped, isOptimized: false)
!21 = !DISubroutineType(types: !22)
!22 = !{null, !19, !23}
!23 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !24, size: 64)
!24 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !13)
!25 = !{i32 2, !"CodeView", i32 1}
!26 = !{i32 2, !"Debug Info Version", i32 3}
!27 = !{i32 1, !"wchar_size", i32 2}
!28 = !{i32 7, !"PIC Level", i32 2}
!29 = !{!"clang version 8.0.0 "}
!30 = distinct !DISubprogram(name: "Func_EmptyClass", linkageName: "?Func_EmptyClass@@YA?AVEmptyClass@@AEAV1@@Z", scope: !8, file: !8, line: 9, type: !31, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!31 = !DISubroutineType(types: !32)
!32 = !{!33, !34}
!33 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "EmptyClass", file: !8, line: 7, size: 8, flags: DIFlagTypePassByValue, elements: !4, identifier: ".?AVEmptyClass@@")
!34 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !33, size: 64)
!35 = !DILocalVariable(name: "arg", arg: 1, scope: !30, file: !8, line: 9, type: !34)
!36 = !DILocation(line: 9, scope: !30)
!37 = distinct !DISubprogram(name: "Func_ExplicitCtorClass", linkageName: "?Func_ExplicitCtorClass@@YA?AVExplicitCtorClass@@AEAV1@@Z", scope: !8, file: !8, line: 16, type: !38, isLocal: false, isDefinition: true, scopeLine: 16, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!38 = !DISubroutineType(types: !39)
!39 = !{!40, !46}
!40 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "ExplicitCtorClass", file: !8, line: 11, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !41, identifier: ".?AVExplicitCtorClass@@")
!41 = !{!42}
!42 = !DISubprogram(name: "ExplicitCtorClass", scope: !40, file: !8, line: 14, type: !43, isLocal: false, isDefinition: false, scopeLine: 14, flags: DIFlagPublic | DIFlagExplicit | DIFlagPrototyped, isOptimized: false)
!43 = !DISubroutineType(types: !44)
!44 = !{null, !45}
!45 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !40, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
!46 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !40, size: 64)
!47 = !DILocalVariable(name: "arg", arg: 1, scope: !37, file: !8, line: 16, type: !46)
!48 = !DILocation(line: 16, scope: !37)
!49 = distinct !DISubprogram(name: "Func_DefaultedCtorClass", linkageName: "?Func_DefaultedCtorClass@@YA?AVDefaultedCtorClass@@AEAV1@@Z", scope: !8, file: !8, line: 23, type: !50, isLocal: false, isDefinition: true, scopeLine: 23, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!50 = !DISubroutineType(types: !51)
!51 = !{!52, !58}
!52 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "DefaultedCtorClass", file: !8, line: 18, size: 8, flags: DIFlagTypePassByValue, elements: !53, identifier: ".?AVDefaultedCtorClass@@")
!53 = !{!54}
!54 = !DISubprogram(name: "DefaultedCtorClass", scope: !52, file: !8, line: 21, type: !55, isLocal: false, isDefinition: false, scopeLine: 21, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false)
!55 = !DISubroutineType(types: !56)
!56 = !{null, !57}
!57 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !52, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
!58 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !52, size: 64)
!59 = !DILocalVariable(name: "arg", arg: 1, scope: !49, file: !8, line: 23, type: !58)
!60 = !DILocation(line: 23, scope: !49)
!61 = distinct !DISubprogram(name: "Func_DefaultArgumentCtorClass", linkageName: "?Func_DefaultArgumentCtorClass@@YA?AVDefaultArgumentCtorClass@@AEAV1@@Z", scope: !8, file: !8, line: 30, type: !62, isLocal: false, isDefinition: true, scopeLine: 30, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!62 = !DISubroutineType(types: !63)
!63 = !{!64, !70}
!64 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "DefaultArgumentCtorClass", file: !8, line: 25, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !65, identifier: ".?AVDefaultArgumentCtorClass@@")
!65 = !{!66}
!66 = !DISubprogram(name: "DefaultArgumentCtorClass", scope: !64, file: !8, line: 28, type: !67, isLocal: false, isDefinition: false, scopeLine: 28, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false)
!67 = !DISubroutineType(types: !68)
!68 = !{null, !69, !12}
!69 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !64, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
!70 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !64, size: 64)
!71 = !DILocalVariable(name: "arg", arg: 1, scope: !61, file: !8, line: 30, type: !70)
!72 = !DILocation(line: 30, scope: !61)
!73 = distinct !DISubprogram(name: "Func_UserDtorClass", linkageName: "?Func_UserDtorClass@@YA?AVUserDtorClass@@AEAV1@@Z", scope: !8, file: !8, line: 37, type: !74, isLocal: false, isDefinition: true, scopeLine: 37, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!74 = !DISubroutineType(types: !75)
!75 = !{!76, !82}
!76 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "UserDtorClass", file: !8, line: 32, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !77, identifier: ".?AVUserDtorClass@@")
!77 = !{!78}
!78 = !DISubprogram(name: "~UserDtorClass", scope: !76, file: !8, line: 35, type: !79, isLocal: false, isDefinition: false, scopeLine: 35, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false)
!79 = !DISubroutineType(types: !80)
!80 = !{null, !81}
!81 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !76, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
!82 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !76, size: 64)
!83 = !DILocalVariable(name: "arg", arg: 1, scope: !73, file: !8, line: 37, type: !82)
!84 = !DILocation(line: 37, scope: !73)
!85 = distinct !DISubprogram(name: "Func_DefaultedDtorClass", linkageName: "?Func_DefaultedDtorClass@@YA?AVDefaultedDtorClass@@AEAV1@@Z", scope: !8, file: !8, line: 44, type: !86, isLocal: false, isDefinition: true, scopeLine: 44, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!86 = !DISubroutineType(types: !87)
!87 = !{!88, !94}
!88 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "DefaultedDtorClass", file: !8, line: 39, size: 8, flags: DIFlagTypePassByValue, elements: !89, identifier: ".?AVDefaultedDtorClass@@")
!89 = !{!90}
!90 = !DISubprogram(name: "~DefaultedDtorClass", scope: !88, file: !8, line: 42, type: !91, isLocal: false, isDefinition: false, scopeLine: 42, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: false)
!91 = !DISubroutineType(types: !92)
!92 = !{null, !93}
!93 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !88, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
!94 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !88, size: 64)
!95 = !DILocalVariable(name: "arg", arg: 1, scope: !85, file: !8, line: 44, type: !94)
!96 = !DILocation(line: 44, scope: !85)
!97 = distinct !DISubprogram(name: "Func_AClass", linkageName: "?Func_AClass@@YA?AVAClass@@AEAV1@@Z", scope: !8, file: !8, line: 49, type: !98, isLocal: false, isDefinition: true, scopeLine: 49, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!98 = !DISubroutineType(types: !99)
!99 = !{!100, !103}
!100 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "AClass", file: !8, line: 46, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !101, identifier: ".?AVAClass@@")
!101 = !{!102}
!102 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !100, baseType: !40, flags: DIFlagPublic, extraData: i32 0)
!103 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !100, size: 64)
!104 = !DILocalVariable(name: "arg", arg: 1, scope: !97, file: !8, line: 49, type: !103)
!105 = !DILocation(line: 49, scope: !97)
!106 = distinct !DISubprogram(name: "Func_BClass", linkageName: "?Func_BClass@@YA?AVBClass@@AEAV1@@Z", scope: !8, file: !8, line: 53, type: !107, isLocal: false, isDefinition: true, scopeLine: 53, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!107 = !DISubroutineType(types: !108)
!108 = !{!109, !112}
!109 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "BClass", file: !8, line: 51, size: 8, flags: DIFlagTypePassByValue, elements: !110, identifier: ".?AVBClass@@")
!110 = !{!111}
!111 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !109, file: !8, line: 51, baseType: !12, flags: DIFlagStaticMember)
!112 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !109, size: 64)
!113 = !DILocalVariable(name: "arg", arg: 1, scope: !106, file: !8, line: 53, type: !112)
!114 = !DILocation(line: 53, scope: !106)
!115 = distinct !DISubprogram(name: "Func_AStruct", linkageName: "?Func_AStruct@@YA?AUAStruct@@AEAU1@@Z", scope: !8, file: !8, line: 69, type: !116, isLocal: false, isDefinition: true, scopeLine: 69, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!116 = !DISubroutineType(types: !117)
!117 = !{!118, !119}
!118 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "AStruct", file: !8, line: 67, size: 8, flags: DIFlagTypePassByValue, elements: !4, identifier: ".?AUAStruct@@")
!119 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !118, size: 64)
!120 = !DILocalVariable(name: "arg", arg: 1, scope: !115, file: !8, line: 69, type: !119)
!121 = !DILocation(line: 69, scope: !115)
!122 = distinct !DISubprogram(name: "Func_BStruct", linkageName: "?Func_BStruct@@YA?AUBStruct@@AEAU1@@Z", scope: !8, file: !8, line: 73, type: !123, isLocal: false, isDefinition: true, scopeLine: 73, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!123 = !DISubroutineType(types: !124)
!124 = !{!125, !131}
!125 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "BStruct", file: !8, line: 71, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !126, identifier: ".?AUBStruct@@")
!126 = !{!127}
!127 = !DISubprogram(name: "BStruct", scope: !125, file: !8, line: 71, type: !128, isLocal: false, isDefinition: false, scopeLine: 71, flags: DIFlagPrototyped, isOptimized: false)
!128 = !DISubroutineType(types: !129)
!129 = !{null, !130}
!130 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !125, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
!131 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !125, size: 64)
!132 = !DILocalVariable(name: "arg", arg: 1, scope: !122, file: !8, line: 73, type: !131)
!133 = !DILocation(line: 73, scope: !122)
!134 = distinct !DISubprogram(name: "S", linkageName: "?S@@YAXXZ", scope: !8, file: !8, line: 75, type: !135, isLocal: false, isDefinition: true, scopeLine: 75, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!135 = !DISubroutineType(types: !136)
!136 = !{null}
!137 = !DILocalVariable(name: "s", scope: !134, file: !8, line: 85, type: !138)
!138 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "ComplexStruct", scope: !134, file: !8, line: 76, size: 8, flags: DIFlagTypePassByValue, elements: !139, identifier: ".?AUComplexStruct@?1??S@@YAXXZ@")
!139 = !{!140, !141}
!140 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S", scope: !138, file: !8, line: 80, size: 8, flags: DIFlagTypePassByValue, elements: !4, identifier: ".?AUS@ComplexStruct@?1??0@YAXXZ@")
!141 = !DIDerivedType(tag: DW_TAG_member, name: "s", scope: !138, file: !8, line: 83, baseType: !140, size: 8)
!142 = !DILocation(line: 85, scope: !134)
!143 = !DILocation(line: 86, scope: !134)
!144 = distinct !DISubprogram(name: "Func_AUnion", linkageName: "?Func_AUnion@@YA?ATAUnion@@AEAT1@@Z", scope: !8, file: !8, line: 90, type: !145, isLocal: false, isDefinition: true, scopeLine: 90, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!145 = !DISubroutineType(types: !146)
!146 = !{!147, !148}
!147 = distinct !DICompositeType(tag: DW_TAG_union_type, name: "AUnion", file: !8, line: 88, size: 8, flags: DIFlagTypePassByValue, elements: !4, identifier: ".?ATAUnion@@")
!148 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !147, size: 64)
!149 = !DILocalVariable(name: "arg", arg: 1, scope: !144, file: !8, line: 90, type: !148)
!150 = !DILocation(line: 90, scope: !144)
!151 = distinct !DISubprogram(name: "Func_BUnion", linkageName: "?Func_BUnion@@YA?ATBUnion@@AEAT1@@Z", scope: !8, file: !8, line: 94, type: !152, isLocal: false, isDefinition: true, scopeLine: 94, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!152 = !DISubroutineType(types: !153)
!153 = !{!154, !160}
!154 = distinct !DICompositeType(tag: DW_TAG_union_type, name: "BUnion", file: !8, line: 92, size: 8, flags: DIFlagTypePassByValue, elements: !155, identifier: ".?ATBUnion@@")
!155 = !{!156}
!156 = !DISubprogram(name: "BUnion", scope: !154, file: !8, line: 92, type: !157, isLocal: false, isDefinition: false, scopeLine: 92, flags: DIFlagPrototyped, isOptimized: false)
!157 = !DISubroutineType(types: !158)
!158 = !{null, !159}
!159 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !154, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer)
!160 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !154, size: 64)
!161 = !DILocalVariable(name: "arg", arg: 1, scope: !151, file: !8, line: 94, type: !160)
!162 = !DILocation(line: 94, scope: !151)
!163 = distinct !DISubprogram(name: "U", linkageName: "?U@@YAXXZ", scope: !8, file: !8, line: 96, type: !135, isLocal: false, isDefinition: true, scopeLine: 96, flags: DIFlagPrototyped, isOptimized: false, unit: !2, retainedNodes: !4)
!164 = !DILocalVariable(name: "c", scope: !163, file: !8, line: 105, type: !165)
!165 = distinct !DICompositeType(tag: DW_TAG_union_type, name: "ComplexUnion", scope: !163, file: !8, line: 97, size: 32, flags: DIFlagTypePassByValue, elements: !166, identifier: ".?ATComplexUnion@?1??U@@YAXXZ@")
!166 = !{!167, !170, !171}
!167 = distinct !DICompositeType(tag: DW_TAG_union_type, name: "NestedUnion", scope: !165, file: !8, line: 100, size: 32, flags: DIFlagTypePassByValue, elements: !168, identifier: ".?ATNestedUnion@ComplexUnion@?1??U@@YAXXZ@")
!168 = !{!169}
!169 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !167, file: !8, line: 100, baseType: !12, size: 32)
!170 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !165, file: !8, line: 102, baseType: !167, size: 32)
!171 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !165, file: !8, line: 103, baseType: !12, size: 32)
!172 = !DILocation(line: 105, scope: !163)
!173 = !DILocation(line: 106, scope: !163)
|
{
"language": "Assembly"
}
|
; RUN: opt < %s -partial-inliner -skip-partial-inlining-cost-analysis -S | FileCheck %s
; RUN: opt < %s -passes=partial-inliner -skip-partial-inlining-cost-analysis -S | FileCheck %s
%"class.base" = type { %"struct.base"* }
%"struct.base" = type opaque
@g = external local_unnamed_addr global i32, align 4
define i32 @callee_unknown_use2(i32 %arg) local_unnamed_addr #0 {
; CHECK-LABEL:define{{.*}}@callee_unknown_use2.{{[0-9]}}
; CHECK-NOT: alloca
; CHECK: call void @llvm.lifetime
bb:
%tmp = alloca i32, align 4
%tmp1 = bitcast i32* %tmp to i8*
%tmp2 = load i32, i32* @g, align 4, !tbaa !2
%tmp3 = add nsw i32 %tmp2, 1
%tmp4 = icmp slt i32 %arg, 0
br i1 %tmp4, label %bb6, label %bb5
bb5: ; preds = %bb
call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp1) #2
store i32 %tmp3, i32* %tmp, align 4, !tbaa !2
store i32 %tmp3, i32* @g, align 4, !tbaa !2
call void @bar(i32* nonnull %tmp) #2
call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp1) #2
br label %bb6
bb6: ; preds = %bb5, %bb
%tmp7 = phi i32 [ 1, %bb5 ], [ 0, %bb ]
%tmp10 = bitcast i8* %tmp1 to i32*
ret i32 %tmp7
}
; Function Attrs: argmemonly nounwind
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
declare void @bar(i32*) local_unnamed_addr #2
declare void @bar2(i32*, i32*) local_unnamed_addr #1
; Function Attrs: argmemonly nounwind
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
; Function Attrs: nounwind uwtable
define i32 @caller(i32 %arg) local_unnamed_addr #0 {
bb:
%tmp = tail call i32 @callee_unknown_use2(i32 %arg)
ret i32 %tmp
}
attributes #0 = { nounwind uwtable}
attributes #1 = { argmemonly nounwind }
attributes #2 = { nounwind }
!llvm.module.flags = !{!0}
!llvm.ident = !{!1}
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{!"clang version 5.0.0 (trunk 303574)"}
!2 = !{!3, !3, i64 0}
!3 = !{!"int", !4, i64 0}
!4 = !{!"omnipotent char", !5, i64 0}
!5 = !{!"Simple C/C++ TBAA"}
|
{
"language": "Assembly"
}
|
// Copyright 2016 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build s390x
// +build linux
// +build !gccgo
#include "textflag.h"
//
// System calls for s390x, Linux
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
BR syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
BR syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
BL runtime·entersyscall(SB)
MOVD a1+8(FP), R2
MOVD a2+16(FP), R3
MOVD a3+24(FP), R4
MOVD $0, R5
MOVD $0, R6
MOVD $0, R7
MOVD trap+0(FP), R1 // syscall entry
SYSCALL
MOVD R2, r1+32(FP)
MOVD R3, r2+40(FP)
BL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
BR syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
BR syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOVD a1+8(FP), R2
MOVD a2+16(FP), R3
MOVD a3+24(FP), R4
MOVD $0, R5
MOVD $0, R6
MOVD $0, R7
MOVD trap+0(FP), R1 // syscall entry
SYSCALL
MOVD R2, r1+32(FP)
MOVD R3, r2+40(FP)
RET
|
{
"language": "Assembly"
}
|
// Check that two distinct CHECK lines won't match the same string
// RUN: not FileCheck -input-file %s %s
; CHECK: {{a[0-9]b}}
; CHECK: {{a[0-9]b}}
a2b
|
{
"language": "Assembly"
}
|
/*********************************************************************/
/* */
/* Optimized BLAS libraries */
/* By Kazushige Goto <kgoto@tacc.utexas.edu> */
/* */
/* Copyright (c) The University of Texas, 2009. All rights reserved. */
/* UNIVERSITY EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES CONCERNING */
/* THIS SOFTWARE AND DOCUMENTATION, INCLUDING ANY WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, */
/* NON-INFRINGEMENT AND WARRANTIES OF PERFORMANCE, AND ANY WARRANTY */
/* THAT MIGHT OTHERWISE ARISE FROM COURSE OF DEALING OR USAGE OF */
/* TRADE. NO WARRANTY IS EITHER EXPRESS OR IMPLIED WITH RESPECT TO */
/* THE USE OF THE SOFTWARE OR DOCUMENTATION. */
/* Under no circumstances shall University be liable for incidental, */
/* special, indirect, direct or consequential damages or loss of */
/* profits, interruption of business, or related expenses which may */
/* arise from use of Software or Documentation, including but not */
/* limited to those resulting from defects in Software and/or */
/* Documentation, or loss or inaccuracy of data of any kind. */
/*********************************************************************/
#define ASSEMBLER
#include "common.h"
#define N r3
#define XX r4
#define PREA r5
#ifdef linux
#ifndef __64BIT__
#define X r6
#define INCX r7
#else
#define X r7
#define INCX r8
#endif
#endif
#if defined(_AIX) || defined(__APPLE__)
#if !defined(__64BIT__) && defined(DOUBLE)
#define X r8
#define INCX r9
#else
#define X r7
#define INCX r8
#endif
#endif
#define FZERO f0
#define ALPHA f1
PROLOGUE
PROFCODE
addi SP, SP, -8
li r0, 0
stw r0, 0(SP)
lfs FZERO, 0(SP)
addi SP, SP, 8
slwi INCX, INCX, BASE_SHIFT
li PREA, L1_PREFETCHSIZE
cmpwi cr0, N, 0
blelr- cr0
fcmpu cr0, FZERO, ALPHA
bne- cr0, LL(A1I1)
cmpwi cr0, INCX, SIZE
bne- cr0, LL(A0IN)
srawi. r0, N, 4
mtspr CTR, r0
beq- cr0, LL(A0I1_Remain)
.align 4
LL(A0I1_kernel):
STFD FZERO, 0 * SIZE(X)
STFD FZERO, 1 * SIZE(X)
STFD FZERO, 2 * SIZE(X)
STFD FZERO, 3 * SIZE(X)
STFD FZERO, 4 * SIZE(X)
STFD FZERO, 5 * SIZE(X)
STFD FZERO, 6 * SIZE(X)
STFD FZERO, 7 * SIZE(X)
STFD FZERO, 8 * SIZE(X)
STFD FZERO, 9 * SIZE(X)
STFD FZERO, 10 * SIZE(X)
STFD FZERO, 11 * SIZE(X)
STFD FZERO, 12 * SIZE(X)
STFD FZERO, 13 * SIZE(X)
STFD FZERO, 14 * SIZE(X)
STFD FZERO, 15 * SIZE(X)
addi X, X, 16 * SIZE
bdnz LL(A0I1_kernel)
.align 4
LL(A0I1_Remain):
andi. r0, N, 15
mtspr CTR, r0
beqlr+
.align 4
LL(A0I1_RemainKernel):
STFD FZERO, 0 * SIZE(X)
addi X, X, 1 * SIZE
bdnz LL(A0I1_RemainKernel)
blr
.align 4
LL(A0IN):
srawi. r0, N, 3
mtspr CTR, r0
beq- LL(A0IN_Remain)
.align 4
LL(A0IN_Kernel):
dcbtst X, PREA
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
bdnz LL(A0IN_Kernel)
.align 4
LL(A0IN_Remain):
andi. r0, N, 7
mtspr CTR, r0
beqlr+
.align 4
LL(A0IN_RemainKernel):
STFD FZERO, 0 * SIZE(X)
add X, X, INCX
bdnz LL(A0IN_RemainKernel)
blr
.align 4
LL(A1I1):
cmpwi cr0, INCX, SIZE
bne- LL(A1IN)
mr XX, X
srawi. r0, N, 4
mtspr CTR, r0
beq+ LL(A1I1_Remain)
LFD f2, 0 * SIZE(X)
LFD f3, 1 * SIZE(X)
LFD f4, 2 * SIZE(X)
LFD f5, 3 * SIZE(X)
LFD f6, 4 * SIZE(X)
LFD f7, 5 * SIZE(X)
LFD f8, 6 * SIZE(X)
LFD f9, 7 * SIZE(X)
bdz LL(13)
.align 4
LL(A1I1_kernel):
FMUL f10, ALPHA, f2
FMUL f11, ALPHA, f3
FMUL f12, ALPHA, f4
FMUL f13, ALPHA, f5
LFD f2, 8 * SIZE(X)
LFD f3, 9 * SIZE(X)
LFD f4, 10 * SIZE(X)
LFD f5, 11 * SIZE(X)
STFD f10, 0 * SIZE(X)
STFD f11, 1 * SIZE(X)
STFD f12, 2 * SIZE(X)
STFD f13, 3 * SIZE(X)
FMUL f10, ALPHA, f6
FMUL f11, ALPHA, f7
FMUL f12, ALPHA, f8
FMUL f13, ALPHA, f9
LFD f6, 12 * SIZE(X)
LFD f7, 13 * SIZE(X)
LFD f8, 14 * SIZE(X)
LFD f9, 15 * SIZE(X)
STFD f10, 4 * SIZE(X)
STFD f11, 5 * SIZE(X)
STFD f12, 6 * SIZE(X)
STFD f13, 7 * SIZE(X)
FMUL f10, ALPHA, f2
FMUL f11, ALPHA, f3
FMUL f12, ALPHA, f4
FMUL f13, ALPHA, f5
LFD f2, 16 * SIZE(X)
LFD f3, 17 * SIZE(X)
LFD f4, 18 * SIZE(X)
LFD f5, 19 * SIZE(X)
STFD f10, 8 * SIZE(X)
STFD f11, 9 * SIZE(X)
STFD f12, 10 * SIZE(X)
STFD f13, 11 * SIZE(X)
FMUL f10, ALPHA, f6
FMUL f11, ALPHA, f7
FMUL f12, ALPHA, f8
FMUL f13, ALPHA, f9
LFD f6, 20 * SIZE(X)
LFD f7, 21 * SIZE(X)
LFD f8, 22 * SIZE(X)
LFD f9, 23 * SIZE(X)
STFD f10, 12 * SIZE(X)
STFD f11, 13 * SIZE(X)
STFD f12, 14 * SIZE(X)
STFD f13, 15 * SIZE(X)
addi X, X, 16 * SIZE
dcbtst X, PREA
bdnz LL(A1I1_kernel)
.align 4
LL(13):
FMUL f10, ALPHA, f2
FMUL f11, ALPHA, f3
FMUL f12, ALPHA, f4
FMUL f13, ALPHA, f5
LFD f2, 8 * SIZE(X)
LFD f3, 9 * SIZE(X)
LFD f4, 10 * SIZE(X)
LFD f5, 11 * SIZE(X)
STFD f10, 0 * SIZE(X)
STFD f11, 1 * SIZE(X)
STFD f12, 2 * SIZE(X)
STFD f13, 3 * SIZE(X)
FMUL f10, ALPHA, f6
FMUL f11, ALPHA, f7
FMUL f12, ALPHA, f8
FMUL f13, ALPHA, f9
LFD f6, 12 * SIZE(X)
LFD f7, 13 * SIZE(X)
LFD f8, 14 * SIZE(X)
LFD f9, 15 * SIZE(X)
STFD f10, 4 * SIZE(X)
STFD f11, 5 * SIZE(X)
STFD f12, 6 * SIZE(X)
STFD f13, 7 * SIZE(X)
FMUL f10, ALPHA, f2
FMUL f11, ALPHA, f3
FMUL f12, ALPHA, f4
FMUL f13, ALPHA, f5
STFD f10, 8 * SIZE(X)
STFD f11, 9 * SIZE(X)
STFD f12, 10 * SIZE(X)
STFD f13, 11 * SIZE(X)
FMUL f10, ALPHA, f6
FMUL f11, ALPHA, f7
FMUL f12, ALPHA, f8
FMUL f13, ALPHA, f9
STFD f10, 12 * SIZE(X)
STFD f11, 13 * SIZE(X)
STFD f12, 14 * SIZE(X)
STFD f13, 15 * SIZE(X)
addi X, X, 16 * SIZE
.align 4
LL(A1I1_Remain):
andi. r0, N, 15
mtspr CTR, r0
beqlr+
.align 4
LL(A1I1_RemainKernel):
LFD f2, 0 * SIZE(X)
FMUL f2, ALPHA, f2
STFD f2, 0 * SIZE(X)
addi X, X, 1 * SIZE
bdnz LL(A1I1_RemainKernel)
blr
.align 4
LL(A1IN):
mr XX, X
srawi. r0, N, 3
mtspr CTR, r0
beq- LL(A1IN_Remain)
.align 4
LL(A1IN_Kernel):
LFD f2, 0 * SIZE(XX)
add XX, XX, INCX
LFD f3, 0 * SIZE(XX)
add XX, XX, INCX
LFD f4, 0 * SIZE(XX)
add XX, XX, INCX
LFD f5, 0 * SIZE(XX)
add XX, XX, INCX
FMUL f2, ALPHA, f2
FMUL f3, ALPHA, f3
FMUL f4, ALPHA, f4
FMUL f5, ALPHA, f5
LFD f6, 0 * SIZE(XX)
add XX, XX, INCX
LFD f7, 0 * SIZE(XX)
add XX, XX, INCX
LFD f8, 0 * SIZE(XX)
add XX, XX, INCX
LFD f9, 0 * SIZE(XX)
add XX, XX, INCX
FMUL f6, ALPHA, f6
FMUL f7, ALPHA, f7
FMUL f8, ALPHA, f8
FMUL f9, ALPHA, f9
STFD f2, 0 * SIZE(X)
add X, X, INCX
STFD f3, 0 * SIZE(X)
add X, X, INCX
STFD f4, 0 * SIZE(X)
add X, X, INCX
STFD f5, 0 * SIZE(X)
add X, X, INCX
STFD f6, 0 * SIZE(X)
add X, X, INCX
STFD f7, 0 * SIZE(X)
add X, X, INCX
STFD f8, 0 * SIZE(X)
add X, X, INCX
STFD f9, 0 * SIZE(X)
add X, X, INCX
bdnz LL(A1IN_Kernel)
.align 4
LL(A1IN_Remain):
andi. r0, N, 7
mtspr CTR, r0
beqlr+
.align 4
LL(A1IN_RemainKernel):
LFD f2, 0 * SIZE(XX)
add XX, XX, INCX
FMUL f2, ALPHA, f2
STFD f2, 0 * SIZE(X)
add X, X, INCX
bdnz LL(A1IN_RemainKernel)
blr
EPILOGUE
|
{
"language": "Assembly"
}
|
// Purpose:
// Check that parsing bad commands gives a useful error.
// - Unbalanced parenthesis
// Check directives are in check.txt to prevent dexter reading any embedded
// commands.
//
// Note: Despite using 'lldb' as the debugger, lldb is not actually required
// as the test should finish before lldb would be invoked.
//
// RUN: not %dexter_base test --builder 'clang' --debugger 'lldb' \
// RUN: --cflags "-O0 -g" -v -- %s \
// RUN: | FileCheck %s --match-full-lines --strict-whitespace
//
// CHECK:parser error:{{.*}}err_paren.cpp(22): Unbalanced parenthesis starting here
// CHECK:// {{Dex}}ExpectWatchValue(
// CHECK: ^
int main(){
return 0;
}
// DexExpectWatchValue(
|
{
"language": "Assembly"
}
|
#include "../sysfs.h"
/* Gyroscope types of attribute */
#define IIO_DEV_ATTR_GYRO_OFFSET(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_offset, _mode, _show, _store, _addr)
#define IIO_DEV_ATTR_GYRO_X_OFFSET(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_x_offset, _mode, _show, _store, _addr)
#define IIO_DEV_ATTR_GYRO_Y_OFFSET(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_y_offset, _mode, _show, _store, _addr)
#define IIO_DEV_ATTR_GYRO_Z_OFFSET(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_z_offset, _mode, _show, _store, _addr)
#define IIO_DEV_ATTR_GYRO_X_GAIN(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_x_gain, _mode, _show, _store, _addr)
#define IIO_DEV_ATTR_GYRO_Y_GAIN(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_y_gain, _mode, _show, _store, _addr)
#define IIO_DEV_ATTR_GYRO_Z_GAIN(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_z_gain, _mode, _show, _store, _addr)
#define IIO_DEV_ATTR_GYRO_SCALE(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_scale, S_IRUGO, _show, _store, _addr)
#define IIO_DEV_ATTR_GYRO(_show, _addr) \
IIO_DEVICE_ATTR(gyro_raw, S_IRUGO, _show, NULL, _addr)
#define IIO_DEV_ATTR_GYRO_X(_show, _addr) \
IIO_DEVICE_ATTR(gyro_x_raw, S_IRUGO, _show, NULL, _addr)
#define IIO_DEV_ATTR_GYRO_Y(_show, _addr) \
IIO_DEVICE_ATTR(gyro_y_raw, S_IRUGO, _show, NULL, _addr)
#define IIO_DEV_ATTR_GYRO_Z(_show, _addr) \
IIO_DEVICE_ATTR(gyro_z_raw, S_IRUGO, _show, NULL, _addr)
#define IIO_DEV_ATTR_ANGL(_show, _addr) \
IIO_DEVICE_ATTR(angl_raw, S_IRUGO, _show, NULL, _addr)
|
{
"language": "Assembly"
}
|
;===============================================================================
; Copyright 2014-2019 Intel Corporation
; All Rights Reserved.
;
; If this software was obtained under the Intel Simplified Software License,
; the following terms apply:
;
; The source code, information and material ("Material") contained herein is
; owned by Intel Corporation or its suppliers or licensors, and title to such
; Material remains with Intel Corporation or its suppliers or licensors. The
; Material contains proprietary information of Intel or its suppliers and
; licensors. The Material is protected by worldwide copyright laws and treaty
; provisions. No part of the Material may be used, copied, reproduced,
; modified, published, uploaded, posted, transmitted, distributed or disclosed
; in any way without Intel's prior express written permission. No license under
; any patent, copyright or other intellectual property rights in the Material
; is granted to or conferred upon you, either expressly, by implication,
; inducement, estoppel or otherwise. Any license under such intellectual
; property rights must be express and approved by Intel in writing.
;
; Unless otherwise agreed by Intel in writing, you may not remove or alter this
; notice or any other notice embedded in Materials by Intel or Intel's
; suppliers or licensors in any way.
;
;
; If this software was obtained under the Apache License, Version 2.0 (the
; "License"), the following terms apply:
;
; You may not use this file except in compliance with the License. You may
; obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
;
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;
; See the License for the specific language governing permissions and
; limitations under the License.
;===============================================================================
;
;
; Purpose: Cryptography Primitive.
; Message block processing according to SHA512
;
; Content:
; UpdateSHA512
;
;
SECTION .text
%define IPP_ALIGN_FACTOR 32
%macro LD_ADDR 2
lea %1, %2
%endmacro
;;
;; ENDIANNESS
;;
%macro ENDIANNESS 2
vpshufb %1, %1, %2
%endmacro
;;
;; Rotate Right
;;
%macro PRORQ 3
vpsllq %3, %1, (64-%2)
vpsrlq %1, %1, %2
vpor %1, %1,%3
%endmacro
;;
;; Init and Update W:
;;
;; j = 0-15
;; W[j] = ENDIANNESS(src)
;;
;; j = 16-79
;; W[j] = SIGMA1(W[j- 2]) + W[j- 7]
;; +SIGMA0(W[j-15]) + W[j-16]
;;
;; SIGMA0(x) = ROR64(x,1) ^ROR64(x,8) ^LSR64(x,7)
;; SIGMA1(x) = ROR64(x,19)^ROR64(x,61)^LSR64(x,6)
;;
%macro SIGMA0 4
vpsrlq %1, %2, 7
vmovdqa %3, %2
PRORQ %2, 1, %4
vpxor %1, %1, %2
PRORQ %3,8, %4
vpxor %1, %1, %3
%endmacro
%macro SIGMA1 4
vpsrlq %1, %2, 6
vmovdqa %3, %2
PRORQ %2, 19, %4
vpxor %1, %1, %2
PRORQ %3,61, %4
vpxor %1, %1, %3
%endmacro
;;
;; SHA512 step
;;
;; Ipp64u T1 = H + SUM1(E) + CHJ(E,F,G) + K_SHA512[t] + W[t];
;; Ipp64u T2 = SUM0(A) + MAJ(A,B,C);
;; D+= T1;
;; H = T1 + T2;
;;
;; where
;; SUM1(x) = ROR64(x,14) ^ ROR64(x,18) ^ ROR64(x,41)
;; SUM0(x) = ROR64(x,28) ^ ROR64(x,34) ^ ROR64(x,39)
;;
;; CHJ(x,y,z) = (x & y) ^ (~x & z) => x&(y^z) ^z
;; MAJ(x,y,z) = (x & y) ^ (x & z) ^ (y & z) = (x&y)^((x^y)&z)
;;
;; Input:
;; A,B,C,D,E,F,G,H - 8 digest's values
;; pW - pointer to the W array
;; pK512 - pointer to the constants
;; pBuffer - temporary buffer
;; Output:
;; A,B,C,D*,E,F,G,H* - 8 digest's values (D and H updated)
;; pW - pointer to the W array
;; pK512 - pointer to the constants
;; pBuffer - temporary buffer (changed)
;;
%macro CHJ 5
vpxor %1, %3,%4 ; R=(f^g)
vpand %1, %1,%2 ; R=e & (f^g)
vpxor %1, %1,%4 ; R=e & (f^g) ^g
%endmacro
%macro MAJ 5
vpxor %5, %2,%3 ; T=a^b
vpand %1, %2,%3 ; R=a&b
vpand %5, %5,%4 ; T=(a^b)&c
vpxor %1, %1,%5 ; R=(a&b)^((a^b)&c)
%endmacro
%macro SUM0 3
vmovdqa %1,%2
PRORQ %1,28,%3 ; R=ROR(X,28)
PRORQ %2,34,%3 ; X=ROR(X,34)
vpxor %1, %1,%2
PRORQ %2,(39-34),%3 ; X=ROR(x,39)
vpxor %1, %1,%2
%endmacro
%macro SUM1 3
vmovdqa %1,%2
PRORQ %1,14,%3 ; R=ROR(X,14)
PRORQ %2,18,%3 ; X=ROR(X,18)
vpxor %1, %1,%2
PRORQ %2,(41-18),%3 ; X=ROR(x,41)
vpxor %1, %1,%2
%endmacro
%macro SHA512_STEP 11
vmovdqa oword [%11+0*oSize],%5 ; save E
vmovdqa oword [%11+1*oSize],%1 ; save A
vmovdqa oword [%11+2*oSize],%4 ; save D
vmovdqa oword [%11+3*oSize],%8 ; save H
CHJ %4,%5,%6,%7, %8 ; t1 = h+CHJ(e,f,g)+pW[]+pK512[]
vmovq %8, qword [%9]
vpaddq %4, %4,%8 ; +[pW]
vmovq %8, qword [%10]
vpaddq %4, %4,%8 ; +[pK512]
vpaddq %4, %4,oword [%11+3*oSize]
vmovdqa oword [%11+3*oSize],%4 ; save t1
MAJ %8,%1,%2,%3, %4 ; t2 = MAJ(a,b,c)
vmovdqa oword [%11+4*oSize],%8 ; save t2
SUM1 %4,%5,%8 ; D = SUM1(e)
vpaddq %4, %4,oword [%11+3*oSize]; t1 = h+CHJ(e,f,g)+pW[]+pK512[] + SUM1(e)
SUM0 %8,%1,%5 ; H = SUM0(a)
vpaddq %8, %8,oword [%11+4*oSize]; t2 = MAJ(a,b,c)+SUM0(a)
vpaddq %8, %8,%4 ; h = t1+t2
vpaddq %4, %4,oword [%11+2*oSize]; d+= t1
vmovdqa %5,oword [%11+0*oSize] ; restore E
vmovdqa %1,oword [%11+1*oSize] ; restore A
%endmacro
ALIGN IPP_ALIGN_FACTOR
SWP_BYTE:
pByteSwp DB 7,6,5,4,3,2,1,0, 15,14,13,12,11,10,9,8
;*******************************************************************************************
;* Purpose: Update internal digest according to message block
;*
;* void UpdateSHA512(DigestSHA512 digest, const Ipp64u* mblk, int mlen, const void* pParam)
;*
;*******************************************************************************************
;;
;; Lib = W7, V8, P8
;;
;; Caller = ippsSHA512Update
;; Caller = ippsSHA512Final
;; Caller = ippsSHA512MessageDigest
;;
;; Caller = ippsSHA384Update
;; Caller = ippsSHA384Final
;; Caller = ippsSHA384MessageDigest
;;
;; Caller = ippsHMACSHA512Update
;; Caller = ippsHMACSHA512Final
;; Caller = ippsHMACSHA512MessageDigest
;;
;; Caller = ippsHMACSHA384Update
;; Caller = ippsHMACSHA384Final
;; Caller = ippsHMACSHA384MessageDigest
;;
;; ALIGN IPP_ALIGN_FACTOR
;; IPPASM UpdateSHA512 PROC NEAR C PUBLIC \
;; USES esi edi,\
;; digest: PTR QWORD,\ ; digest address
;; mblk: PTR BYTE,\ ; buffer address
;; mlen: DWORD,\ ; buffer length
;; pSHA512: PTR QWORD ; address of SHA constants
global ASM_PFX(UpdateSHA512G9)
ASM_PFX(UpdateSHA512G9):
%define oSize 16
%define qSize 8
%define digest [ebp+0x08]
%define mblk [ebp+0x0C]
%define mlen [ebp+0x10]
%define pSHA512 [ebp+0x14]
%define MBS_SHA512 128 ; SHA512 block data size
%define sSize 5 ; size of save area (oword)
%define dSize 8 ; size of digest (oword)
%define wSize 80 ; W values queue (qword)
%define stackSize sSize*oSize+dSize*oSize+wSize*qSize
%define sOffset 0 ; save area
%define dOffset sOffset+sSize*oSize ; digest offset
%define wOffset dOffset+dSize*oSize ; W values offset
%define acualOffset wOffset+wSize*qSize ; actual stack size offset
; Save
push ebp
mov ebp,esp
push ebx
push esi
push edi
; Start
mov edi,digest ; digest address
mov esi,mblk ; source data address
mov eax,mlen ; source data length
mov edx, pSHA512 ; table constant address
sub esp,stackSize ; allocate local buffer (probably unaligned)
mov ecx,esp
and esp,-16 ; 16-byte aligned stack
sub ecx,esp
add ecx,stackSize ; acual stack size (bytes)
mov [esp+acualOffset],ecx
vmovq xmm0,qword [edi+qSize*0] ; A = digest[0]
vmovq xmm1,qword [edi+qSize*1] ; B = digest[1]
vmovq xmm2,qword [edi+qSize*2] ; C = digest[2]
vmovq xmm3,qword [edi+qSize*3] ; D = digest[3]
vmovq xmm4,qword [edi+qSize*4] ; E = digest[4]
vmovq xmm5,qword [edi+qSize*5] ; F = digest[5]
vmovq xmm6,qword [edi+qSize*6] ; G = digest[6]
vmovq xmm7,qword [edi+qSize*7] ; H = digest[7]
vmovdqa oword [esp+dOffset+oSize*0], xmm0
vmovdqa oword [esp+dOffset+oSize*1], xmm1
vmovdqa oword [esp+dOffset+oSize*2], xmm2
vmovdqa oword [esp+dOffset+oSize*3], xmm3
vmovdqa oword [esp+dOffset+oSize*4], xmm4
vmovdqa oword [esp+dOffset+oSize*5], xmm5
vmovdqa oword [esp+dOffset+oSize*6], xmm6
vmovdqa oword [esp+dOffset+oSize*7], xmm7
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; process next data block
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
sha512_block_loop:
;;
;; initialize the first 16 qwords in the array W (remember about endian)
;;
;vmovdqa xmm1, oword pByteSwp ; load shuffle mask
LD_ADDR ecx, [pByteSwp]
movdqa xmm1, oword [ecx+(pByteSwp-SWP_BYTE)]
mov ecx,0
ALIGN IPP_ALIGN_FACTOR
loop1:
vmovdqu xmm0, oword [esi+ecx*qSize] ; swap input
ENDIANNESS xmm0, xmm1
vmovdqa oword [esp+wOffset+ecx*qSize],xmm0
add ecx,oSize/qSize
cmp ecx,16
jl loop1
;;
;; initialize another 80-16 qwords in the array W
;;
ALIGN IPP_ALIGN_FACTOR
loop2:
vmovdqa xmm1,oword [esp+ecx*qSize+wOffset- 2*qSize] ; xmm1 = W[j-2]
SIGMA1 xmm0,xmm1,xmm2,xmm3
vmovdqu xmm5,oword [esp+ecx*qSize+wOffset-15*qSize] ; xmm5 = W[j-15]
SIGMA0 xmm4,xmm5,xmm6,xmm3
vmovdqu xmm7,oword [esp+ecx*qSize+wOffset- 7*qSize] ; W[j-7]
vpaddq xmm0, xmm0,xmm4
vpaddq xmm7, xmm7,oword [esp+ecx*qSize+wOffset-16*qSize] ; W[j-16]
vpaddq xmm0, xmm0,xmm7
vmovdqa oword [esp+ecx*qSize+wOffset],xmm0
add ecx,oSize/qSize
cmp ecx,80
jl loop2
;;
;; init A,B,C,D,E,F,G,H by the internal digest
;;
vmovdqa xmm0,oword [esp+dOffset+oSize*0] ; A = digest[0]
vmovdqa xmm1,oword [esp+dOffset+oSize*1] ; B = digest[1]
vmovdqa xmm2,oword [esp+dOffset+oSize*2] ; C = digest[2]
vmovdqa xmm3,oword [esp+dOffset+oSize*3] ; D = digest[3]
vmovdqa xmm4,oword [esp+dOffset+oSize*4] ; E = digest[4]
vmovdqa xmm5,oword [esp+dOffset+oSize*5] ; F = digest[5]
vmovdqa xmm6,oword [esp+dOffset+oSize*6] ; G = digest[6]
vmovdqa xmm7,oword [esp+dOffset+oSize*7] ; H = digest[7]
;;
;; perform 0-79 steps
;;
xor ecx,ecx
ALIGN IPP_ALIGN_FACTOR
loop3:
;; A, B, C, D, E, F, G, H W[], K[], buffer
;; --------------------------------------------------------------------------------------------------------------------------------------
SHA512_STEP xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7, esp+ecx*qSize+wOffset+qSize*0, edx+ecx*qSize+qSize*0, esp
SHA512_STEP xmm7,xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6, esp+ecx*qSize+wOffset+qSize*1, edx+ecx*qSize+qSize*1, esp
SHA512_STEP xmm6,xmm7,xmm0,xmm1,xmm2,xmm3,xmm4,xmm5, esp+ecx*qSize+wOffset+qSize*2, edx+ecx*qSize+qSize*2, esp
SHA512_STEP xmm5,xmm6,xmm7,xmm0,xmm1,xmm2,xmm3,xmm4, esp+ecx*qSize+wOffset+qSize*3, edx+ecx*qSize+qSize*3, esp
SHA512_STEP xmm4,xmm5,xmm6,xmm7,xmm0,xmm1,xmm2,xmm3, esp+ecx*qSize+wOffset+qSize*4, edx+ecx*qSize+qSize*4, esp
SHA512_STEP xmm3,xmm4,xmm5,xmm6,xmm7,xmm0,xmm1,xmm2, esp+ecx*qSize+wOffset+qSize*5, edx+ecx*qSize+qSize*5, esp
SHA512_STEP xmm2,xmm3,xmm4,xmm5,xmm6,xmm7,xmm0,xmm1, esp+ecx*qSize+wOffset+qSize*6, edx+ecx*qSize+qSize*6, esp
SHA512_STEP xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7,xmm0, esp+ecx*qSize+wOffset+qSize*7, edx+ecx*qSize+qSize*7, esp
add ecx,8
cmp ecx,80
jl loop3
;;
;; update digest
;;
vpaddq xmm0, xmm0,oword [esp+dOffset+oSize*0] ; A += digest[0]
vpaddq xmm1, xmm1,oword [esp+dOffset+oSize*1] ; B += digest[1]
vpaddq xmm2, xmm2,oword [esp+dOffset+oSize*2] ; C += digest[2]
vpaddq xmm3, xmm3,oword [esp+dOffset+oSize*3] ; D += digest[3]
vpaddq xmm4, xmm4,oword [esp+dOffset+oSize*4] ; E += digest[4]
vpaddq xmm5, xmm5,oword [esp+dOffset+oSize*5] ; F += digest[5]
vpaddq xmm6, xmm6,oword [esp+dOffset+oSize*6] ; G += digest[6]
vpaddq xmm7, xmm7,oword [esp+dOffset+oSize*7] ; H += digest[7]
vmovdqa oword [esp+dOffset+oSize*0],xmm0 ; digest[0] = A
vmovdqa oword [esp+dOffset+oSize*1],xmm1 ; digest[1] = B
vmovdqa oword [esp+dOffset+oSize*2],xmm2 ; digest[2] = C
vmovdqa oword [esp+dOffset+oSize*3],xmm3 ; digest[3] = D
vmovdqa oword [esp+dOffset+oSize*4],xmm4 ; digest[4] = E
vmovdqa oword [esp+dOffset+oSize*5],xmm5 ; digest[5] = F
vmovdqa oword [esp+dOffset+oSize*6],xmm6 ; digest[6] = G
vmovdqa oword [esp+dOffset+oSize*7],xmm7 ; digest[7] = H
add esi, MBS_SHA512
sub eax, MBS_SHA512
jg sha512_block_loop
vmovq qword [edi+qSize*0], xmm0 ; A = digest[0]
vmovq qword [edi+qSize*1], xmm1 ; B = digest[1]
vmovq qword [edi+qSize*2], xmm2 ; C = digest[2]
vmovq qword [edi+qSize*3], xmm3 ; D = digest[3]
vmovq qword [edi+qSize*4], xmm4 ; E = digest[4]
vmovq qword [edi+qSize*5], xmm5 ; F = digest[5]
vmovq qword [edi+qSize*6], xmm6 ; G = digest[6]
vmovq qword [edi+qSize*7], xmm7 ; H = digest[7]
add esp,[esp+acualOffset]
; Restore
pop edi
pop esi
pop ebx
pop ebp
ret
|
{
"language": "Assembly"
}
|
; RUN: llvm-as < %s | llvm-bcanalyzer -dump | FileCheck %s
!named = !{!0}
; CHECK: <METADATA_BLOCK
; CHECK-NEXT: <STRINGS
; CHECK-SAME: /> num-strings = 3 {
; CHECK-NEXT: 'a'
; CHECK-NEXT: 'b'
; CHECK-NEXT: 'c'
; CHECK-NEXT: }
!0 = !{!"a", !"b", !"c"}
|
{
"language": "Assembly"
}
|
# RUN: llvm-nm -g %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
# RUN: llvm-nm -g -g %p/Inputs/hello.obj.macho-x86_64 | FileCheck %s
# CHECK-NOT: EH_frame0
# CHECK: _main
|
{
"language": "Assembly"
}
|
// RUN: c-index-test -test-inclusion-stack-source %s 2>&1 | FileCheck %s
#include "include_test.h"
// CHECK: cindex-test-inclusions.c
// CHECK: included by:
// CHECK: include_test.h
// CHECK: included by:
// CHECK: cindex-test-inclusions.c:3:10
// CHECK: include_test_2.h
// CHECK: included by:
// CHECK: include_test.h:1:10
// CHECK: cindex-test-inclusions.c:3:10
|
{
"language": "Assembly"
}
|
.PAG 'TAPE WRITE'
; CASSETTE INFO - FSBLK IS BLOCK COUNTER FOR RECORD
; FSBLK = 2 -FIRST HEADER
; = 1 -FIRST DATA
; = 0 -SECOND DATA
;
; WRITE - TOGGLE WRITE BIT ACCORDING TO LSB IN OCHAR
;
WRITE LDA OCHAR ;SHIFT BIT TO WRITE INTO CARRY
LSR A
LDA #96 ;...C CLR WRITE SHORT
BCC WRT1
WRTW LDA #176 ;...C SET WRITE LONG
WRT1 LDX #0 ;SET AND STORE TIME
WRTX STA D1T2L
STX D1T2H
LDA D1ICR ;CLEAR IRQ
LDA #$19 ;ENABLE TIMER (ONE-SHOT)
STA D1CRB
LDA R6510 ;TOGGLE WRITE BIT
EOR #$08
STA R6510
AND #$08 ;LEAVE ONLY WRITE BIT
RTS
;
WRTL3 SEC ;FLAG PRP FOR END OF BLOCK
ROR PRP
BMI WRT3 ; JMP
;
; WRTN - CALLED AT THE END OF EACH BYTE
; TO WRITE A LONG RER REZ
; HHHHHHLLLLLLHHHLLL...
;
WRTN LDA RER ;CHECK FOR ONE LONG
BNE WRTN1
LDA #16 ;WRITE A LONG BIT
LDX #1
JSR WRTX
BNE WRT3
INC RER
LDA PRP ;IF END OF BLOCK(BIT SET BY WRTL3)...
BPL WRT3 ;...NO END CONTINUE
JMP WRNC ;...END ...FINISH OFF
;
WRTN1 LDA REZ ;CHECK FOR A ONE BIT
BNE WRTN2
JSR WRTW
BNE WRT3
INC REZ
BNE WRT3
;
WRTN2 JSR WRITE
BNE WRT3 ;ON BIT LOW EXIT
LDA FIRT ;CHECK FOR FIRST OF DIPOLE
EOR #1
STA FIRT
BEQ WRT2 ;DIPOLE DONE
LDA OCHAR ;FLIPS BIT FOR COMPLEMENTARY RIGHT
EOR #1
STA OCHAR
AND #1 ;TOGGLE PARITY
EOR PRTY
STA PRTY
WRT3 JMP PREND ;RESTORE REGS AND RTI EXIT
;
WRT2 LSR OCHAR ;MOVE TO NEXT BIT
DEC PCNTR ;DEC COUNTER FOR # OF BITS
LDA PCNTR ;CHECK FOR 8 BITS SENT...
BEQ WRT4 ;...IF YES MOVE IN PARITY
BPL WRT3 ;...ELSE SEND REST
;
WRTS JSR NEWCH ;CLEAN UP COUNTERS
CLI ;ALLOW FOR INTERRUPTS TO NEST
LDA CNTDN ;ARE WE WRITING HEADER COUNTERS?...
BEQ WRT6 ;...NO
; WRITE HEADER COUNTERS (9876543210 TO HELP WITH READ)
LDX #0 ;CLEAR BCC
STX DATA
WRTS1 DEC CNTDN
LDX FSBLK ;CHECK FOR FIRST BLOCK HEADER
CPX #2
BNE WRT61 ;...NO
ORA #$80 ;...YES MARK FIRST BLOCK HEADER
WRT61 STA OCHAR ;WRITE CHARACTERS IN HEADER
BNE WRT3
;
WRT6 JSR CMPSTE ;COMPARE START:END
BCC WRT7 ;NOT DONE
BNE WRTL3 ;GO MARK END
INC SAH
LDA DATA ;WRITE OUT BCC
STA OCHAR
BCS WRT3 ;JMP
;
WRT7 LDY #0 ;GET NEXT CHARACTER
LDA (SAL)Y
STA OCHAR ;STORE IN OUTPUT CHARACTER
EOR DATA ;UPDATE BCC
STA DATA
JSR INCSAL ;INCREMENT FETCH ADDRESS
BNE WRT3 ;BRANCH ALWAYS
;
WRT4 LDA PRTY ;MOVE PARITY INTO OCHAR...
EOR #1
STA OCHAR ;...TO BE WRITTEN AS NEXT BIT
WRTBK JMP PREND ;RESTORE REGS AND RTI EXIT
;
WRNC DEC FSBLK ;CHECK FOR END
BNE WREND ;...BLOCK ONLY
JSR TNOF ;...WRITE, SO TURN OFF MOTOR
WREND LDA #80 ;PUT 80 CASSETTE SYNCS AT END
STA SHCNL
LDX #8
SEI
JSR BSIV ;SET VECTOR TO WRITE ZEROS
BNE WRTBK ;JMP
;
WRTZ LDA #120 ;WRITE LEADING ZEROS FOR SYNC
JSR WRT1
BNE WRTBK
DEC SHCNL ;CHECK IF DONE WITH LOW SYNC...
BNE WRTBK ;...NO
JSR NEWCH ;...YES CLEAR UP COUNTERS
DEC SHCNH ;CHECK IF DONE WITH SYNC...
BPL WRTBK ;...NO
LDX #10 ;...YES SO SET VECTOR FOR DATA
JSR BSIV
CLI
INC SHCNH ;ZERO SHCNH
LDA FSBLK ;IF DONE THEN...
BEQ STKY ;...GOTO SYSTEM RESTORE
JSR RD300
LDX #9 ;SET UP FOR HEADER COUNT
STX CNTDN
STX PRP ;CLEAR ENDOF BLOCK FLAG
BNE WRTS ;JMP
;
TNIF PHP ;CLEAN UP INTERRUPTS AND RESTORE PIA'S
SEI
LDA VICREG+17 ;UNLOCK VIC
ORA #$10 ;ENABLE DISPLAY
STA VICREG+17
JSR TNOF ;TURN OFF MOTOR
LDA #$7F ;CLEAR INTERRUPTS
STA D1ICR
JSR IOKEYS ;RESTORE KEYBOARD IRQ FROM TIMMER1
LDA IRQTMP+1 ;RESTORE KEYBOARD INTERRUPT VECTOR
BEQ TNIQ ;NO IRQ (IRQ VECTOR CANNOT BE Z-PAGE)
STA CINV+1
LDA IRQTMP
STA CINV
TNIQ PLP
RTS
;
STKY JSR TNIF ;GO RESTORE SYSTEM INTERRUPTS
BEQ WRTBK ;CAME FOR CASSETTE IRQ SO RTI
;
; BSIV - SUBROUTINE TO CHANGE IRQ VECTORS
; ENTRYS - .X = 8 WRITE ZEROS TO TAPE
; .X = 10 WRITE DATA TO TAPE
; .X = 12 RESTORE TO KEYSCAN
; .X = 14 READ DATA FROM TAPE
;
BSIV LDA BSIT-8,X ;MOVE IRQ VECTORS, TABLE TO INDIRECT
STA CINV
LDA BSIT+1-8,X
STA CINV+1
RTS
;
TNOF LDA R6510 ;TURN OFF CASSETTE MOTOR
ORA #$20 ;
STA R6510
RTS
.SKI 3
;COMPARE START AND END LOAD/SAVE
;ADDRESSES. SUBROUTINE CALLED BY
;TAPE READ, SAVE, TAPE WRITE
;
CMPSTE SEC
LDA SAL
SBC EAL
LDA SAH
SBC EAH
RTS
.SKI 3
;INCREMENT ADDRESS POINTER SAL
;
INCSAL INC SAL
BNE INCR
INC SAH
INCR RTS
.END
; RSR 7/28/80 ADD COMMENTS
; RSR 8/4/80 CHANGED I/O FOR VIXEN
; RSR 8/21/80 CHANGED I/O FOR VIXEN MOD
; RSR 8/25/80 CHANGED I/O FOR VIXEN MOD2
; RSR 12/11/81 MODIFY I/O FOR VIC-40
; RSR 2/9/82 ADD VIC TURN ON, REPLACE SAH WITH PRP
|
{
"language": "Assembly"
}
|
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build linux
// +build arm64
// +build !gccgo
#include "textflag.h"
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
B syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
BL runtime·entersyscall(SB)
MOVD a1+8(FP), R0
MOVD a2+16(FP), R1
MOVD a3+24(FP), R2
MOVD $0, R3
MOVD $0, R4
MOVD $0, R5
MOVD trap+0(FP), R8 // syscall entry
SVC
MOVD R0, r1+32(FP) // r1
MOVD R1, r2+40(FP) // r2
BL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
B syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOVD a1+8(FP), R0
MOVD a2+16(FP), R1
MOVD a3+24(FP), R2
MOVD $0, R3
MOVD $0, R4
MOVD $0, R5
MOVD trap+0(FP), R8 // syscall entry
SVC
MOVD R0, r1+32(FP)
MOVD R1, r2+40(FP)
RET
|
{
"language": "Assembly"
}
|
Var newStartMenuLink
Var oldStartMenuLink
Var newDesktopLink
Var oldDesktopLink
Var oldShortcutName
Var oldMenuDirectory
!include "common.nsh"
!include "MUI2.nsh"
!include "multiUser.nsh"
!include "allowOnlyOneInstallerInstance.nsh"
!ifdef INSTALL_MODE_PER_ALL_USERS
!ifdef BUILD_UNINSTALLER
RequestExecutionLevel user
!else
RequestExecutionLevel admin
!endif
!else
RequestExecutionLevel user
!endif
!ifdef BUILD_UNINSTALLER
SilentInstall silent
!else
Var appExe
Var launchLink
!endif
!ifdef ONE_CLICK
!include "oneClick.nsh"
!else
!include "assistedInstaller.nsh"
!endif
!insertmacro addLangs
!ifmacrodef customHeader
!insertmacro customHeader
!endif
Function .onInit
!ifmacrodef preInit
!insertmacro preInit
!endif
!ifdef DISPLAY_LANG_SELECTOR
!insertmacro MUI_LANGDLL_DISPLAY
!endif
!ifdef BUILD_UNINSTALLER
WriteUninstaller "${UNINSTALLER_OUT_FILE}"
!insertmacro quitSuccess
!else
!insertmacro check64BitAndSetRegView
!ifdef ONE_CLICK
!insertmacro ALLOW_ONLY_ONE_INSTALLER_INSTANCE
!else
${IfNot} ${UAC_IsInnerInstance}
!insertmacro ALLOW_ONLY_ONE_INSTALLER_INSTANCE
${EndIf}
!endif
!insertmacro initMultiUser
!ifmacrodef customInit
!insertmacro customInit
!endif
!ifmacrodef addLicenseFiles
InitPluginsDir
!insertmacro addLicenseFiles
!endif
!endif
FunctionEnd
!ifndef BUILD_UNINSTALLER
!include "installUtil.nsh"
!endif
Section "install"
!ifndef BUILD_UNINSTALLER
!include "installSection.nsh"
!endif
SectionEnd
!ifdef BUILD_UNINSTALLER
!include "uninstaller.nsh"
!endif
|
{
"language": "Assembly"
}
|
// RUN: %check_clang_tidy %s fuchsia-restrict-system-includes %t \
// RUN: -- -config="{CheckOptions: [{key: fuchsia-restrict-system-includes.Includes, value: 'cstd*'}]}" \
// RUN: -- -I %S/Inputs/fuchsia-restrict-system-includes -isystem %S/Inputs/fuchsia-restrict-system-includes/system
#include <cstdlib.h>
#include <cstdarg.h>
#include <t.h>
// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: system include t.h not allowed
// CHECK-FIXES-NOT: #include <t.h>
|
{
"language": "Assembly"
}
|
# REQUIRES: x86
# RUN: llvm-mc -triple=x86_64-windows-msvc -filetype=obj -o %t.obj %s
# RUN: cp %t.obj %t.dupl.obj
# RUN: not lld-link /out:%t.exe %t.obj %t.dupl.obj 2>&1 | FileCheck %s
# CHECK: error: duplicate symbol: main
# CHECK-NEXT: >>> defined at file1.cpp:2
# CHECK-NEXT: >>> {{.*}}.obj
# CHECK-NEXT: >>> defined at {{.*}}.obj
.cv_file 1 "file1.cpp" "EDA15C78BB573E49E685D8549286F33C" 1
.cv_file 2 "file2.cpp" "EDA15C78BB573E49E685D8549286F33D" 1
.section .text,"xr",one_only,main
.globl main
main:
.cv_func_id 0
.cv_loc 0 1 1 0 is_stmt 0
.cv_loc 0 1 2 0
retq
.Lfunc_end0:
.section .debug$S,"dr",associative,main
.long 4
.cv_linetable 0, main, .Lfunc_end0
.section .debug$S,"dr"
.long 4
.cv_filechecksums
.cv_stringtable
|
{
"language": "Assembly"
}
|
// Test host codegen.
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
// Test target codegen - host bc file has to be created first.
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// SIMD-ONLY1-NOT: {{__kmpc|__tgt}}
// expected-no-diagnostics
#ifndef HEADER
#define HEADER
// CHECK-DAG: [[TT:%.+]] = type { i64, i8 }
// CHECK-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]], i32, i32 }
// CHECK-DAG: [[DEVTY:%.+]] = type { i8*, i8*, [[ENTTY]]*, [[ENTTY]]* }
// CHECK-DAG: [[DSCTY:%.+]] = type { i32, [[DEVTY]]*, [[ENTTY]]*, [[ENTTY]]* }
// TCHECK: [[ENTTY:%.+]] = type { i8*, i8*, i{{32|64}}, i32, i32 }
// CHECK-DAG: $[[REGFN:\.omp_offloading\..+]] = comdat
// CHECK-DAG: [[SIZET:@.+]] = private unnamed_addr constant [2 x i[[SZ]]] [i[[SZ]] 0, i[[SZ]] 4]
// CHECK-DAG: [[MAPT:@.+]] = private unnamed_addr constant [2 x i64] [i64 544, i64 800]
// CHECK-DAG: @{{.*}} = weak constant i8 0
// TCHECK: @{{.+}} = weak constant [[ENTTY]]
// TCHECK: @{{.+}} = {{.*}}constant [[ENTTY]]
// TCHECK-NOT: @{{.+}} = weak constant [[ENTTY]]
// Check if offloading descriptor is created.
// CHECK: [[ENTBEGIN:@.+]] = external constant [[ENTTY]]
// CHECK: [[ENTEND:@.+]] = external constant [[ENTTY]]
// CHECK: [[DEVBEGIN:@.+]] = extern_weak constant i8
// CHECK: [[DEVEND:@.+]] = extern_weak constant i8
// CHECK: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[DEVTY]]] [{{.+}} { i8* [[DEVBEGIN]], i8* [[DEVEND]], [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }], comdat($[[REGFN]])
// CHECK: [[DESC:@.+]] = internal constant [[DSCTY]] { i32 1, [[DEVTY]]* getelementptr inbounds ([1 x [[DEVTY]]], [1 x [[DEVTY]]]* [[IMAGES]], i32 0, i32 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }, comdat($[[REGFN]])
// Check target registration is registered as a Ctor.
// CHECK: appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* @[[REGFN]], i8* bitcast (void ()* @[[REGFN]] to i8*) }]
template<typename tx, typename ty>
struct TT{
tx X;
ty Y;
};
int global;
extern int global;
// CHECK: define {{.*}}[[FOO:@.+]](
int foo(int n) {
int a = 0;
short aa = 0;
float b[10];
float bn[n];
double c[5][10];
double cn[5][n];
TT<long long, char> d;
static long *plocal;
// CHECK: [[ADD:%.+]] = add nsw i32
// CHECK: store i32 [[ADD]], i32* [[DEVICE_CAP:%.+]],
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 [[GTID:%.+]], i32 1, i[[SZ]] {{20|40}}, i[[SZ]] 4, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY0:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY0:%.+]]*
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 3
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i32 0, i32 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call void @__kmpc_omp_wait_deps(%struct.ident_t* @0, i32 [[GTID]], i32 4, i8* [[DEP]], i32 0, i8* null)
// CHECK: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]])
// CHECK: call i32 [[TASK_ENTRY0]](i32 [[GTID]], [[TASK_TY0]]* [[BC_TASK]])
// CHECK: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]])
#pragma omp target teams device(global + a) depend(in: global) depend(out: a, b, cn[4])
{
}
// CHECK: [[ADD:%.+]] = add nsw i32
// CHECK: store i32 [[ADD]], i32* [[DEVICE_CAP:%.+]],
// CHECK: [[BOOL:%.+]] = icmp ne i32 %{{.+}}, 0
// CHECK: br i1 [[BOOL]], label %[[THEN:.+]], label %[[ELSE:.+]]
// CHECK: [[THEN]]:
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP:%.+]], i32 0, i32 0
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P:%.+]], i32 0, i32 0
// CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]**
// CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]**
// CHECK-DAG: store i[[SZ]]* [[BP0:%[^,]+]], i[[SZ]]** [[CBPADDR0]]
// CHECK-DAG: store i[[SZ]]* [[BP0]], i[[SZ]]** [[CPADDR0]]
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 1
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 1
// CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]*
// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]*
// CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], i[[SZ]]* [[CBPADDR1]]
// CHECK-DAG: store i[[SZ]] [[BP1]], i[[SZ]]* [[CPADDR1]]
// CHECK-DAG: getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 0
// CHECK-DAG: getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 0
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 [[GTID]], i32 1, i[[SZ]] {{104|52}}, i[[SZ]] {{16|12}}, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY1_:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY1_:%.+]]*
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i32 0, i32 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]], i32 3, i8* [[DEP]], i32 0, i8* null)
// CHECK: br label %[[EXIT:.+]]
// CHECK: [[ELSE]]:
// CHECK-NOT: getelementptr inbounds [2 x i8*], [2 x i8*]*
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 [[GTID]], i32 1, i[[SZ]] {{56|28}}, i[[SZ]] {{16|12}}, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY1__:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY1__:%.+]]*
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i32 0, i32 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]], i32 3, i8* [[DEP]], i32 0, i8* null)
// CHECK: br label %[[EXIT:.+]]
// CHECK: [[EXIT]]:
#pragma omp target teams device(global + a) nowait depend(inout: global, a, bn) if(a)
{
static int local1;
*plocal = global;
local1 = global;
}
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 [[GTID]], i32 1, i[[SZ]] {{48|24}}, i[[SZ]] 4, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY2:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY2:%.+]]*
// CHECK: getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* %{{.+}}, i32 0, i32 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call void @__kmpc_omp_wait_deps(%struct.ident_t* @0, i32 [[GTID]], i32 1, i8* [[DEP]], i32 0, i8* null)
// CHECK: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]])
// CHECK: call i32 [[TASK_ENTRY2]](i32 [[GTID]], [[TASK_TY2]]* [[BC_TASK]])
// CHECK: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]])
#pragma omp target teams if(0) firstprivate(global) depend(out:global)
{
global += 1;
}
return a;
}
// Check that the offloading functions are emitted and that the arguments are
// correct and loaded correctly for the target regions in foo().
// CHECK: define internal void [[HVT0:@.+]]()
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias)
// CHECK: store void (i8*, ...)* null, void (i8*, ...)** %
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: [[DEVICE:%.+]] = sext i32 [[DEV]] to i64
// CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams(i64 [[DEVICE]], i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i64* null, i32 0, i32 0)
// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT0]]()
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
// CHECK: ret i32 0
// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}})
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias)
// CHECK: call void (i8*, ...) %
// CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i[[SZ]]], [2 x i[[SZ]]]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: [[DEVICE:%.+]] = sext i32 [[DEV]] to i64
// CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams_nowait(i64 [[DEVICE]], i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SZT]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* [[MAPT]], i32 0, i32 0), i32 0, i32 0)
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: [[BP0:%.+]] = load i[[SZ]]*, i[[SZ]]** %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]])
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
// CHECK: ret i32 0
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias)
// CHECK: call void (i8*, ...) %
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[BP0:%.+]] = load i[[SZ]]*, i[[SZ]]** %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]])
// CHECK: ret i32 0
// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}})
// Create stack storage and store argument in there.
// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align
// CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align
// CHECK-64: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32*
// CHECK-64: load i32, i32* [[AA_CADDR]], align
// CHECK-32: load i32, i32* [[AA_ADDR]], align
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias)
// CHECK: call void (i8*, ...) %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT2]](i[[SZ]] [[BP1]])
// CHECK: ret i32 0
#endif
|
{
"language": "Assembly"
}
|
# RUN: llc -debug-entry-values -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s
#
# CHECK: DW_TAG_GNU_call_site
# CHECK-NEXT: DW_AT_abstract_origin {{.*}} "foo"
# CHECK-NEXT: DW_AT_low_pc
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
# CHECK-NEXT: DW_AT_location (DW_OP_reg2 RCX)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg14 R14+0)
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
# CHECK-NEXT: DW_AT_location (DW_OP_reg1 RDX)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_fbreg +8)
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
# CHECK-NEXT: DW_AT_location (DW_OP_reg5 RDI)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg4 RSI))
# CHECK-EMPTY:
# CHECK: DW_TAG_GNU_call_site
# CHECK-NEXT: DW_AT_abstract_origin {{.*}}"foo"
# CHECK-NEXT: DW_AT_low_pc
# CHECK-EMPTY:
# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
# RCX loads memory location. We can't rely that memory location won't be changed.
# CHECK-NOT: DW_AT_location (DW_OP_reg2 RCX)
# CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_lit4)
# CHECK-EMPTY:
# CHECK-NOT: DW_TAG_GNU_call_site_parameter
#
# Check that call site interpretation analysis can interpret instructions such
# as move immediate, register to register moves, stack loading and LEA
# instructions. Last negative check should verify that we are not producing
# interpretation for RDX register since its loaded value is call clobberable.
# Also check that we are generating proper call site debug entities.
--- |
; ModuleID = 'dbgcall-site-interpretation.c'
source_filename = "dbgcall-site-interpretation.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nounwind uwtable
define dso_local i32 @baa(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) local_unnamed_addr !dbg !9 {
entry:
%arg3.addr = alloca i32, align 4
%local2 = alloca i32, align 4
call void @llvm.dbg.value(metadata i32 %arg1, metadata !14, metadata !DIExpression()), !dbg !21
call void @llvm.dbg.value(metadata i32 %arg2, metadata !15, metadata !DIExpression()), !dbg !21
call void @llvm.dbg.value(metadata i32 %arg3, metadata !16, metadata !DIExpression()), !dbg !21
store i32 %arg3, i32* %arg3.addr, align 4
call void @llvm.dbg.value(metadata i32 %arg4, metadata !17, metadata !DIExpression()), !dbg !21
%0 = bitcast i32* %local2 to i8*, !dbg !21
call void @llvm.dbg.value(metadata i32* %arg3.addr, metadata !16, metadata !DIExpression(DW_OP_deref)), !dbg !21
%call = call i32 @foo(i32 %arg1, i32 %arg2, i32* nonnull %arg3.addr, i32 %arg4), !dbg !21
call void @llvm.dbg.value(metadata i32 %call, metadata !18, metadata !DIExpression()), !dbg !21
%cmp = icmp sgt i32 %arg1, %arg2, !dbg !21
%1 = load i32, i32* %arg3.addr, align 4, !dbg !21
call void @llvm.dbg.value(metadata i32 %1, metadata !16, metadata !DIExpression()), !dbg !21
%add = add nsw i32 %1, %arg1, !dbg !21
%add1 = add nsw i32 %arg4, %arg2, !dbg !21
%local1.0 = select i1 %cmp, i32 %add, i32 %add1, !dbg !21
call void @llvm.dbg.value(metadata i32 %local1.0, metadata !18, metadata !DIExpression()), !dbg !21
%rem = srem i32 %1, %arg1, !dbg !21
%tobool = icmp eq i32 %rem, 0, !dbg !21
%mul = mul nsw i32 %1, %arg1, !dbg !21
%add3 = add nsw i32 %1, %arg4, !dbg !21
%storemerge = select i1 %tobool, i32 %mul, i32 %add3, !dbg !21
call void @llvm.dbg.value(metadata i32 %storemerge, metadata !19, metadata !DIExpression()), !dbg !21
store i32 %storemerge, i32* %local2, align 4, !dbg !21
%cmp6 = icmp slt i32 %storemerge, %arg4, !dbg !21
%local3.0.v = select i1 %cmp6, i32 %local1.0, i32 %arg1, !dbg !21
%local3.0 = mul nsw i32 %local3.0.v, %storemerge, !dbg !21
call void @llvm.dbg.value(metadata i32 %local3.0, metadata !20, metadata !DIExpression()), !dbg !21
call void @llvm.dbg.value(metadata i32* %local2, metadata !19, metadata !DIExpression(DW_OP_deref)), !dbg !21
%call12 = call i32 @foo(i32 %local1.0, i32 4, i32* nonnull %local2, i32 %local3.0), !dbg !21
call void @llvm.dbg.value(metadata i32 %call12, metadata !14, metadata !DIExpression()), !dbg !21
%add13 = add nsw i32 %call12, 4, !dbg !21
ret i32 %add13, !dbg !21
}
declare !dbg !4 dso_local i32 @foo(i32, i32, i32*, i32) local_unnamed_addr
; Function Attrs: nounwind readnone speculatable
declare void @llvm.dbg.value(metadata, metadata, metadata)
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!5, !6, !7}
!llvm.ident = !{!8}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 9.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, nameTableKind: None)
!1 = !DIFile(filename: "dbgcall-site-interpretation.c", directory: "/dir")
!2 = !{}
!3 = !{!4}
!4 = !DISubprogram(name: "foo", scope: !1, file: !1, line: 9, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2)
!5 = !{i32 2, !"Dwarf Version", i32 4}
!6 = !{i32 2, !"Debug Info Version", i32 3}
!7 = !{i32 1, !"wchar_size", i32 4}
!8 = !{!"clang version 9.0.0"}
!9 = distinct !DISubprogram(name: "baa", scope: !1, file: !1, line: 10, type: !10, scopeLine: 10, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !13)
!10 = !DISubroutineType(types: !11)
!11 = !{!12, !12, !12, !12, !12}
!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!13 = !{!14, !15, !16, !17, !18, !19, !20}
!14 = !DILocalVariable(name: "arg1", arg: 1, scope: !9, file: !1, line: 10, type: !12)
!15 = !DILocalVariable(name: "arg2", arg: 2, scope: !9, file: !1, line: 10, type: !12, flags: DIFlagArgumentNotModified)
!16 = !DILocalVariable(name: "arg3", arg: 3, scope: !9, file: !1, line: 10, type: !12)
!17 = !DILocalVariable(name: "arg4", arg: 4, scope: !9, file: !1, line: 10, type: !12, flags: DIFlagArgumentNotModified)
!18 = !DILocalVariable(name: "local1", scope: !9, file: !1, line: 11, type: !12)
!19 = !DILocalVariable(name: "local2", scope: !9, file: !1, line: 11, type: !12)
!20 = !DILocalVariable(name: "local3", scope: !9, file: !1, line: 11, type: !12)
!21 = !DILocation(line: 10, column: 13, scope: !9)
...
---
name: baa
liveins:
- { reg: '$edi', virtual-reg: '' }
- { reg: '$esi', virtual-reg: '' }
- { reg: '$edx', virtual-reg: '' }
- { reg: '$ecx', virtual-reg: '' }
callSites:
- { bb: 0, offset: 23, fwdArgRegs:
- { arg: 0, reg: '$edi' }
- { arg: 1, reg: '$esi' }
- { arg: 2, reg: '$rdx' }
- { arg: 3, reg: '$ecx' } }
- { bb: 0, offset: 49, fwdArgRegs:
- { arg: 0, reg: '$edi' }
- { arg: 1, reg: '$esi' }
- { arg: 2, reg: '$rdx' }
- { arg: 3, reg: '$ecx' } }
body: |
bb.0.entry:
liveins: $ecx, $edi, $edx, $esi, $r15, $r14, $rbx
DBG_VALUE $edi, $noreg, !14, !DIExpression(), debug-location !21
DBG_VALUE $esi, $noreg, !15, !DIExpression(), debug-location !21
DBG_VALUE $edx, $noreg, !16, !DIExpression(), debug-location !21
DBG_VALUE $ecx, $noreg, !17, !DIExpression(), debug-location !21
frame-setup PUSH64r killed $r15, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
frame-setup PUSH64r killed $r14, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 24
frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 32
$rsp = frame-setup SUB64ri8 $rsp, 16, implicit-def dead $eflags
CFI_INSTRUCTION def_cfa_offset 48
CFI_INSTRUCTION offset $rbx, -32
CFI_INSTRUCTION offset $r14, -24
CFI_INSTRUCTION offset $r15, -16
$r14d = MOV32rr $ecx, implicit-def $r14
DBG_VALUE $edx, $noreg, !16, !DIExpression(), debug-location !21
$r15d = MOV32rr $esi, implicit-def $r15
$ebx = MOV32rr $edi, implicit-def $rbx
$edi = MOV32rr $esi
MOV32mr $rsp, 1, $noreg, 8, $noreg, killed renamable $edx :: (store 4 into %ir.arg3.addr)
renamable $rdx = LEA64r $rsp, 1, $noreg, 8, $noreg
renamable $ecx = MOV32rr $r14d,
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $rdx, implicit $ecx, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, implicit-def $rax, debug-location !21
DBG_VALUE $noreg, $noreg, !18, !DIExpression(), debug-location !21
$rdx = MOV64rr renamable $rax
$ecx = KILL renamable $ecx, implicit-def $rcx
renamable $eax = LEA64_32r renamable $rcx, 1, renamable $rbx, 0, $noreg, debug-location !21
renamable $edi = LEA64_32r renamable $r14, 1, renamable $r15, 0, $noreg, debug-location !21
CMP32rr renamable $ebx, renamable $r15d, implicit-def $eflags, implicit killed $r15, debug-location !21
renamable $edi = CMOV32rr killed renamable $edi, killed renamable $eax, 15, implicit killed $eflags, debug-location !21
DBG_VALUE $edi, $noreg, !18, !DIExpression(), debug-location !21
$eax = MOV32rr $ecx, debug-location !21
CDQ implicit-def $eax, implicit-def $edx, implicit $eax, debug-location !21
IDIV32r renamable $ebx, implicit-def dead $eax, implicit-def $edx, implicit-def dead $eflags, implicit $eax, implicit $edx, debug-location !21
$eax = MOV32rr $ecx, debug-location !21
renamable $eax = nsw IMUL32rr killed renamable $eax, renamable $ebx, implicit-def dead $eflags, debug-location !21
renamable $ecx = nsw ADD32rr renamable $ecx, renamable $r14d, implicit-def dead $eflags, implicit killed $rcx, implicit-def $rcx, debug-location !21
TEST32rr killed renamable $edx, renamable $edx, implicit-def $eflags, debug-location !21
renamable $ecx = CMOV32rr renamable $ecx, killed renamable $eax, 4, implicit killed $eflags, implicit killed $rcx, implicit-def $rcx, debug-location !21
DBG_VALUE $ecx, $noreg, !19, !DIExpression(), debug-location !21
MOV32mr $rsp, 1, $noreg, 12, $noreg, renamable $ecx, debug-location !21 :: (store 4 into %ir.local2)
CMP32rr renamable $ecx, renamable $r14d, implicit-def $eflags, implicit killed $r14, debug-location !21
renamable $ebx = CMOV32rr renamable $ebx, renamable $edi, 12, implicit killed $eflags, implicit killed $rbx, implicit-def $rbx, debug-location !21
renamable $ecx = nsw IMUL32rr renamable $ecx, renamable $ebx, implicit-def dead $eflags, implicit killed $rbx, implicit killed $rcx, implicit-def $rcx, debug-location !21
DBG_VALUE $rsp, $noreg, !19, !DIExpression(DW_OP_plus_uconst, 12, DW_OP_deref), debug-location !21
DBG_VALUE $ecx, $noreg, !20, !DIExpression(), debug-location !21
$esi = MOV32ri 4, debug-location !21
renamable $ecx = MOV32rm $rsp, 1, $noreg, 8, $noreg, implicit-def $rcx, debug-location !21 :: (dereferenceable load 4 from %ir.arg3.addr)
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $rdx, implicit $ecx, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, implicit-def $rax, debug-location !21
DBG_VALUE $eax, $noreg, !14, !DIExpression(), debug-location !21
renamable $eax = nsw ADD32ri8 killed renamable $eax, 4, implicit-def dead $eflags, debug-location !21
$rsp = frame-destroy ADD64ri8 $rsp, 16, implicit-def dead $eflags, debug-location !21
CFI_INSTRUCTION def_cfa_offset 32, debug-location !21
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21
CFI_INSTRUCTION def_cfa_offset 24, debug-location !21
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21
DBG_VALUE $ecx, $noreg, !17, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !21
CFI_INSTRUCTION def_cfa_offset 16, debug-location !21
$r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21
DBG_VALUE $esi, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !21
CFI_INSTRUCTION def_cfa_offset 8, debug-location !21
RETQ $eax, debug-location !21
...
|
{
"language": "Assembly"
}
|
/*
* Cryptographic API.
*
* Serpent Cipher Algorithm.
*
* Copyright (C) 2002 Dag Arne Osvik <osvik@ii.uib.no>
* 2003 Herbert Valerio Riedel <hvr@gnu.org>
*
* Added tnepres support:
* Ruben Jesus Garcia Hernandez <ruben@ugr.es>, 18.10.2004
* Based on code by hvr
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <asm/byteorder.h>
#include <linux/crypto.h>
#include <linux/types.h>
#include <crypto/serpent.h>
/* Key is padded to the maximum of 256 bits before round key generation.
* Any key length <= 256 bits (32 bytes) is allowed by the algorithm.
*/
#define PHI 0x9e3779b9UL
#define keyiter(a, b, c, d, i, j) \
({ b ^= d; b ^= c; b ^= a; b ^= PHI ^ i; b = rol32(b, 11); k[j] = b; })
#define loadkeys(x0, x1, x2, x3, i) \
({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
#define storekeys(x0, x1, x2, x3, i) \
({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
#define store_and_load_keys(x0, x1, x2, x3, s, l) \
({ storekeys(x0, x1, x2, x3, s); loadkeys(x0, x1, x2, x3, l); })
#define K(x0, x1, x2, x3, i) ({ \
x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
x1 ^= k[4*(i)+1]; x0 ^= k[4*(i)+0]; \
})
#define LK(x0, x1, x2, x3, x4, i) ({ \
x0 = rol32(x0, 13);\
x2 = rol32(x2, 3); x1 ^= x0; x4 = x0 << 3; \
x3 ^= x2; x1 ^= x2; \
x1 = rol32(x1, 1); x3 ^= x4; \
x3 = rol32(x3, 7); x4 = x1; \
x0 ^= x1; x4 <<= 7; x2 ^= x3; \
x0 ^= x3; x2 ^= x4; x3 ^= k[4*i+3]; \
x1 ^= k[4*i+1]; x0 = rol32(x0, 5); x2 = rol32(x2, 22);\
x0 ^= k[4*i+0]; x2 ^= k[4*i+2]; \
})
#define KL(x0, x1, x2, x3, x4, i) ({ \
x0 ^= k[4*i+0]; x1 ^= k[4*i+1]; x2 ^= k[4*i+2]; \
x3 ^= k[4*i+3]; x0 = ror32(x0, 5); x2 = ror32(x2, 22);\
x4 = x1; x2 ^= x3; x0 ^= x3; \
x4 <<= 7; x0 ^= x1; x1 = ror32(x1, 1); \
x2 ^= x4; x3 = ror32(x3, 7); x4 = x0 << 3; \
x1 ^= x0; x3 ^= x4; x0 = ror32(x0, 13);\
x1 ^= x2; x3 ^= x2; x2 = ror32(x2, 3); \
})
#define S0(x0, x1, x2, x3, x4) ({ \
x4 = x3; \
x3 |= x0; x0 ^= x4; x4 ^= x2; \
x4 = ~x4; x3 ^= x1; x1 &= x0; \
x1 ^= x4; x2 ^= x0; x0 ^= x3; \
x4 |= x0; x0 ^= x2; x2 &= x1; \
x3 ^= x2; x1 = ~x1; x2 ^= x4; \
x1 ^= x2; \
})
#define S1(x0, x1, x2, x3, x4) ({ \
x4 = x1; \
x1 ^= x0; x0 ^= x3; x3 = ~x3; \
x4 &= x1; x0 |= x1; x3 ^= x2; \
x0 ^= x3; x1 ^= x3; x3 ^= x4; \
x1 |= x4; x4 ^= x2; x2 &= x0; \
x2 ^= x1; x1 |= x0; x0 = ~x0; \
x0 ^= x2; x4 ^= x1; \
})
#define S2(x0, x1, x2, x3, x4) ({ \
x3 = ~x3; \
x1 ^= x0; x4 = x0; x0 &= x2; \
x0 ^= x3; x3 |= x4; x2 ^= x1; \
x3 ^= x1; x1 &= x0; x0 ^= x2; \
x2 &= x3; x3 |= x1; x0 = ~x0; \
x3 ^= x0; x4 ^= x0; x0 ^= x2; \
x1 |= x2; \
})
#define S3(x0, x1, x2, x3, x4) ({ \
x4 = x1; \
x1 ^= x3; x3 |= x0; x4 &= x0; \
x0 ^= x2; x2 ^= x1; x1 &= x3; \
x2 ^= x3; x0 |= x4; x4 ^= x3; \
x1 ^= x0; x0 &= x3; x3 &= x4; \
x3 ^= x2; x4 |= x1; x2 &= x1; \
x4 ^= x3; x0 ^= x3; x3 ^= x2; \
})
#define S4(x0, x1, x2, x3, x4) ({ \
x4 = x3; \
x3 &= x0; x0 ^= x4; \
x3 ^= x2; x2 |= x4; x0 ^= x1; \
x4 ^= x3; x2 |= x0; \
x2 ^= x1; x1 &= x0; \
x1 ^= x4; x4 &= x2; x2 ^= x3; \
x4 ^= x0; x3 |= x1; x1 = ~x1; \
x3 ^= x0; \
})
#define S5(x0, x1, x2, x3, x4) ({ \
x4 = x1; x1 |= x0; \
x2 ^= x1; x3 = ~x3; x4 ^= x0; \
x0 ^= x2; x1 &= x4; x4 |= x3; \
x4 ^= x0; x0 &= x3; x1 ^= x3; \
x3 ^= x2; x0 ^= x1; x2 &= x4; \
x1 ^= x2; x2 &= x0; \
x3 ^= x2; \
})
#define S6(x0, x1, x2, x3, x4) ({ \
x4 = x1; \
x3 ^= x0; x1 ^= x2; x2 ^= x0; \
x0 &= x3; x1 |= x3; x4 = ~x4; \
x0 ^= x1; x1 ^= x2; \
x3 ^= x4; x4 ^= x0; x2 &= x0; \
x4 ^= x1; x2 ^= x3; x3 &= x1; \
x3 ^= x0; x1 ^= x2; \
})
#define S7(x0, x1, x2, x3, x4) ({ \
x1 = ~x1; \
x4 = x1; x0 = ~x0; x1 &= x2; \
x1 ^= x3; x3 |= x4; x4 ^= x2; \
x2 ^= x3; x3 ^= x0; x0 |= x1; \
x2 &= x0; x0 ^= x4; x4 ^= x3; \
x3 &= x0; x4 ^= x1; \
x2 ^= x4; x3 ^= x1; x4 |= x0; \
x4 ^= x1; \
})
#define SI0(x0, x1, x2, x3, x4) ({ \
x4 = x3; x1 ^= x0; \
x3 |= x1; x4 ^= x1; x0 = ~x0; \
x2 ^= x3; x3 ^= x0; x0 &= x1; \
x0 ^= x2; x2 &= x3; x3 ^= x4; \
x2 ^= x3; x1 ^= x3; x3 &= x0; \
x1 ^= x0; x0 ^= x2; x4 ^= x3; \
})
#define SI1(x0, x1, x2, x3, x4) ({ \
x1 ^= x3; x4 = x0; \
x0 ^= x2; x2 = ~x2; x4 |= x1; \
x4 ^= x3; x3 &= x1; x1 ^= x2; \
x2 &= x4; x4 ^= x1; x1 |= x3; \
x3 ^= x0; x2 ^= x0; x0 |= x4; \
x2 ^= x4; x1 ^= x0; \
x4 ^= x1; \
})
#define SI2(x0, x1, x2, x3, x4) ({ \
x2 ^= x1; x4 = x3; x3 = ~x3; \
x3 |= x2; x2 ^= x4; x4 ^= x0; \
x3 ^= x1; x1 |= x2; x2 ^= x0; \
x1 ^= x4; x4 |= x3; x2 ^= x3; \
x4 ^= x2; x2 &= x1; \
x2 ^= x3; x3 ^= x4; x4 ^= x0; \
})
#define SI3(x0, x1, x2, x3, x4) ({ \
x2 ^= x1; \
x4 = x1; x1 &= x2; \
x1 ^= x0; x0 |= x4; x4 ^= x3; \
x0 ^= x3; x3 |= x1; x1 ^= x2; \
x1 ^= x3; x0 ^= x2; x2 ^= x3; \
x3 &= x1; x1 ^= x0; x0 &= x2; \
x4 ^= x3; x3 ^= x0; x0 ^= x1; \
})
#define SI4(x0, x1, x2, x3, x4) ({ \
x2 ^= x3; x4 = x0; x0 &= x1; \
x0 ^= x2; x2 |= x3; x4 = ~x4; \
x1 ^= x0; x0 ^= x2; x2 &= x4; \
x2 ^= x0; x0 |= x4; \
x0 ^= x3; x3 &= x2; \
x4 ^= x3; x3 ^= x1; x1 &= x0; \
x4 ^= x1; x0 ^= x3; \
})
#define SI5(x0, x1, x2, x3, x4) ({ \
x4 = x1; x1 |= x2; \
x2 ^= x4; x1 ^= x3; x3 &= x4; \
x2 ^= x3; x3 |= x0; x0 = ~x0; \
x3 ^= x2; x2 |= x0; x4 ^= x1; \
x2 ^= x4; x4 &= x0; x0 ^= x1; \
x1 ^= x3; x0 &= x2; x2 ^= x3; \
x0 ^= x2; x2 ^= x4; x4 ^= x3; \
})
#define SI6(x0, x1, x2, x3, x4) ({ \
x0 ^= x2; \
x4 = x0; x0 &= x3; x2 ^= x3; \
x0 ^= x2; x3 ^= x1; x2 |= x4; \
x2 ^= x3; x3 &= x0; x0 = ~x0; \
x3 ^= x1; x1 &= x2; x4 ^= x0; \
x3 ^= x4; x4 ^= x2; x0 ^= x1; \
x2 ^= x0; \
})
#define SI7(x0, x1, x2, x3, x4) ({ \
x4 = x3; x3 &= x0; x0 ^= x2; \
x2 |= x4; x4 ^= x1; x0 = ~x0; \
x1 |= x3; x4 ^= x0; x0 &= x2; \
x0 ^= x1; x1 &= x2; x3 ^= x2; \
x4 ^= x3; x2 &= x3; x3 |= x0; \
x1 ^= x4; x3 ^= x4; x4 &= x0; \
x4 ^= x2; \
})
int __serpent_setkey(struct serpent_ctx *ctx, const u8 *key,
unsigned int keylen)
{
u32 *k = ctx->expkey;
u8 *k8 = (u8 *)k;
u32 r0, r1, r2, r3, r4;
int i;
/* Copy key, add padding */
for (i = 0; i < keylen; ++i)
k8[i] = key[i];
if (i < SERPENT_MAX_KEY_SIZE)
k8[i++] = 1;
while (i < SERPENT_MAX_KEY_SIZE)
k8[i++] = 0;
/* Expand key using polynomial */
r0 = le32_to_cpu(k[3]);
r1 = le32_to_cpu(k[4]);
r2 = le32_to_cpu(k[5]);
r3 = le32_to_cpu(k[6]);
r4 = le32_to_cpu(k[7]);
keyiter(le32_to_cpu(k[0]), r0, r4, r2, 0, 0);
keyiter(le32_to_cpu(k[1]), r1, r0, r3, 1, 1);
keyiter(le32_to_cpu(k[2]), r2, r1, r4, 2, 2);
keyiter(le32_to_cpu(k[3]), r3, r2, r0, 3, 3);
keyiter(le32_to_cpu(k[4]), r4, r3, r1, 4, 4);
keyiter(le32_to_cpu(k[5]), r0, r4, r2, 5, 5);
keyiter(le32_to_cpu(k[6]), r1, r0, r3, 6, 6);
keyiter(le32_to_cpu(k[7]), r2, r1, r4, 7, 7);
keyiter(k[0], r3, r2, r0, 8, 8);
keyiter(k[1], r4, r3, r1, 9, 9);
keyiter(k[2], r0, r4, r2, 10, 10);
keyiter(k[3], r1, r0, r3, 11, 11);
keyiter(k[4], r2, r1, r4, 12, 12);
keyiter(k[5], r3, r2, r0, 13, 13);
keyiter(k[6], r4, r3, r1, 14, 14);
keyiter(k[7], r0, r4, r2, 15, 15);
keyiter(k[8], r1, r0, r3, 16, 16);
keyiter(k[9], r2, r1, r4, 17, 17);
keyiter(k[10], r3, r2, r0, 18, 18);
keyiter(k[11], r4, r3, r1, 19, 19);
keyiter(k[12], r0, r4, r2, 20, 20);
keyiter(k[13], r1, r0, r3, 21, 21);
keyiter(k[14], r2, r1, r4, 22, 22);
keyiter(k[15], r3, r2, r0, 23, 23);
keyiter(k[16], r4, r3, r1, 24, 24);
keyiter(k[17], r0, r4, r2, 25, 25);
keyiter(k[18], r1, r0, r3, 26, 26);
keyiter(k[19], r2, r1, r4, 27, 27);
keyiter(k[20], r3, r2, r0, 28, 28);
keyiter(k[21], r4, r3, r1, 29, 29);
keyiter(k[22], r0, r4, r2, 30, 30);
keyiter(k[23], r1, r0, r3, 31, 31);
k += 50;
keyiter(k[-26], r2, r1, r4, 32, -18);
keyiter(k[-25], r3, r2, r0, 33, -17);
keyiter(k[-24], r4, r3, r1, 34, -16);
keyiter(k[-23], r0, r4, r2, 35, -15);
keyiter(k[-22], r1, r0, r3, 36, -14);
keyiter(k[-21], r2, r1, r4, 37, -13);
keyiter(k[-20], r3, r2, r0, 38, -12);
keyiter(k[-19], r4, r3, r1, 39, -11);
keyiter(k[-18], r0, r4, r2, 40, -10);
keyiter(k[-17], r1, r0, r3, 41, -9);
keyiter(k[-16], r2, r1, r4, 42, -8);
keyiter(k[-15], r3, r2, r0, 43, -7);
keyiter(k[-14], r4, r3, r1, 44, -6);
keyiter(k[-13], r0, r4, r2, 45, -5);
keyiter(k[-12], r1, r0, r3, 46, -4);
keyiter(k[-11], r2, r1, r4, 47, -3);
keyiter(k[-10], r3, r2, r0, 48, -2);
keyiter(k[-9], r4, r3, r1, 49, -1);
keyiter(k[-8], r0, r4, r2, 50, 0);
keyiter(k[-7], r1, r0, r3, 51, 1);
keyiter(k[-6], r2, r1, r4, 52, 2);
keyiter(k[-5], r3, r2, r0, 53, 3);
keyiter(k[-4], r4, r3, r1, 54, 4);
keyiter(k[-3], r0, r4, r2, 55, 5);
keyiter(k[-2], r1, r0, r3, 56, 6);
keyiter(k[-1], r2, r1, r4, 57, 7);
keyiter(k[0], r3, r2, r0, 58, 8);
keyiter(k[1], r4, r3, r1, 59, 9);
keyiter(k[2], r0, r4, r2, 60, 10);
keyiter(k[3], r1, r0, r3, 61, 11);
keyiter(k[4], r2, r1, r4, 62, 12);
keyiter(k[5], r3, r2, r0, 63, 13);
keyiter(k[6], r4, r3, r1, 64, 14);
keyiter(k[7], r0, r4, r2, 65, 15);
keyiter(k[8], r1, r0, r3, 66, 16);
keyiter(k[9], r2, r1, r4, 67, 17);
keyiter(k[10], r3, r2, r0, 68, 18);
keyiter(k[11], r4, r3, r1, 69, 19);
keyiter(k[12], r0, r4, r2, 70, 20);
keyiter(k[13], r1, r0, r3, 71, 21);
keyiter(k[14], r2, r1, r4, 72, 22);
keyiter(k[15], r3, r2, r0, 73, 23);
keyiter(k[16], r4, r3, r1, 74, 24);
keyiter(k[17], r0, r4, r2, 75, 25);
keyiter(k[18], r1, r0, r3, 76, 26);
keyiter(k[19], r2, r1, r4, 77, 27);
keyiter(k[20], r3, r2, r0, 78, 28);
keyiter(k[21], r4, r3, r1, 79, 29);
keyiter(k[22], r0, r4, r2, 80, 30);
keyiter(k[23], r1, r0, r3, 81, 31);
k += 50;
keyiter(k[-26], r2, r1, r4, 82, -18);
keyiter(k[-25], r3, r2, r0, 83, -17);
keyiter(k[-24], r4, r3, r1, 84, -16);
keyiter(k[-23], r0, r4, r2, 85, -15);
keyiter(k[-22], r1, r0, r3, 86, -14);
keyiter(k[-21], r2, r1, r4, 87, -13);
keyiter(k[-20], r3, r2, r0, 88, -12);
keyiter(k[-19], r4, r3, r1, 89, -11);
keyiter(k[-18], r0, r4, r2, 90, -10);
keyiter(k[-17], r1, r0, r3, 91, -9);
keyiter(k[-16], r2, r1, r4, 92, -8);
keyiter(k[-15], r3, r2, r0, 93, -7);
keyiter(k[-14], r4, r3, r1, 94, -6);
keyiter(k[-13], r0, r4, r2, 95, -5);
keyiter(k[-12], r1, r0, r3, 96, -4);
keyiter(k[-11], r2, r1, r4, 97, -3);
keyiter(k[-10], r3, r2, r0, 98, -2);
keyiter(k[-9], r4, r3, r1, 99, -1);
keyiter(k[-8], r0, r4, r2, 100, 0);
keyiter(k[-7], r1, r0, r3, 101, 1);
keyiter(k[-6], r2, r1, r4, 102, 2);
keyiter(k[-5], r3, r2, r0, 103, 3);
keyiter(k[-4], r4, r3, r1, 104, 4);
keyiter(k[-3], r0, r4, r2, 105, 5);
keyiter(k[-2], r1, r0, r3, 106, 6);
keyiter(k[-1], r2, r1, r4, 107, 7);
keyiter(k[0], r3, r2, r0, 108, 8);
keyiter(k[1], r4, r3, r1, 109, 9);
keyiter(k[2], r0, r4, r2, 110, 10);
keyiter(k[3], r1, r0, r3, 111, 11);
keyiter(k[4], r2, r1, r4, 112, 12);
keyiter(k[5], r3, r2, r0, 113, 13);
keyiter(k[6], r4, r3, r1, 114, 14);
keyiter(k[7], r0, r4, r2, 115, 15);
keyiter(k[8], r1, r0, r3, 116, 16);
keyiter(k[9], r2, r1, r4, 117, 17);
keyiter(k[10], r3, r2, r0, 118, 18);
keyiter(k[11], r4, r3, r1, 119, 19);
keyiter(k[12], r0, r4, r2, 120, 20);
keyiter(k[13], r1, r0, r3, 121, 21);
keyiter(k[14], r2, r1, r4, 122, 22);
keyiter(k[15], r3, r2, r0, 123, 23);
keyiter(k[16], r4, r3, r1, 124, 24);
keyiter(k[17], r0, r4, r2, 125, 25);
keyiter(k[18], r1, r0, r3, 126, 26);
keyiter(k[19], r2, r1, r4, 127, 27);
keyiter(k[20], r3, r2, r0, 128, 28);
keyiter(k[21], r4, r3, r1, 129, 29);
keyiter(k[22], r0, r4, r2, 130, 30);
keyiter(k[23], r1, r0, r3, 131, 31);
/* Apply S-boxes */
S3(r3, r4, r0, r1, r2); store_and_load_keys(r1, r2, r4, r3, 28, 24);
S4(r1, r2, r4, r3, r0); store_and_load_keys(r2, r4, r3, r0, 24, 20);
S5(r2, r4, r3, r0, r1); store_and_load_keys(r1, r2, r4, r0, 20, 16);
S6(r1, r2, r4, r0, r3); store_and_load_keys(r4, r3, r2, r0, 16, 12);
S7(r4, r3, r2, r0, r1); store_and_load_keys(r1, r2, r0, r4, 12, 8);
S0(r1, r2, r0, r4, r3); store_and_load_keys(r0, r2, r4, r1, 8, 4);
S1(r0, r2, r4, r1, r3); store_and_load_keys(r3, r4, r1, r0, 4, 0);
S2(r3, r4, r1, r0, r2); store_and_load_keys(r2, r4, r3, r0, 0, -4);
S3(r2, r4, r3, r0, r1); store_and_load_keys(r0, r1, r4, r2, -4, -8);
S4(r0, r1, r4, r2, r3); store_and_load_keys(r1, r4, r2, r3, -8, -12);
S5(r1, r4, r2, r3, r0); store_and_load_keys(r0, r1, r4, r3, -12, -16);
S6(r0, r1, r4, r3, r2); store_and_load_keys(r4, r2, r1, r3, -16, -20);
S7(r4, r2, r1, r3, r0); store_and_load_keys(r0, r1, r3, r4, -20, -24);
S0(r0, r1, r3, r4, r2); store_and_load_keys(r3, r1, r4, r0, -24, -28);
k -= 50;
S1(r3, r1, r4, r0, r2); store_and_load_keys(r2, r4, r0, r3, 22, 18);
S2(r2, r4, r0, r3, r1); store_and_load_keys(r1, r4, r2, r3, 18, 14);
S3(r1, r4, r2, r3, r0); store_and_load_keys(r3, r0, r4, r1, 14, 10);
S4(r3, r0, r4, r1, r2); store_and_load_keys(r0, r4, r1, r2, 10, 6);
S5(r0, r4, r1, r2, r3); store_and_load_keys(r3, r0, r4, r2, 6, 2);
S6(r3, r0, r4, r2, r1); store_and_load_keys(r4, r1, r0, r2, 2, -2);
S7(r4, r1, r0, r2, r3); store_and_load_keys(r3, r0, r2, r4, -2, -6);
S0(r3, r0, r2, r4, r1); store_and_load_keys(r2, r0, r4, r3, -6, -10);
S1(r2, r0, r4, r3, r1); store_and_load_keys(r1, r4, r3, r2, -10, -14);
S2(r1, r4, r3, r2, r0); store_and_load_keys(r0, r4, r1, r2, -14, -18);
S3(r0, r4, r1, r2, r3); store_and_load_keys(r2, r3, r4, r0, -18, -22);
k -= 50;
S4(r2, r3, r4, r0, r1); store_and_load_keys(r3, r4, r0, r1, 28, 24);
S5(r3, r4, r0, r1, r2); store_and_load_keys(r2, r3, r4, r1, 24, 20);
S6(r2, r3, r4, r1, r0); store_and_load_keys(r4, r0, r3, r1, 20, 16);
S7(r4, r0, r3, r1, r2); store_and_load_keys(r2, r3, r1, r4, 16, 12);
S0(r2, r3, r1, r4, r0); store_and_load_keys(r1, r3, r4, r2, 12, 8);
S1(r1, r3, r4, r2, r0); store_and_load_keys(r0, r4, r2, r1, 8, 4);
S2(r0, r4, r2, r1, r3); store_and_load_keys(r3, r4, r0, r1, 4, 0);
S3(r3, r4, r0, r1, r2); storekeys(r1, r2, r4, r3, 0);
return 0;
}
EXPORT_SYMBOL_GPL(__serpent_setkey);
int serpent_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)
{
return __serpent_setkey(crypto_tfm_ctx(tfm), key, keylen);
}
EXPORT_SYMBOL_GPL(serpent_setkey);
void __serpent_encrypt(struct serpent_ctx *ctx, u8 *dst, const u8 *src)
{
const u32 *k = ctx->expkey;
const __le32 *s = (const __le32 *)src;
__le32 *d = (__le32 *)dst;
u32 r0, r1, r2, r3, r4;
/*
* Note: The conversions between u8* and u32* might cause trouble
* on architectures with stricter alignment rules than x86
*/
r0 = le32_to_cpu(s[0]);
r1 = le32_to_cpu(s[1]);
r2 = le32_to_cpu(s[2]);
r3 = le32_to_cpu(s[3]);
K(r0, r1, r2, r3, 0);
S0(r0, r1, r2, r3, r4); LK(r2, r1, r3, r0, r4, 1);
S1(r2, r1, r3, r0, r4); LK(r4, r3, r0, r2, r1, 2);
S2(r4, r3, r0, r2, r1); LK(r1, r3, r4, r2, r0, 3);
S3(r1, r3, r4, r2, r0); LK(r2, r0, r3, r1, r4, 4);
S4(r2, r0, r3, r1, r4); LK(r0, r3, r1, r4, r2, 5);
S5(r0, r3, r1, r4, r2); LK(r2, r0, r3, r4, r1, 6);
S6(r2, r0, r3, r4, r1); LK(r3, r1, r0, r4, r2, 7);
S7(r3, r1, r0, r4, r2); LK(r2, r0, r4, r3, r1, 8);
S0(r2, r0, r4, r3, r1); LK(r4, r0, r3, r2, r1, 9);
S1(r4, r0, r3, r2, r1); LK(r1, r3, r2, r4, r0, 10);
S2(r1, r3, r2, r4, r0); LK(r0, r3, r1, r4, r2, 11);
S3(r0, r3, r1, r4, r2); LK(r4, r2, r3, r0, r1, 12);
S4(r4, r2, r3, r0, r1); LK(r2, r3, r0, r1, r4, 13);
S5(r2, r3, r0, r1, r4); LK(r4, r2, r3, r1, r0, 14);
S6(r4, r2, r3, r1, r0); LK(r3, r0, r2, r1, r4, 15);
S7(r3, r0, r2, r1, r4); LK(r4, r2, r1, r3, r0, 16);
S0(r4, r2, r1, r3, r0); LK(r1, r2, r3, r4, r0, 17);
S1(r1, r2, r3, r4, r0); LK(r0, r3, r4, r1, r2, 18);
S2(r0, r3, r4, r1, r2); LK(r2, r3, r0, r1, r4, 19);
S3(r2, r3, r0, r1, r4); LK(r1, r4, r3, r2, r0, 20);
S4(r1, r4, r3, r2, r0); LK(r4, r3, r2, r0, r1, 21);
S5(r4, r3, r2, r0, r1); LK(r1, r4, r3, r0, r2, 22);
S6(r1, r4, r3, r0, r2); LK(r3, r2, r4, r0, r1, 23);
S7(r3, r2, r4, r0, r1); LK(r1, r4, r0, r3, r2, 24);
S0(r1, r4, r0, r3, r2); LK(r0, r4, r3, r1, r2, 25);
S1(r0, r4, r3, r1, r2); LK(r2, r3, r1, r0, r4, 26);
S2(r2, r3, r1, r0, r4); LK(r4, r3, r2, r0, r1, 27);
S3(r4, r3, r2, r0, r1); LK(r0, r1, r3, r4, r2, 28);
S4(r0, r1, r3, r4, r2); LK(r1, r3, r4, r2, r0, 29);
S5(r1, r3, r4, r2, r0); LK(r0, r1, r3, r2, r4, 30);
S6(r0, r1, r3, r2, r4); LK(r3, r4, r1, r2, r0, 31);
S7(r3, r4, r1, r2, r0); K(r0, r1, r2, r3, 32);
d[0] = cpu_to_le32(r0);
d[1] = cpu_to_le32(r1);
d[2] = cpu_to_le32(r2);
d[3] = cpu_to_le32(r3);
}
EXPORT_SYMBOL_GPL(__serpent_encrypt);
static void serpent_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
{
struct serpent_ctx *ctx = crypto_tfm_ctx(tfm);
__serpent_encrypt(ctx, dst, src);
}
void __serpent_decrypt(struct serpent_ctx *ctx, u8 *dst, const u8 *src)
{
const u32 *k = ctx->expkey;
const __le32 *s = (const __le32 *)src;
__le32 *d = (__le32 *)dst;
u32 r0, r1, r2, r3, r4;
r0 = le32_to_cpu(s[0]);
r1 = le32_to_cpu(s[1]);
r2 = le32_to_cpu(s[2]);
r3 = le32_to_cpu(s[3]);
K(r0, r1, r2, r3, 32);
SI7(r0, r1, r2, r3, r4); KL(r1, r3, r0, r4, r2, 31);
SI6(r1, r3, r0, r4, r2); KL(r0, r2, r4, r1, r3, 30);
SI5(r0, r2, r4, r1, r3); KL(r2, r3, r0, r4, r1, 29);
SI4(r2, r3, r0, r4, r1); KL(r2, r0, r1, r4, r3, 28);
SI3(r2, r0, r1, r4, r3); KL(r1, r2, r3, r4, r0, 27);
SI2(r1, r2, r3, r4, r0); KL(r2, r0, r4, r3, r1, 26);
SI1(r2, r0, r4, r3, r1); KL(r1, r0, r4, r3, r2, 25);
SI0(r1, r0, r4, r3, r2); KL(r4, r2, r0, r1, r3, 24);
SI7(r4, r2, r0, r1, r3); KL(r2, r1, r4, r3, r0, 23);
SI6(r2, r1, r4, r3, r0); KL(r4, r0, r3, r2, r1, 22);
SI5(r4, r0, r3, r2, r1); KL(r0, r1, r4, r3, r2, 21);
SI4(r0, r1, r4, r3, r2); KL(r0, r4, r2, r3, r1, 20);
SI3(r0, r4, r2, r3, r1); KL(r2, r0, r1, r3, r4, 19);
SI2(r2, r0, r1, r3, r4); KL(r0, r4, r3, r1, r2, 18);
SI1(r0, r4, r3, r1, r2); KL(r2, r4, r3, r1, r0, 17);
SI0(r2, r4, r3, r1, r0); KL(r3, r0, r4, r2, r1, 16);
SI7(r3, r0, r4, r2, r1); KL(r0, r2, r3, r1, r4, 15);
SI6(r0, r2, r3, r1, r4); KL(r3, r4, r1, r0, r2, 14);
SI5(r3, r4, r1, r0, r2); KL(r4, r2, r3, r1, r0, 13);
SI4(r4, r2, r3, r1, r0); KL(r4, r3, r0, r1, r2, 12);
SI3(r4, r3, r0, r1, r2); KL(r0, r4, r2, r1, r3, 11);
SI2(r0, r4, r2, r1, r3); KL(r4, r3, r1, r2, r0, 10);
SI1(r4, r3, r1, r2, r0); KL(r0, r3, r1, r2, r4, 9);
SI0(r0, r3, r1, r2, r4); KL(r1, r4, r3, r0, r2, 8);
SI7(r1, r4, r3, r0, r2); KL(r4, r0, r1, r2, r3, 7);
SI6(r4, r0, r1, r2, r3); KL(r1, r3, r2, r4, r0, 6);
SI5(r1, r3, r2, r4, r0); KL(r3, r0, r1, r2, r4, 5);
SI4(r3, r0, r1, r2, r4); KL(r3, r1, r4, r2, r0, 4);
SI3(r3, r1, r4, r2, r0); KL(r4, r3, r0, r2, r1, 3);
SI2(r4, r3, r0, r2, r1); KL(r3, r1, r2, r0, r4, 2);
SI1(r3, r1, r2, r0, r4); KL(r4, r1, r2, r0, r3, 1);
SI0(r4, r1, r2, r0, r3); K(r2, r3, r1, r4, 0);
d[0] = cpu_to_le32(r2);
d[1] = cpu_to_le32(r3);
d[2] = cpu_to_le32(r1);
d[3] = cpu_to_le32(r4);
}
EXPORT_SYMBOL_GPL(__serpent_decrypt);
static void serpent_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
{
struct serpent_ctx *ctx = crypto_tfm_ctx(tfm);
__serpent_decrypt(ctx, dst, src);
}
static int tnepres_setkey(struct crypto_tfm *tfm, const u8 *key,
unsigned int keylen)
{
u8 rev_key[SERPENT_MAX_KEY_SIZE];
int i;
for (i = 0; i < keylen; ++i)
rev_key[keylen - i - 1] = key[i];
return serpent_setkey(tfm, rev_key, keylen);
}
static void tnepres_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
{
const u32 * const s = (const u32 * const)src;
u32 * const d = (u32 * const)dst;
u32 rs[4], rd[4];
rs[0] = swab32(s[3]);
rs[1] = swab32(s[2]);
rs[2] = swab32(s[1]);
rs[3] = swab32(s[0]);
serpent_encrypt(tfm, (u8 *)rd, (u8 *)rs);
d[0] = swab32(rd[3]);
d[1] = swab32(rd[2]);
d[2] = swab32(rd[1]);
d[3] = swab32(rd[0]);
}
static void tnepres_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
{
const u32 * const s = (const u32 * const)src;
u32 * const d = (u32 * const)dst;
u32 rs[4], rd[4];
rs[0] = swab32(s[3]);
rs[1] = swab32(s[2]);
rs[2] = swab32(s[1]);
rs[3] = swab32(s[0]);
serpent_decrypt(tfm, (u8 *)rd, (u8 *)rs);
d[0] = swab32(rd[3]);
d[1] = swab32(rd[2]);
d[2] = swab32(rd[1]);
d[3] = swab32(rd[0]);
}
static struct crypto_alg srp_algs[2] = { {
.cra_name = "serpent",
.cra_driver_name = "serpent-generic",
.cra_priority = 100,
.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
.cra_blocksize = SERPENT_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct serpent_ctx),
.cra_alignmask = 3,
.cra_module = THIS_MODULE,
.cra_u = { .cipher = {
.cia_min_keysize = SERPENT_MIN_KEY_SIZE,
.cia_max_keysize = SERPENT_MAX_KEY_SIZE,
.cia_setkey = serpent_setkey,
.cia_encrypt = serpent_encrypt,
.cia_decrypt = serpent_decrypt } }
}, {
.cra_name = "tnepres",
.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
.cra_blocksize = SERPENT_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct serpent_ctx),
.cra_alignmask = 3,
.cra_module = THIS_MODULE,
.cra_u = { .cipher = {
.cia_min_keysize = SERPENT_MIN_KEY_SIZE,
.cia_max_keysize = SERPENT_MAX_KEY_SIZE,
.cia_setkey = tnepres_setkey,
.cia_encrypt = tnepres_encrypt,
.cia_decrypt = tnepres_decrypt } }
} };
static int __init serpent_mod_init(void)
{
return crypto_register_algs(srp_algs, ARRAY_SIZE(srp_algs));
}
static void __exit serpent_mod_fini(void)
{
crypto_unregister_algs(srp_algs, ARRAY_SIZE(srp_algs));
}
module_init(serpent_mod_init);
module_exit(serpent_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Serpent and tnepres (kerneli compatible serpent reversed) Cipher Algorithm");
MODULE_AUTHOR("Dag Arne Osvik <osvik@ii.uib.no>");
MODULE_ALIAS_CRYPTO("tnepres");
MODULE_ALIAS_CRYPTO("serpent");
MODULE_ALIAS_CRYPTO("serpent-generic");
|
{
"language": "Assembly"
}
|
; RUN: opt < %s -scalarrepl -instcombine -inline -instcombine -S | grep "ret i32 42"
; PR3489
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "x86_64-apple-darwin10.0"
%struct.anon = type <{ i32, i32, i32 }>
define i32 @f({ i64, i64 }) nounwind {
entry:
%tmp = alloca { i64, i64 }, align 8 ; <{ i64, i64 }*> [#uses=2]
store { i64, i64 } %0, { i64, i64 }* %tmp
%1 = bitcast { i64, i64 }* %tmp to %struct.anon* ; <%struct.anon*> [#uses=1]
%2 = load %struct.anon* %1, align 8 ; <%struct.anon> [#uses=1]
%tmp3 = extractvalue %struct.anon %2, 0
ret i32 %tmp3
}
define i32 @g() {
%a = call i32 @f({i64,i64} { i64 42, i64 1123123123123123 })
ret i32 %a
}
|
{
"language": "Assembly"
}
|
package java_cup;
import java.util.Hashtable;
import java.util.Enumeration;
/** This class represents a production in the grammar. It contains
* a LHS non terminal, and an array of RHS symbols. As various
* transformations are done on the RHS of the production, it may shrink.
* As a result a separate length is always maintained to indicate how much
* of the RHS array is still valid.<p>
*
* I addition to construction and manipulation operations, productions provide
* methods for factoring out actions (see remove_embedded_actions()), for
* computing the nullability of the production (i.e., can it derive the empty
* string, see check_nullable()), and operations for computing its first
* set (i.e., the set of terminals that could appear at the beginning of some
* string derived from the production, see check_first_set()).
*
* @see java_cup.production_part
* @see java_cup.symbol_part
* @see java_cup.action_part
* @version last updated: 11/25/95
* @author Scott Hudson
*/
public class production {
/*-----------------------------------------------------------*/
/*--- Constructor(s) ----------------------------------------*/
/*-----------------------------------------------------------*/
/** Full constructor. This constructor accepts a LHS non terminal,
* an array of RHS parts (including terminals, non terminals, and
* actions), and a string for a final reduce action. It does several
* manipulations in the process of creating a production object.
* After some validity checking it translates labels that appear in
* actions into code for accessing objects on the runtime parse stack.
* It them merges adjacent actions if they appear and moves any trailing
* action into the final reduce actions string. Next it removes any
* embedded actions by factoring them out with new action productions.
* Finally it assigns a unique index to the production.<p>
*
* Factoring out of actions is accomplished by creating new "hidden"
* non terminals. For example if the production was originally: <pre>
* A ::= B {action} C D
* </pre>
* then it is factored into two productions:<pre>
* A ::= B X C D
* X ::= {action}
* </pre>
* (where X is a unique new non terminal). This has the effect of placing
* all actions at the end where they can be handled as part of a reduce by
* the parser.
*/
public production(
non_terminal lhs_sym,
production_part rhs_parts[],
int rhs_l,
String action_str)
throws internal_error
{
int i;
action_part tail_action;
/* remember the length */
if (rhs_l >= 0)
_rhs_length = rhs_l;
else if (rhs_parts != null)
_rhs_length = rhs_parts.length;
else
_rhs_length = 0;
/* make sure we have a valid left-hand-side */
if (lhs_sym == null)
throw new internal_error(
"Attempt to construct a production with a null LHS");
/* translate labels appearing in action strings */
action_str = translate_labels(
rhs_parts, rhs_l, action_str, lhs_sym.stack_type());
/* count use of lhs */
lhs_sym.note_use();
/* create the part for left-hand-side */
_lhs = new symbol_part(lhs_sym);
/* merge adjacent actions (if any) */
_rhs_length = merge_adjacent_actions(rhs_parts, _rhs_length);
/* strip off any trailing action */
tail_action = strip_trailing_action(rhs_parts, _rhs_length);
if (tail_action != null) _rhs_length--;
/* allocate and copy over the right-hand-side */
_rhs = new production_part[_rhs_length];
for (i=0; i<_rhs_length; i++)
_rhs[i] = rhs_parts[i];
/* count use of each rhs symbol */
for (i=0; i<_rhs_length; i++)
if (!_rhs[i].is_action())
((symbol_part)_rhs[i]).the_symbol().note_use();
/* merge any trailing action with action string parameter */
if (action_str == null) action_str = "";
if (tail_action != null && tail_action.code_string() != null)
action_str = tail_action.code_string() + action_str;
/* stash the action */
_action = new action_part(action_str);
/* rewrite production to remove any embedded actions */
remove_embedded_actions();
/* assign an index */
_index = next_index++;
/* put us in the global collection of productions */
_all.put(new Integer(_index),this);
/* put us in the production list of the lhs non terminal */
lhs_sym.add_production(this);
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Constructor with no action string. */
public production(
non_terminal lhs_sym,
production_part rhs_parts[],
int rhs_l)
throws internal_error
{
this(lhs_sym,rhs_parts,rhs_l,null);
}
/*-----------------------------------------------------------*/
/*--- (Access to) Static (Class) Variables ------------------*/
/*-----------------------------------------------------------*/
/** Table of all productions. Elements are stored using their index as
* the key.
*/
protected static Hashtable _all = new Hashtable();
/** Access to all productions. */
public static Enumeration all() {return _all.elements();};
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Total number of productions. */
public static int number() {return _all.size();};
/** Static counter for assigning unique index numbers. */
protected static int next_index;
/*-----------------------------------------------------------*/
/*--- (Access to) Instance Variables ------------------------*/
/*-----------------------------------------------------------*/
/** The left hand side non-terminal. */
protected symbol_part _lhs;
/** The left hand side non-terminal. */
public symbol_part lhs() {return _lhs;}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** A collection of parts for the right hand side. */
protected production_part _rhs[];
/** Access to the collection of parts for the right hand side. */
public production_part rhs(int indx) throws internal_error
{
if (indx >= 0 && indx < _rhs_length)
return _rhs[indx];
else
throw new internal_error(
"Index out of range for right hand side of production");
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** How much of the right hand side array we are presently using. */
protected int _rhs_length;
/** How much of the right hand side array we are presently using. */
public int rhs_length() {return _rhs_length;}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** An action_part containing code for the action to be performed when we
* reduce with this production.
*/
protected action_part _action;
/** An action_part containing code for the action to be performed when we
* reduce with this production.
*/
public action_part action() {return _action;}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Index number of the production. */
protected int _index;
/** Index number of the production. */
public int index() {return _index;}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Count of number of reductions using this production. */
protected int _num_reductions = 0;
/** Count of number of reductions using this production. */
public int num_reductions() {return _num_reductions;}
/** Increment the count of reductions with this non-terminal */
public void note_reduction_use() {_num_reductions++;}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Is the nullability of the production known or unknown? */
protected boolean _nullable_known = false;
/** Is the nullability of the production known or unknown? */
public boolean nullable_known() {return _nullable_known;}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Nullability of the production (can it derive the empty string). */
protected boolean _nullable = false;
/** Nullability of the production (can it derive the empty string). */
public boolean nullable() {return _nullable;}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** First set of the production. This is the set of terminals that
* could appear at the front of some string derived from this production.
*/
protected terminal_set _first_set = new terminal_set();
/** First set of the production. This is the set of terminals that
* could appear at the front of some string derived from this production.
*/
public terminal_set first_set() {return _first_set;}
/*-----------------------------------------------------------*/
/*--- Static Methods ----------------------------------------*/
/*-----------------------------------------------------------*/
/** Determine if a given character can be a label id starter.
* @param c the character in question.
*/
protected static boolean is_id_start(char c)
{
return (c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || (c == '_');
//later need to handle non-8-bit chars here
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Determine if a character can be in a label id.
* @param c the character in question.
*/
protected static boolean is_id_char(char c)
{
return is_id_start(c) || (c >= '0' && c <= '9');
}
/*-----------------------------------------------------------*/
/*--- General Methods ---------------------------------------*/
/*-----------------------------------------------------------*/
/** Determine the translation for one label id found within a code_string.
* Symbols appearing in the RHS correspond to objects found on the parse
* stack at runtime. The code to access them, becomes code to access an
* object at the appropriate offset from the top of the stack, and then
* cast that to the proper type.
*
* @param id_str the name of the id to be translated.
* @param act_pos the original position of the action it appears in.
* @param label_map a hash table mapping labels to positions in the RHS.
* @param type_map a hash table mapping labels to declared symbol types.
*/
protected String label_translate(
String id_str, /* the id string we are (possibly) translating */
int act_pos, /* position of the action */
Hashtable label_map, /* map from labels to positions in the RHS */
Hashtable label_types)/* map from labels to stack types */
{
Integer label_pos;
String label_type;
int offset;
/* look up the id */
label_pos = (Integer)label_map.get(id_str);
/* if we don't find it, just return the id */
if (label_pos == null) return id_str;
/* extract the type of the labeled symbol */
label_type = (String)label_types.get(id_str);
/* is this for the LHS? */
if (label_pos.intValue() == -1)
{
/* return the result object cast properly */
return "((" + label_type + ")" + emit.pre("result") + ")";
}
/* its a RHS label */
/* if the label appears after the action, we have an error */
if (label_pos.intValue() > act_pos)
{
/* emit an error message */
System.err.println("*** Label \"" + id_str +
"\" appears in action before it appears in production");
lexer.error_count++;
// later need to print the production this is in
/* just return the id unchanged */
return id_str;
}
/* calculate the stack offset as the difference in position from
label to action minus one */
offset = (act_pos - label_pos.intValue())-1;
/* translation is properly cast element at that offset from TOS */
return "(/*"+id_str+"*/("+label_type+")" +
emit.pre("stack") + ".elementAt(" + emit.pre("top") +"-"+ offset + "))";
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Translate all the label names within an action string to appropriate code.
* @param act_string the string to be translated
* @param act_pos the position that the action originally held in the
* production.
* @param label_map a hash table mapping labels to positions in the RHS.
* @param type_map a hash table mapping labels to declared symbol types.
*/
protected String action_translate(
String act_string, /* the action string */
int act_pos, /* the position of the action on the RHS */
Hashtable label_map, /* map from labels to RHS positions */
Hashtable label_types) /* map from labels to symbol stack types */
{
int id_start;
int pos;
int len;
String id_str;
boolean in_id;
StringBuffer result;
char buffer[];
/* if we have no string we are done */
if (act_string == null || act_string.length()== 0) return act_string;
len = act_string.length();
/* set up a place to put the result */
result = new StringBuffer(len + 50);
/* extract string into array */
buffer = new char[len + 1];
act_string.getChars(0, len, buffer, 0);
/* put terminator in buffer so we can look one past the end */
buffer[len] = '\0';
/* walk down the input buffer looking for identifiers */
in_id = false;
for (pos = id_start = 0; pos <= len; pos++)
{
/* are we currently working on an id? */
if (in_id)
{
/* does this end the id? */
if (!is_id_char(buffer[pos]))
{
/* extract the id string and translate it */
id_str = new String(buffer, id_start, pos - id_start);
result.append(
label_translate(id_str, act_pos, label_map,label_types));
/* copy over the ending character */
if (buffer[pos] != '\0')
result.append(buffer, pos, 1);
/* and we are done with this id */
in_id = false;
}
else
{
/* we are still in the id, so just keep going */
}
}
else /* we are not inside an id */
{
/* start a new id? */
if (is_id_start(buffer[pos]))
{
/* start keeping these chars as an id */
in_id = true;
id_start = pos;
}
else
{
/* just copy over the char */
if (buffer[pos] != '\0')
result.append(buffer, pos, 1);
}
}
}
/* return the accumulated result */
return result.toString();
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Translate label names to appropriate code within all action strings.
* @param rhs array of RHS parts.
* @param rhs_len how much of rhs to consider valid.
* @param final_action the final action string of the production.
* @param lhs_type the object type associated with the LHS symbol.
*/
protected String translate_labels(
production_part rhs[],
int rhs_len,
String final_action,
String lhs_type)
{
Hashtable label_map = new Hashtable(11);
Hashtable label_types = new Hashtable(11);
symbol_part part;
action_part act_part;
int pos;
/* walk down the parts and extract the labels */
for (pos = 0; pos < rhs_len; pos++)
{
if (!rhs[pos].is_action())
{
part = (symbol_part)rhs[pos];
/* if it has a label enter it in the tables */
if (part.label() != null)
{
label_map.put(part.label(), new Integer(pos));
label_types.put(part.label(), part.the_symbol().stack_type());
}
}
}
/* add a label for the LHS */
label_map.put("RESULT", new Integer(-1));
label_types.put("RESULT", lhs_type);
/* now walk across and do each action string */
for (pos = 0; pos < rhs_len; pos++)
{
if (rhs[pos].is_action())
{
act_part = (action_part)rhs[pos];
act_part.set_code_string(
action_translate(
act_part.code_string(), pos, label_map, label_types));
}
}
/* now do the final action string at the position after the last */
return action_translate(final_action, rhs_len, label_map, label_types);
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Helper routine to merge adjacent actions in a set of RHS parts
* @param rhs_parts array of RHS parts.
* @param len amount of that array that is valid.
* @return remaining valid length.
*/
protected int merge_adjacent_actions(production_part rhs_parts[], int len)
{
int from_loc, to_loc, merge_cnt;
/* bail out early if we have no work to do */
if (rhs_parts == null || len == 0) return 0;
merge_cnt = 0;
to_loc = -1;
for (from_loc=0; from_loc<len; from_loc++)
{
/* do we go in the current position or one further */
if (to_loc < 0 || !rhs_parts[to_loc].is_action()
|| !rhs_parts[from_loc].is_action())
{
/* next one */
to_loc++;
/* clear the way for it */
if (to_loc != from_loc) rhs_parts[to_loc] = null;
}
/* if this is not trivial? */
if (to_loc != from_loc)
{
/* do we merge or copy? */
if (rhs_parts[to_loc] != null && rhs_parts[to_loc].is_action() &&
rhs_parts[from_loc].is_action())
{
/* merge */
rhs_parts[to_loc] = new action_part(
((action_part)rhs_parts[to_loc]).code_string() +
((action_part)rhs_parts[from_loc]).code_string());
merge_cnt++;
}
else
{
/* copy */
rhs_parts[to_loc] = rhs_parts[from_loc];
}
}
}
/* return the used length */
return len - merge_cnt;
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Helper routine to strip a trailing action off rhs and return it
* @param rhs_parts array of RHS parts.
* @param len how many of those are valid.
* @return the removed action part.
*/
protected action_part strip_trailing_action(
production_part rhs_parts[],
int len)
{
action_part result;
/* bail out early if we have nothing to do */
if (rhs_parts == null || len == 0) return null;
/* see if we have a trailing action */
if (rhs_parts[len-1].is_action())
{
/* snip it out and return it */
result = (action_part)rhs_parts[len-1];
rhs_parts[len-1] = null;
return result;
}
else
return null;
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Remove all embedded actions from a production by factoring them
* out into individual action production using new non terminals.
* if the original production was: <pre>
* A ::= B {action1} C {action2} D
* </pre>
* then it will be factored into: <pre>
* A ::= B NT$1 C NT$2 D
* NT$1 ::= {action1}
* NT$2 ::= {action2}
* </pre>
* where NT$1 and NT$2 are new system created non terminals.
*/
protected void remove_embedded_actions() throws internal_error
{
non_terminal new_nt;
production new_prod;
/* walk over the production and process each action */
for (int act_loc = 0; act_loc < rhs_length(); act_loc++)
if (rhs(act_loc).is_action())
{
/* create a new non terminal for the action production */
new_nt = non_terminal.create_new();
/* create a new production with just the action */
new_prod = new action_production(this, new_nt, null, 0,
((action_part)rhs(act_loc)).code_string());
/* replace the action with the generated non terminal */
_rhs[act_loc] = new symbol_part(new_nt);
}
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Check to see if the production (now) appears to be nullable.
* A production is nullable if its RHS could derive the empty string.
* This results when the RHS is empty or contains only non terminals
* which themselves are nullable.
*/
public boolean check_nullable() throws internal_error
{
production_part part;
symbol sym;
int pos;
/* if we already know bail out early */
if (nullable_known()) return nullable();
/* if we have a zero size RHS we are directly nullable */
if (rhs_length() == 0)
{
/* stash and return the result */
return set_nullable(true);
}
/* otherwise we need to test all of our parts */
for (pos=0; pos<rhs_length(); pos++)
{
part = rhs(pos);
/* only look at non-actions */
if (!part.is_action())
{
sym = ((symbol_part)part).the_symbol();
/* if its a terminal we are definitely not nullable */
if (!sym.is_non_term())
return set_nullable(false);
/* its a non-term, is it marked nullable */
else if (!((non_terminal)sym).nullable())
/* this one not (yet) nullable, so we aren't */
return false;
}
}
/* if we make it here all parts are nullable */
return set_nullable(true);
}
/** set (and return) nullability */
boolean set_nullable(boolean v)
{
_nullable_known = true;
_nullable = v;
return v;
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Update (and return) the first set based on current NT firsts.
* This assumes that nullability has already been computed for all non
* terminals and productions.
*/
public terminal_set check_first_set() throws internal_error
{
int part;
symbol sym;
/* walk down the right hand side till we get past all nullables */
for (part=0; part<rhs_length(); part++)
{
/* only look at non-actions */
if (!rhs(part).is_action())
{
sym = ((symbol_part)rhs(part)).the_symbol();
/* is it a non-terminal?*/
if (sym.is_non_term())
{
/* add in current firsts from that NT */
_first_set.add(((non_terminal)sym).first_set());
/* if its not nullable, we are done */
if (!((non_terminal)sym).nullable())
break;
}
else
{
/* its a terminal -- add that to the set */
_first_set.add((terminal)sym);
/* we are done */
break;
}
}
}
/* return our updated first set */
return first_set();
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Equality comparison. */
public boolean equals(production other)
{
if (other == null) return false;
return other._index == _index;
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Generic equality comparison. */
public boolean equals(Object other)
{
if (!(other instanceof production))
return false;
else
return equals((production)other);
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Produce a hash code. */
public int hashCode()
{
/* just use a simple function of the index */
return _index*13;
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Convert to a string. */
public String toString()
{
String result;
/* catch any internal errors */
try {
result = "production [" + index() + "]: ";
result += ((lhs() != null) ? lhs().toString() : "$$NULL-LHS$$");
result += " :: = ";
for (int i = 0; i<rhs_length(); i++)
result += rhs(i) + " ";
result += ";";
if (action() != null && action().code_string() != null)
result += " {" + action().code_string() + "}";
if (nullable_known())
if (nullable())
result += "[NULLABLE]";
else
result += "[NOT NULLABLE]";
} catch (internal_error e) {
/* crash on internal error since we can't throw it from here (because
superclass does not throw anything. */
e.crash();
result = null;
}
return result;
}
/*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*/
/** Convert to a simpler string. */
public String to_simple_string() throws internal_error
{
String result;
result = ((lhs() != null) ? lhs().the_symbol().name() : "NULL_LHS");
result += " ::= ";
for (int i = 0; i < rhs_length(); i++)
if (!rhs(i).is_action())
result += ((symbol_part)rhs(i)).the_symbol().name() + " ";
return result;
}
/*-----------------------------------------------------------*/
};
|
{
"language": "Assembly"
}
|
dnl AMD64 mpn_addmul_2 optimised for Intel Haswell.
dnl Contributed to the GNU project by Torbjörn Granlund.
dnl Copyright 2013 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C cycles/limb
C AMD K8,K9 n/a
C AMD K10 n/a
C AMD bull n/a
C AMD pile n/a
C AMD steam ?
C AMD bobcat n/a
C AMD jaguar ?
C Intel P4 n/a
C Intel core n/a
C Intel NHM n/a
C Intel SBR n/a
C Intel IBR n/a
C Intel HWL 2.15
C Intel BWL ?
C Intel atom n/a
C VIA nano n/a
C The loop of this code is the result of running a code generation and
C optimisation tool suite written by David Harvey and Torbjörn Granlund.
define(`rp', `%rdi')
define(`up', `%rsi')
define(`n_param',`%rdx')
define(`vp', `%rcx')
define(`v0', `%r8')
define(`v1', `%r9')
define(`w0', `%rbx')
define(`w1', `%rcx')
define(`w2', `%rbp')
define(`w3', `%r10')
define(`n', `%r11')
define(`X0', `%r12')
define(`X1', `%r13')
ABI_SUPPORT(DOS64)
ABI_SUPPORT(STD64)
ASM_START()
TEXT
ALIGN(32)
PROLOGUE(mpn_addmul_2)
FUNC_ENTRY(4)
push %rbx
push %rbp
push %r12
push %r13
mov (vp), v0
mov 8(vp), v1
mov n_param, n
shr $2, n
test $1, R8(n_param)
jnz L(bx1)
L(bx0): mov (rp), X0
mov 8(rp), X1
test $2, R8(n_param)
jnz L(b10)
L(b00): mov (up), %rdx
lea 16(up), up
mulx( v0, %rax, w1)
add %rax, X0
mulx( v1, %rax, w2)
adc $0, w1
mov X0, (rp)
add %rax, X1
adc $0, w2
mov -8(up), %rdx
lea 16(rp), rp
jmp L(lo0)
L(b10): mov (up), %rdx
inc n
mulx( v0, %rax, w1)
add %rax, X0
adc $0, w1
mulx( v1, %rax, w2)
mov X0, (rp)
mov 16(rp), X0
add %rax, X1
adc $0, w2
xor w0, w0
jmp L(lo2)
L(bx1): mov (rp), X1
mov 8(rp), X0
test $2, R8(n_param)
jnz L(b11)
L(b01): mov (up), %rdx
mulx( v0, %rax, w3)
add %rax, X1
adc $0, w3
mulx( v1, %rax, w0)
add %rax, X0
adc $0, w0
mov 8(up), %rdx
mov X1, (rp)
mov 16(rp), X1
mulx( v0, %rax, w1)
lea 24(rp), rp
lea 24(up), up
jmp L(lo1)
L(b11): mov (up), %rdx
inc n
mulx( v0, %rax, w3)
add %rax, X1
adc $0, w3
mulx( v1, %rax, w0)
add %rax, X0
adc $0, w0
mov X1, (rp)
mov 8(up), %rdx
mulx( v0, %rax, w1)
lea 8(rp), rp
lea 8(up), up
jmp L(lo3)
ALIGN(16)
L(top): mulx( v0, %rax, w3)
add w0, X1
adc $0, w2
add %rax, X1
adc $0, w3
mulx( v1, %rax, w0)
add %rax, X0
adc $0, w0
lea 32(rp), rp
add w1, X1
mov -16(up), %rdx
mov X1, -24(rp)
adc $0, w3
add w2, X0
mov -8(rp), X1
mulx( v0, %rax, w1)
adc $0, w0
L(lo1): add %rax, X0
mulx( v1, %rax, w2)
adc $0, w1
add w3, X0
mov X0, -16(rp)
adc $0, w1
add %rax, X1
adc $0, w2
add w0, X1
mov -8(up), %rdx
adc $0, w2
L(lo0): mulx( v0, %rax, w3)
add %rax, X1
adc $0, w3
mov (rp), X0
mulx( v1, %rax, w0)
add %rax, X0
adc $0, w0
add w1, X1
mov X1, -8(rp)
adc $0, w3
mov (up), %rdx
add w2, X0
mulx( v0, %rax, w1)
adc $0, w0
L(lo3): add %rax, X0
adc $0, w1
mulx( v1, %rax, w2)
add w3, X0
mov 8(rp), X1
mov X0, (rp)
mov 16(rp), X0
adc $0, w1
add %rax, X1
adc $0, w2
L(lo2): mov 8(up), %rdx
lea 32(up), up
dec n
jnz L(top)
L(end): mulx( v0, %rax, w3)
add w0, X1
adc $0, w2
add %rax, X1
adc $0, w3
mulx( v1, %rdx, %rax)
add w1, X1
mov X1, 8(rp)
adc $0, w3
add w2, %rdx
adc $0, %rax
add w3, %rdx
mov %rdx, 16(rp)
adc $0, %rax
pop %r13
pop %r12
pop %rbp
pop %rbx
FUNC_EXIT()
ret
EPILOGUE()
|
{
"language": "Assembly"
}
|
flf2a$ 4 4 7 -1 32 0 0 0
Author : Lukasz Tyrala (lt.)
Date : 2004/4/12 12:28:23
Version: 1.2 (full)
URL : http://home.autocom.pl/bjt/lt
e-mail : luty@autocom.pl
--------------------------------------------
..xx.. (C) COPYRIGHTS MMIV by
.xXXXXXXx Lukasz Tyrala (lt.)
/ xXXXXx
.` xDXXx Permission is hereby given to
C Xx modify this font, as long as
\ x the modifier's name is placed
`---/| on a comment line.
lt. | | For comercial use of this font
please contact with me (lt.).
--------------------------------------------
This font has been created using JavE's
FIGlet font export assistant.
---- Have a look at: http://www.jave.de ----
Visit polish a-a usenet at------------------
-----------------------news:pl.rec.ascii-art
$ #
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_||| #
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'||=,#
=||' ##
__ #
\ \[\#
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|
{
"language": "Assembly"
}
|
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for AMD64, OpenBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
|
{
"language": "Assembly"
}
|
/**
******************************************************************************
* @file stm32f7xx_hal_rtc.c
* @author MCD Application Team
* @version V1.2.2
* @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
* + Initialization and de-initialization functions
* + RTC Time and Date functions
* + RTC Alarm functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### Backup Domain Operating Condition #####
==============================================================================
[..] The real-time clock (RTC), the RTC backup registers, and the backup
SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
VDD supply is powered off.
To retain the content of the RTC backup registers, backup SRAM, and supply
the RTC when VDD is turned off, VBAT pin can be connected to an optional
standby voltage supplied by a battery or by another source.
[..] To allow the RTC operating even when the main digital supply (VDD) is turned
off, the VBAT pin powers the following blocks:
(#) The RTC
(#) The LSE oscillator
(#) The backup SRAM when the low power backup regulator is enabled
(#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
[..] When the backup domain is supplied by VDD (analog switch connected to VDD),
the following pins are available:
(#) PC14 and PC15 can be used as either GPIO or LSE pins
(#) PC13 can be used as a GPIO or as the RTC_AF1 pin
(#) PI8 can be used as a GPIO or as the RTC_AF2 pin
[..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
because VDD is not present), the following pins are available:
(#) PC14 and PC15 can be used as LSE pins only
(#) PC13 can be used as the RTC_AF1 pin
(#) PI8 can be used as the RTC_AF2 pin
(#) PC1 can be used as the RTC_AF3 pin
##### Backup Domain Reset #####
==================================================================
[..] The backup domain reset sets all RTC registers and the RCC_BDCR register
to their reset values. The BKPSRAM is not affected by this reset. The only
way to reset the BKPSRAM is through the Flash interface by requesting
a protection level change from 1 to 0.
[..] A backup domain reset is generated when one of the following events occurs:
(#) Software reset, triggered by setting the BDRST bit in the
RCC Backup domain control register (RCC_BDCR).
(#) VDD or VBAT power on, if both supplies have previously been powered off.
##### Backup Domain Access #####
==================================================================
[..] After reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted write
accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
__HAL_RCC_PWR_CLK_ENABLE() function.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
(+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
(+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
##### How to use this driver #####
==================================================================
[..]
(+) Enable the RTC domain access (see description in the section above).
(+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
*** Time and Date configuration ***
===================================
[..]
(+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
and HAL_RTC_SetDate() functions.
(+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
*** Alarm configuration ***
===========================
[..]
(+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
(+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
##### RTC and low power modes #####
==================================================================
[..] The MCU can be woken up from a low power mode by an RTC alternate
function.
[..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and
Standby low power modes.
[..] The system can also wake up from low power modes without depending
on an external interrupt (Auto-wakeup mode), by using the RTC alarm
or the RTC wakeup events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup RTC RTC
* @brief RTC HAL module driver
* @{
*/
#ifdef HAL_RTC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to initialize and configure the
RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
RTC registers Write protection, enter and exit the RTC initialization mode,
RTC registers synchronization check and reference clock detection enable.
(#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
It is split into 2 programmable prescalers to minimize power consumption.
(++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
(++) When both prescalers are used, it is recommended to configure the
asynchronous prescaler to a high value to minimize power consumption.
(#) All RTC registers are Write protected. Writing to the RTC registers
is enabled by writing a key into the Write Protection register, RTC_WPR.
(#) To configure the RTC Calendar, user application should enter
initialization mode. In this mode, the calendar counter is stopped
and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
(#) To read the calendar through the shadow registers after Calendar
initialization, calendar update or after wakeup from low power modes
the software must first clear the RSF flag. The software must then
wait until it is set again before reading the calendar, which means
that the calendar registers have been correctly copied into the
RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
implements the above software sequence (RSF clear and RSF check).
@endverbatim
* @{
*/
/**
* @brief Initializes the RTC peripheral
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
/* Check the RTC peripheral state */
if(hrtc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
if(hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
else
{
/* Clear RTC_CR FMT, OSEL and POL Bits */
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
/* Set RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_READY;
return HAL_OK;
}
}
/**
* @brief DeInitializes the RTC peripheral
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
else
{
/* Reset TR, DR and CR registers */
hrtc->Instance->TR = (uint32_t)0x00000000;
hrtc->Instance->DR = (uint32_t)0x00002101;
/* Reset All CR bits except CR[2:0] */
hrtc->Instance->CR &= (uint32_t)0x00000007;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till WUTWF flag is set and if Time out is reached exit */
while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
/* Reset all RTC CR register bits */
hrtc->Instance->CR &= (uint32_t)0x00000000;
hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
hrtc->Instance->PRER = (uint32_t)0x007F00FF;
hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
hrtc->Instance->CALR = (uint32_t)0x00000000;
hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
/* Reset ISR register and exit initialization mode */
hrtc->Instance->ISR = (uint32_t)0x00000000;
/* Reset Tamper and alternate functions configuration register */
hrtc->Instance->TAMPCR = 0x00000000;
/* Reset Option register */
hrtc->Instance->OR = 0x00000000;
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_ERROR;
return HAL_ERROR;
}
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* De-Initialize RTC MSP */
HAL_RTC_MspDeInit(hrtc);
hrtc->State = HAL_RTC_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief Initializes the RTC MSP.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the RTC MSP.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup RTC_Group2 RTC Time and Date functions
* @brief RTC Time and Date functions
*
@verbatim
===============================================================================
##### RTC Time and Date functions #####
===============================================================================
[..] This section provides functions allowing to configure Time and Date features
@endverbatim
* @{
*/
/**
* @brief Sets RTC current time.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
assert_param(IS_RTC_HOUR12(sTime->Hours));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
}
else
{
sTime->TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(sTime->Hours));
}
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
(((uint32_t)sTime->TimeFormat) << 16));
}
else
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
tmpreg = RTC_Bcd2ToByte(sTime->Hours);
assert_param(IS_RTC_HOUR12(tmpreg));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
}
else
{
sTime->TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
((uint32_t)(sTime->Minutes) << 8) | \
((uint32_t)sTime->Seconds) | \
((uint32_t)(sTime->TimeFormat) << 16));
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
else
{
/* Set the RTC_TR register */
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
/* Clear the bits to be configured */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
/* Configure the RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
}
/**
* @brief Gets RTC current time.
* @param hrtc: RTC handle
* @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
* with input format (BIN or BCD), also SubSeconds field returning the
* RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
* factor to be used for second fraction ratio computation.
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
* value in second fraction ratio with time unit following generic formula:
* Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
* This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read
* to ensure consistency between the time and date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
/* Get subseconds values from the correspondent registers*/
sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
/* Get SecondFraction structure field from the corresponding register field*/
sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
/* Get the TR register */
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
{
/* Convert the time structure parameters to Binary format */
sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
}
return HAL_OK;
}
/**
* @brief Sets RTC current date.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
if(Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_YEAR(sDate->Year));
assert_param(IS_RTC_MONTH(sDate->Month));
assert_param(IS_RTC_DATE(sDate->Date));
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
((uint32_t)sDate->WeekDay << 13));
}
else
{
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
datetmpreg = RTC_Bcd2ToByte(sDate->Month);
assert_param(IS_RTC_MONTH(datetmpreg));
datetmpreg = RTC_Bcd2ToByte(sDate->Date);
assert_param(IS_RTC_DATE(datetmpreg));
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
(((uint32_t)sDate->Month) << 8) | \
((uint32_t)sDate->Date) | \
(((uint32_t)sDate->WeekDay) << 13));
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Set RTC state*/
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
else
{
/* Set the RTC_DR register */
hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_ERROR;
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY ;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
}
/**
* @brief Gets RTC current date.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
/* Get the DR register */
datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
{
/* Convert the date structure parameters to Binary format */
sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup RTC_Group3 RTC Alarm functions
* @brief RTC Alarm functions
*
@verbatim
===============================================================================
##### RTC Alarm functions #####
===============================================================================
[..] This section provides functions allowing to configure Alarm feature
@endverbatim
* @{
*/
/**
* @brief Sets the specified RTC Alarm.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t tickstart = 0;
uint32_t tmpreg = 0, subsecondtmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(sAlarm->Alarm));
assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
}
else
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
else
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
assert_param(IS_RTC_HOUR12(tmpreg));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
}
else
{
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
/* Configure the Alarm A or Alarm B Sub Second registers */
subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Alarm register */
if(sAlarm->Alarm == RTC_ALARM_A)
{
/* Disable the Alarm A interrupt */
__HAL_RTC_ALARMA_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_TIMEOUT;
}
}
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
/* Configure the Alarm A Sub Second register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMA_ENABLE(hrtc);
}
else
{
/* Disable the Alarm B interrupt */
__HAL_RTC_ALARMB_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_TIMEOUT;
}
}
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
/* Configure the Alarm B Sub Second register */
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMB_ENABLE(hrtc);
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief Sets the specified RTC Alarm with Interrupt
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @note The Alarm register can only be written when the corresponding Alarm
* is disabled (Use the HAL_RTC_DeactivateAlarm()).
* @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t tickstart = 0;
uint32_t tmpreg = 0, subsecondtmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(sAlarm->Alarm));
assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
}
else
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
else
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
assert_param(IS_RTC_HOUR12(tmpreg));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
}
else
{
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
/* Configure the Alarm A or Alarm B Sub Second registers */
subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Configure the Alarm register */
if(sAlarm->Alarm == RTC_ALARM_A)
{
/* Disable the Alarm A interrupt */
__HAL_RTC_ALARMA_DISABLE(hrtc);
/* Clear flag alarm A */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_TIMEOUT;
}
}
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
/* Configure the Alarm A Sub Second register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMA_ENABLE(hrtc);
/* Configure the Alarm interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
}
else
{
/* Disable the Alarm B interrupt */
__HAL_RTC_ALARMB_DISABLE(hrtc);
/* Clear flag alarm B */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_TIMEOUT;
}
}
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
/* Configure the Alarm B Sub Second register */
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMB_ENABLE(hrtc);
/* Configure the Alarm interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
}
/* RTC Alarm Interrupt Configuration: EXTI configuration */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief Deactive the specified RTC Alarm
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @arg RTC_ALARM_B: AlarmB
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
{
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RTC_ALARM(Alarm));
/* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
if(Alarm == RTC_ALARM_A)
{
/* AlarmA */
__HAL_RTC_ALARMA_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_TIMEOUT;
}
}
}
else
{
/* AlarmB */
__HAL_RTC_ALARMB_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_TIMEOUT;
}
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
/**
* @brief Gets the RTC Alarm value and masks.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param sAlarm: Pointer to Date structure
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @arg RTC_ALARM_B: AlarmB
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
{
uint32_t tmpreg = 0, subsecondtmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(Alarm));
if(Alarm == RTC_ALARM_A)
{
/* AlarmA */
sAlarm->Alarm = RTC_ALARM_A;
tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
}
else
{
sAlarm->Alarm = RTC_ALARM_B;
tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
}
/* Fill the structure with the read parameters */
sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
if(Format == RTC_FORMAT_BIN)
{
sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
}
return HAL_OK;
}
/**
* @brief This function handles Alarm interrupt request.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
{
if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
{
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
{
/* AlarmA callback */
HAL_RTC_AlarmAEventCallback(hrtc);
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
}
}
if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
{
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
{
/* AlarmB callback */
HAL_RTCEx_AlarmBEventCallback(hrtc);
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
}
}
/* Clear the EXTI's line Flag for RTC Alarm */
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
* @brief Alarm A callback.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_AlarmAEventCallback could be implemented in the user file
*/
}
/**
* @brief This function handles AlarmA Polling request.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
uint32_t tickstart = 0;
/* Get tick */
tickstart = HAL_GetTick();
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
return HAL_OK;
}
/**
* @}
*/
/** @defgroup RTC_Group4 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Wait for RTC Time and Date Synchronization
@endverbatim
* @{
*/
/**
* @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
* synchronized with RTC APB clock.
* @note The RTC Resynchronization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @note To read the calendar through the shadow registers after Calendar
* initialization, calendar update or after wakeup from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR and RTC_DR shadow registers.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
{
uint32_t tickstart = 0;
/* Clear RSF flag */
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait the registers to be synchronised */
while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup RTC_Group5 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Get RTC state
@endverbatim
* @{
*/
/**
* @brief Returns the RTC state.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
{
return hrtc->State;
}
/**
* @}
*/
/**
* @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
{
uint32_t tickstart = 0;
/* Check if the Initialization mode is set */
if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief Converts a 2 digit decimal to BCD format.
* @param Value: Byte to be converted
* @retval Converted byte
*/
uint8_t RTC_ByteToBcd2(uint8_t Value)
{
uint32_t bcdhigh = 0;
while(Value >= 10)
{
bcdhigh++;
Value -= 10;
}
return ((uint8_t)(bcdhigh << 4) | Value);
}
/**
* @brief Converts from 2 digit BCD to Binary.
* @param Value: BCD value to be converted
* @retval Converted word
*/
uint8_t RTC_Bcd2ToByte(uint8_t Value)
{
uint32_t tmp = 0;
tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
return (tmp + (Value & (uint8_t)0x0F));
}
/**
* @}
*/
#endif /* HAL_RTC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
{
"language": "Assembly"
}
|
; Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=33623
; RUN: llvm-diff %s %s
%A = type { i64, i64 }
@_gm_ = global <2 x %A*> zeroinitializer
define void @f() {
entry:
store <2 x %A*> zeroinitializer, <2 x %A*>* @_gm_
ret void
}
|
{
"language": "Assembly"
}
|
#source: start3.s
#source: bpo-6.s
#source: bpo-5.s
#as: -linker-allocated-gregs
#ld: -m elf64mmix --gc-sections
#objdump: -st
# Check that GC does not mess up things when no BPO:s are collected.
.*: file format elf64-mmix
SYMBOL TABLE:
0+ l d \.init 0+ (|\.init)
0+10 l d \.text 0+ (|\.text)
0+7e8 l d \.MMIX\.reg_contents 0+ (|\.MMIX\.reg_contents)
#...
0+ l \.init 0+ _start
#...
0+14 g \.text 0+ x
0+10 g \.text 0+ x2
#...
Contents of section \.init:
0000 00000000 0000003d 00000000 0000003a .*
Contents of section \.text:
0010 232dfe00 232dfd00 .*
Contents of section \.MMIX\.reg_contents:
07e8 00000000 0000107c 00000000 0000a420 .*
|
{
"language": "Assembly"
}
|
; Don't even think of reading this code
; It was automatically generated by cast-586.pl
; Which is a perl program used to generate the x86 assember for
; any of elf, a.out, BSDI, Win32, gaswin (for GNU as on Win32) or Solaris
; eric <eay@cryptsoft.com>
;
segment .text
extern _CAST_S_table0
extern _CAST_S_table1
extern _CAST_S_table2
extern _CAST_S_table3
global _CAST_encrypt
_CAST_encrypt:
;
push ebp
push ebx
mov ebx, [12+esp]
mov ebp, [16+esp]
push esi
push edi
; Load the 2 words
mov edi, [ebx]
mov esi, [4+ebx]
; Get short key flag
mov eax, [128+ebp]
push eax
xor eax, eax
; round 0
mov edx, [ebp]
mov ecx, [4+ebp]
add edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor edi, ecx
; round 1
mov edx, [8+ebp]
mov ecx, [12+ebp]
xor edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor esi, ecx
; round 2
mov edx, [16+ebp]
mov ecx, [20+ebp]
sub edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor edi, ecx
; round 3
mov edx, [24+ebp]
mov ecx, [28+ebp]
add edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor esi, ecx
; round 4
mov edx, [32+ebp]
mov ecx, [36+ebp]
xor edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor edi, ecx
; round 5
mov edx, [40+ebp]
mov ecx, [44+ebp]
sub edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor esi, ecx
; round 6
mov edx, [48+ebp]
mov ecx, [52+ebp]
add edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor edi, ecx
; round 7
mov edx, [56+ebp]
mov ecx, [60+ebp]
xor edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor esi, ecx
; round 8
mov edx, [64+ebp]
mov ecx, [68+ebp]
sub edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor edi, ecx
; round 9
mov edx, [72+ebp]
mov ecx, [76+ebp]
add edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor esi, ecx
; round 10
mov edx, [80+ebp]
mov ecx, [84+ebp]
xor edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor edi, ecx
; round 11
mov edx, [88+ebp]
mov ecx, [92+ebp]
sub edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor esi, ecx
; test short key flag
pop edx
or edx, edx
jnz NEAR $L000cast_enc_done
; round 12
mov edx, [96+ebp]
mov ecx, [100+ebp]
add edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor edi, ecx
; round 13
mov edx, [104+ebp]
mov ecx, [108+ebp]
xor edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor esi, ecx
; round 14
mov edx, [112+ebp]
mov ecx, [116+ebp]
sub edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor edi, ecx
; round 15
mov edx, [120+ebp]
mov ecx, [124+ebp]
add edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor esi, ecx
$L000cast_enc_done:
nop
mov eax, [20+esp]
mov [4+eax], edi
mov [eax], esi
pop edi
pop esi
pop ebx
pop ebp
ret
extern _CAST_S_table0
extern _CAST_S_table1
extern _CAST_S_table2
extern _CAST_S_table3
global _CAST_decrypt
_CAST_decrypt:
;
push ebp
push ebx
mov ebx, [12+esp]
mov ebp, [16+esp]
push esi
push edi
; Load the 2 words
mov edi, [ebx]
mov esi, [4+ebx]
; Get short key flag
mov eax, [128+ebp]
or eax, eax
jnz NEAR $L001cast_dec_skip
xor eax, eax
; round 15
mov edx, [120+ebp]
mov ecx, [124+ebp]
add edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor edi, ecx
; round 14
mov edx, [112+ebp]
mov ecx, [116+ebp]
sub edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor esi, ecx
; round 13
mov edx, [104+ebp]
mov ecx, [108+ebp]
xor edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor edi, ecx
; round 12
mov edx, [96+ebp]
mov ecx, [100+ebp]
add edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor esi, ecx
$L001cast_dec_skip:
; round 11
mov edx, [88+ebp]
mov ecx, [92+ebp]
sub edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor edi, ecx
; round 10
mov edx, [80+ebp]
mov ecx, [84+ebp]
xor edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor esi, ecx
; round 9
mov edx, [72+ebp]
mov ecx, [76+ebp]
add edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor edi, ecx
; round 8
mov edx, [64+ebp]
mov ecx, [68+ebp]
sub edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor esi, ecx
; round 7
mov edx, [56+ebp]
mov ecx, [60+ebp]
xor edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor edi, ecx
; round 6
mov edx, [48+ebp]
mov ecx, [52+ebp]
add edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor esi, ecx
; round 5
mov edx, [40+ebp]
mov ecx, [44+ebp]
sub edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor edi, ecx
; round 4
mov edx, [32+ebp]
mov ecx, [36+ebp]
xor edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor esi, ecx
; round 3
mov edx, [24+ebp]
mov ecx, [28+ebp]
add edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor edi, ecx
; round 2
mov edx, [16+ebp]
mov ecx, [20+ebp]
sub edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
add ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
xor ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
sub ecx, ebx
xor esi, ecx
; round 1
mov edx, [8+ebp]
mov ecx, [12+ebp]
xor edx, esi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
sub ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
add ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
xor ecx, ebx
xor edi, ecx
; round 0
mov edx, [ebp]
mov ecx, [4+ebp]
add edx, edi
rol edx, cl
mov ebx, edx
xor ecx, ecx
mov cl, dh
and ebx, 255
shr edx, 16
xor eax, eax
mov al, dh
and edx, 255
mov ecx, [_CAST_S_table0+ecx*4]
mov ebx, [_CAST_S_table1+ebx*4]
xor ecx, ebx
mov ebx, [_CAST_S_table2+eax*4]
sub ecx, ebx
mov ebx, [_CAST_S_table3+edx*4]
add ecx, ebx
xor esi, ecx
nop
mov eax, [20+esp]
mov [4+eax], edi
mov [eax], esi
pop edi
pop esi
pop ebx
pop ebp
ret
global _CAST_cbc_encrypt
_CAST_cbc_encrypt:
;
push ebp
push ebx
push esi
push edi
mov ebp, [28+esp]
; getting iv ptr from parameter 4
mov ebx, [36+esp]
mov esi, [ebx]
mov edi, [4+ebx]
push edi
push esi
push edi
push esi
mov ebx, esp
mov esi, [36+esp]
mov edi, [40+esp]
; getting encrypt flag from parameter 5
mov ecx, [56+esp]
; get and push parameter 3
mov eax, [48+esp]
push eax
push ebx
cmp ecx, 0
jz NEAR $L002decrypt
and ebp, 4294967288
mov eax, [8+esp]
mov ebx, [12+esp]
jz NEAR $L003encrypt_finish
L004encrypt_loop:
mov ecx, [esi]
mov edx, [4+esi]
xor eax, ecx
xor ebx, edx
bswap eax
bswap ebx
mov [8+esp], eax
mov [12+esp], ebx
call _CAST_encrypt
mov eax, [8+esp]
mov ebx, [12+esp]
bswap eax
bswap ebx
mov [edi], eax
mov [4+edi], ebx
add esi, 8
add edi, 8
sub ebp, 8
jnz NEAR L004encrypt_loop
$L003encrypt_finish:
mov ebp, [52+esp]
and ebp, 7
jz NEAR $L005finish
xor ecx, ecx
xor edx, edx
mov ebp, [$L006cbc_enc_jmp_table+ebp*4]
jmp ebp
L007ej7:
xor edx, edx
mov dh, [6+esi]
shl edx, 8
L008ej6:
mov dh, [5+esi]
L009ej5:
mov dl, [4+esi]
L010ej4:
mov ecx, [esi]
jmp $L011ejend
L012ej3:
mov ch, [2+esi]
xor ecx, ecx
shl ecx, 8
L013ej2:
mov ch, [1+esi]
L014ej1:
mov cl, [esi]
$L011ejend:
xor eax, ecx
xor ebx, edx
bswap eax
bswap ebx
mov [8+esp], eax
mov [12+esp], ebx
call _CAST_encrypt
mov eax, [8+esp]
mov ebx, [12+esp]
bswap eax
bswap ebx
mov [edi], eax
mov [4+edi], ebx
jmp $L005finish
$L002decrypt:
and ebp, 4294967288
mov eax, [16+esp]
mov ebx, [20+esp]
jz NEAR $L015decrypt_finish
L016decrypt_loop:
mov eax, [esi]
mov ebx, [4+esi]
bswap eax
bswap ebx
mov [8+esp], eax
mov [12+esp], ebx
call _CAST_decrypt
mov eax, [8+esp]
mov ebx, [12+esp]
bswap eax
bswap ebx
mov ecx, [16+esp]
mov edx, [20+esp]
xor ecx, eax
xor edx, ebx
mov eax, [esi]
mov ebx, [4+esi]
mov [edi], ecx
mov [4+edi], edx
mov [16+esp], eax
mov [20+esp], ebx
add esi, 8
add edi, 8
sub ebp, 8
jnz NEAR L016decrypt_loop
$L015decrypt_finish:
mov ebp, [52+esp]
and ebp, 7
jz NEAR $L005finish
mov eax, [esi]
mov ebx, [4+esi]
bswap eax
bswap ebx
mov [8+esp], eax
mov [12+esp], ebx
call _CAST_decrypt
mov eax, [8+esp]
mov ebx, [12+esp]
bswap eax
bswap ebx
mov ecx, [16+esp]
mov edx, [20+esp]
xor ecx, eax
xor edx, ebx
mov eax, [esi]
mov ebx, [4+esi]
L017dj7:
ror edx, 16
mov [6+edi], dl
shr edx, 16
L018dj6:
mov [5+edi], dh
L019dj5:
mov [4+edi], dl
L020dj4:
mov [edi], ecx
jmp $L021djend
L022dj3:
ror ecx, 16
mov [2+edi], cl
shl ecx, 16
L023dj2:
mov [1+esi], ch
L024dj1:
mov [esi], cl
$L021djend:
jmp $L005finish
$L005finish:
mov ecx, [60+esp]
add esp, 24
mov [ecx], eax
mov [4+ecx], ebx
pop edi
pop esi
pop ebx
pop ebp
ret
$L006cbc_enc_jmp_table:
DD 0
DD L014ej1
DD L013ej2
DD L012ej3
DD L010ej4
DD L009ej5
DD L008ej6
DD L007ej7
L025cbc_dec_jmp_table:
DD 0
DD L024dj1
DD L023dj2
DD L022dj3
DD L020dj4
DD L019dj5
DD L018dj6
DD L017dj7
|
{
"language": "Assembly"
}
|
; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s
; CHECK: align
; CHECK: movl $4, -4(%ecx)
; CHECK: movl $5, (%ecx)
; CHECK: addl $4, %ecx
; CHECK: decl %eax
; CHECK: jne
@A = global [16 x [16 x i32]] zeroinitializer, align 32 ; <[16 x [16 x i32]]*> [#uses=2]
define void @test(i32 %row, i32 %N.in) nounwind {
entry:
%N = bitcast i32 %N.in to i32 ; <i32> [#uses=1]
%tmp5 = icmp sgt i32 %N.in, 0 ; <i1> [#uses=1]
br i1 %tmp5, label %cond_true, label %return
cond_true: ; preds = %cond_true, %entry
%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
%i.0.0 = bitcast i32 %indvar to i32 ; <i32> [#uses=2]
%tmp2 = add i32 %i.0.0, 1 ; <i32> [#uses=1]
%tmp = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2 ; <i32*> [#uses=1]
store i32 4, i32* %tmp
%tmp5.upgrd.1 = add i32 %i.0.0, 2 ; <i32> [#uses=1]
%tmp7 = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1 ; <i32*> [#uses=1]
store i32 5, i32* %tmp7
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
%exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %cond_true
return: ; preds = %cond_true, %entry
ret void
}
|
{
"language": "Assembly"
}
|
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
foo:
sleep
; CHECK: sleep ; encoding: [0x88,0x95]
|
{
"language": "Assembly"
}
|
// Test -MT and -E flags, PR4063
// RUN: %clang -E -o %t.1 %s
// RUN: %clang -E -MD -MF %t.d -MT foo -o %t.2 %s
// RUN: diff %t.1 %t.2
// RUN: FileCheck -check-prefix=TEST1 %s < %t.d
// TEST1: foo:
// TEST1: dependencies-and-pp.c
// Test -MQ flag without quoting
// RUN: %clang -E -MD -MF %t.d -MQ foo -o %t %s
// RUN: FileCheck -check-prefix=TEST2 %s < %t.d
// TEST2: foo:
// Test -MQ flag with quoting
// RUN: %clang -E -MD -MF %t.d -MQ '$fo\ooo ooo\ ooo\\ ooo#oo' -o %t %s
// RUN: FileCheck -check-prefix=TEST3 %s < %t.d
// TEST3: $$fo\ooo\ ooo\\\ ooo\\\\\ ooo\#oo:
// Test consecutive -MT flags
// RUN: %clang -E -MD -MF %t.d -MT foo -MT bar -MT baz -o %t %s
// RUN: diff %t.1 %t
// RUN: FileCheck -check-prefix=TEST4 %s < %t.d
// TEST4: foo bar baz:
// Test consecutive -MT and -MQ flags
// RUN: %clang -E -MD -MF %t.d -MT foo -MQ '$(bar)' -MT 'b az' -MQ 'qu ux' -MQ ' space' -o %t %s
// RUN: FileCheck -check-prefix=TEST5 %s < %t.d
// TEST5: foo $$(bar) b az qu\ ux \ space:
// TODO: Test default target without quoting
// TODO: Test default target with quoting
|
{
"language": "Assembly"
}
|
; RUN: llc < %s -march=x86-64 | FileCheck %s
; CHECK: rBM_info
; CHECK-NOT: ret
@sES_closure = external global [0 x i64]
declare cc10 void @sEH_info(i64* noalias nocapture, i64* noalias nocapture, i64* noalias nocapture, i64, i64, i64) align 8
define cc10 void @rBM_info(i64* noalias nocapture %Base_Arg, i64* noalias nocapture %Sp_Arg, i64* noalias nocapture %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind align 8 {
c263:
%ln265 = getelementptr inbounds i64* %Sp_Arg, i64 -2
%ln266 = ptrtoint i64* %ln265 to i64
%ln268 = icmp ult i64 %ln266, %R3_Arg
br i1 %ln268, label %c26a, label %n26p
n26p: ; preds = %c263
br i1 icmp ne (i64 and (i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 7), i64 0), label %c1ZP.i, label %n1ZQ.i
n1ZQ.i: ; preds = %n26p
%ln1ZT.i = load i64* getelementptr inbounds ([0 x i64]* @sES_closure, i64 0, i64 0), align 8
%ln1ZU.i = inttoptr i64 %ln1ZT.i to void (i64*, i64*, i64*, i64, i64, i64)*
tail call cc10 void %ln1ZU.i(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind
br label %rBL_info.exit
c1ZP.i: ; preds = %n26p
tail call cc10 void @sEH_info(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind
br label %rBL_info.exit
rBL_info.exit: ; preds = %c1ZP.i, %n1ZQ.i
ret void
c26a: ; preds = %c263
%ln27h = getelementptr inbounds i64* %Base_Arg, i64 -2
%ln27j = load i64* %ln27h, align 8
%ln27k = inttoptr i64 %ln27j to void (i64*, i64*, i64*, i64, i64, i64)*
tail call cc10 void %ln27k(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind
ret void
}
|
{
"language": "Assembly"
}
|
LIBRARY libsvm
EXPORTS
svm_train @1
svm_cross_validation @2
svm_save_model @3
svm_load_model @4
svm_get_svm_type @5
svm_get_nr_class @6
svm_get_labels @7
svm_get_svr_probability @8
svm_predict_values @9
svm_predict @10
svm_predict_probability @11
svm_free_model_content @12
svm_free_and_destroy_model @13
svm_destroy_param @14
svm_check_parameter @15
svm_check_probability_model @16
svm_set_print_string_function @17
svm_get_sv_indices @18
svm_get_nr_sv @19
|
{
"language": "Assembly"
}
|
/**
* Touhou Community Reliant Automatic Patcher
* Main DLL
*
* ----
*
* Breakpoint entry point. Written for i686-w64-mingw32-as.
*/
.intel_syntax
.global _bp_entry, _bp_entry_localptr, _bp_entry_end
_bp_entry:
pusha
pushf
push %esp
_bp_entry_localptr:
push 0x12345678
/* Since we need to be position-independent... */
mov %eax, offset _breakpoint_process
call eax
add %esp, 8
add %esp, %eax
popf
popa
ret
_bp_entry_end:
|
{
"language": "Assembly"
}
|
*** TEST 23 ***
INIT - port_create - DP1 - internal = 16#1000# external = 16#2000#
TA1 - port_ident - 16#3A010001#
TA1 - port_external_to_internal - external: 16#200E# => internal: 16#100E#
TA1 - port_internal_to_external - internal: 16#100E# => external: 16#200E#
TA1 - port_external_to_internal - external: 16#300E# => internal: 16#300E#
TA1 - port_internal_to_external - internal: 16#50E# => external: 16#50E#
TA1 - port_delete - DP1
*** END OF TEST 23 ***
|
{
"language": "Assembly"
}
|
#!/usr/bin/env perl
# ====================================================================
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
# details see http://www.openssl.org/~appro/cryptogams/.
#
# Permission to use under GPL terms is granted.
# ====================================================================
# SHA256 block procedure for ARMv4. May 2007.
# Performance is ~2x better than gcc 3.4 generated code and in "abso-
# lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
# byte [on single-issue Xscale PXA250 core].
# July 2010.
#
# Rescheduling for dual-issue pipeline resulted in 22% improvement on
# Cortex A8 core and ~20 cycles per processed byte.
# February 2011.
#
# Profiler-assisted and platform-specific optimization resulted in 16%
# improvement on Cortex A8 core and ~15.4 cycles per processed byte.
# September 2013.
#
# Add NEON implementation. On Cortex A8 it was measured to process one
# byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
# S4 does it in 12.5 cycles too, but it's 50% faster than integer-only
# code (meaning that latter performs sub-optimally, nothing was done
# about it).
# May 2014.
#
# Add ARMv8 code path performing at 2.0 cpb on Apple A7.
while (($output=shift) && ($output!~/^\w[\w\-]*\.\w+$/)) {}
open STDOUT,">$output";
$ctx="r0"; $t0="r0";
$inp="r1"; $t4="r1";
$len="r2"; $t1="r2";
$T1="r3"; $t3="r3";
$A="r4";
$B="r5";
$C="r6";
$D="r7";
$E="r8";
$F="r9";
$G="r10";
$H="r11";
@V=($A,$B,$C,$D,$E,$F,$G,$H);
$t2="r12";
$Ktbl="r14";
@Sigma0=( 2,13,22);
@Sigma1=( 6,11,25);
@sigma0=( 7,18, 3);
@sigma1=(17,19,10);
sub BODY_00_15 {
my ($i,$a,$b,$c,$d,$e,$f,$g,$h) = @_;
$code.=<<___ if ($i<16);
#if __ARM_ARCH__>=7
@ ldr $t1,[$inp],#4 @ $i
# if $i==15
str $inp,[sp,#17*4] @ make room for $t4
# endif
eor $t0,$e,$e,ror#`$Sigma1[1]-$Sigma1[0]`
add $a,$a,$t2 @ h+=Maj(a,b,c) from the past
eor $t0,$t0,$e,ror#`$Sigma1[2]-$Sigma1[0]` @ Sigma1(e)
rev $t1,$t1
#else
@ ldrb $t1,[$inp,#3] @ $i
add $a,$a,$t2 @ h+=Maj(a,b,c) from the past
ldrb $t2,[$inp,#2]
ldrb $t0,[$inp,#1]
orr $t1,$t1,$t2,lsl#8
ldrb $t2,[$inp],#4
orr $t1,$t1,$t0,lsl#16
# if $i==15
str $inp,[sp,#17*4] @ make room for $t4
# endif
eor $t0,$e,$e,ror#`$Sigma1[1]-$Sigma1[0]`
orr $t1,$t1,$t2,lsl#24
eor $t0,$t0,$e,ror#`$Sigma1[2]-$Sigma1[0]` @ Sigma1(e)
#endif
___
$code.=<<___;
ldr $t2,[$Ktbl],#4 @ *K256++
add $h,$h,$t1 @ h+=X[i]
str $t1,[sp,#`$i%16`*4]
eor $t1,$f,$g
add $h,$h,$t0,ror#$Sigma1[0] @ h+=Sigma1(e)
and $t1,$t1,$e
add $h,$h,$t2 @ h+=K256[i]
eor $t1,$t1,$g @ Ch(e,f,g)
eor $t0,$a,$a,ror#`$Sigma0[1]-$Sigma0[0]`
add $h,$h,$t1 @ h+=Ch(e,f,g)
#if $i==31
and $t2,$t2,#0xff
cmp $t2,#0xf2 @ done?
#endif
#if $i<15
# if __ARM_ARCH__>=7
ldr $t1,[$inp],#4 @ prefetch
# else
ldrb $t1,[$inp,#3]
# endif
eor $t2,$a,$b @ a^b, b^c in next round
#else
ldr $t1,[sp,#`($i+2)%16`*4] @ from future BODY_16_xx
eor $t2,$a,$b @ a^b, b^c in next round
ldr $t4,[sp,#`($i+15)%16`*4] @ from future BODY_16_xx
#endif
eor $t0,$t0,$a,ror#`$Sigma0[2]-$Sigma0[0]` @ Sigma0(a)
and $t3,$t3,$t2 @ (b^c)&=(a^b)
add $d,$d,$h @ d+=h
eor $t3,$t3,$b @ Maj(a,b,c)
add $h,$h,$t0,ror#$Sigma0[0] @ h+=Sigma0(a)
@ add $h,$h,$t3 @ h+=Maj(a,b,c)
___
($t2,$t3)=($t3,$t2);
}
sub BODY_16_XX {
my ($i,$a,$b,$c,$d,$e,$f,$g,$h) = @_;
$code.=<<___;
@ ldr $t1,[sp,#`($i+1)%16`*4] @ $i
@ ldr $t4,[sp,#`($i+14)%16`*4]
mov $t0,$t1,ror#$sigma0[0]
add $a,$a,$t2 @ h+=Maj(a,b,c) from the past
mov $t2,$t4,ror#$sigma1[0]
eor $t0,$t0,$t1,ror#$sigma0[1]
eor $t2,$t2,$t4,ror#$sigma1[1]
eor $t0,$t0,$t1,lsr#$sigma0[2] @ sigma0(X[i+1])
ldr $t1,[sp,#`($i+0)%16`*4]
eor $t2,$t2,$t4,lsr#$sigma1[2] @ sigma1(X[i+14])
ldr $t4,[sp,#`($i+9)%16`*4]
add $t2,$t2,$t0
eor $t0,$e,$e,ror#`$Sigma1[1]-$Sigma1[0]` @ from BODY_00_15
add $t1,$t1,$t2
eor $t0,$t0,$e,ror#`$Sigma1[2]-$Sigma1[0]` @ Sigma1(e)
add $t1,$t1,$t4 @ X[i]
___
&BODY_00_15(@_);
}
$code=<<___;
#ifndef __KERNEL__
# include "arm_arch.h"
#else
# define __ARM_ARCH__ __LINUX_ARM_ARCH__
# define __ARM_MAX_ARCH__ 7
#endif
.text
#if __ARM_ARCH__<7
.code 32
#else
.syntax unified
# ifdef __thumb2__
.thumb
# else
.code 32
# endif
#endif
.type K256,%object
.align 5
K256:
.word 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
.word 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
.word 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
.word 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
.word 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
.word 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
.word 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
.word 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
.word 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
.word 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
.word 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
.word 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
.word 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
.word 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
.word 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
.word 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
.size K256,.-K256
.word 0 @ terminator
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
.LOPENSSL_armcap:
.word OPENSSL_armcap_P-sha256_block_data_order
#endif
.align 5
.global sha256_block_data_order
.type sha256_block_data_order,%function
sha256_block_data_order:
#if __ARM_ARCH__<7
sub r3,pc,#8 @ sha256_block_data_order
#else
adr r3,sha256_block_data_order
#endif
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
ldr r12,.LOPENSSL_armcap
ldr r12,[r3,r12] @ OPENSSL_armcap_P
tst r12,#ARMV8_SHA256
bne .LARMv8
tst r12,#ARMV7_NEON
bne .LNEON
#endif
add $len,$inp,$len,lsl#6 @ len to point at the end of inp
stmdb sp!,{$ctx,$inp,$len,r4-r11,lr}
ldmia $ctx,{$A,$B,$C,$D,$E,$F,$G,$H}
sub $Ktbl,r3,#256+32 @ K256
sub sp,sp,#16*4 @ alloca(X[16])
.Loop:
# if __ARM_ARCH__>=7
ldr $t1,[$inp],#4
# else
ldrb $t1,[$inp,#3]
# endif
eor $t3,$B,$C @ magic
eor $t2,$t2,$t2
___
for($i=0;$i<16;$i++) { &BODY_00_15($i,@V); unshift(@V,pop(@V)); }
$code.=".Lrounds_16_xx:\n";
for (;$i<32;$i++) { &BODY_16_XX($i,@V); unshift(@V,pop(@V)); }
$code.=<<___;
#if __ARM_ARCH__>=7
ite eq @ Thumb2 thing, sanity check in ARM
#endif
ldreq $t3,[sp,#16*4] @ pull ctx
bne .Lrounds_16_xx
add $A,$A,$t2 @ h+=Maj(a,b,c) from the past
ldr $t0,[$t3,#0]
ldr $t1,[$t3,#4]
ldr $t2,[$t3,#8]
add $A,$A,$t0
ldr $t0,[$t3,#12]
add $B,$B,$t1
ldr $t1,[$t3,#16]
add $C,$C,$t2
ldr $t2,[$t3,#20]
add $D,$D,$t0
ldr $t0,[$t3,#24]
add $E,$E,$t1
ldr $t1,[$t3,#28]
add $F,$F,$t2
ldr $inp,[sp,#17*4] @ pull inp
ldr $t2,[sp,#18*4] @ pull inp+len
add $G,$G,$t0
add $H,$H,$t1
stmia $t3,{$A,$B,$C,$D,$E,$F,$G,$H}
cmp $inp,$t2
sub $Ktbl,$Ktbl,#256 @ rewind Ktbl
bne .Loop
add sp,sp,#`16+3`*4 @ destroy frame
#if __ARM_ARCH__>=5
ldmia sp!,{r4-r11,pc}
#else
ldmia sp!,{r4-r11,lr}
tst lr,#1
moveq pc,lr @ be binary compatible with V4, yet
bx lr @ interoperable with Thumb ISA:-)
#endif
.size sha256_block_data_order,.-sha256_block_data_order
___
######################################################################
# NEON stuff
#
{{{
my @X=map("q$_",(0..3));
my ($T0,$T1,$T2,$T3,$T4,$T5)=("q8","q9","q10","q11","d24","d25");
my $Xfer=$t4;
my $j=0;
sub Dlo() { shift=~m|q([1]?[0-9])|?"d".($1*2):""; }
sub Dhi() { shift=~m|q([1]?[0-9])|?"d".($1*2+1):""; }
sub AUTOLOAD() # thunk [simplified] x86-style perlasm
{ my $opcode = $AUTOLOAD; $opcode =~ s/.*:://; $opcode =~ s/_/\./;
my $arg = pop;
$arg = "#$arg" if ($arg*1 eq $arg);
$code .= "\t$opcode\t".join(',',@_,$arg)."\n";
}
sub Xupdate()
{ use integer;
my $body = shift;
my @insns = (&$body,&$body,&$body,&$body);
my ($a,$b,$c,$d,$e,$f,$g,$h);
&vext_8 ($T0,@X[0],@X[1],4); # X[1..4]
eval(shift(@insns));
eval(shift(@insns));
eval(shift(@insns));
&vext_8 ($T1,@X[2],@X[3],4); # X[9..12]
eval(shift(@insns));
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T2,$T0,$sigma0[0]);
eval(shift(@insns));
eval(shift(@insns));
&vadd_i32 (@X[0],@X[0],$T1); # X[0..3] += X[9..12]
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T1,$T0,$sigma0[2]);
eval(shift(@insns));
eval(shift(@insns));
&vsli_32 ($T2,$T0,32-$sigma0[0]);
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T3,$T0,$sigma0[1]);
eval(shift(@insns));
eval(shift(@insns));
&veor ($T1,$T1,$T2);
eval(shift(@insns));
eval(shift(@insns));
&vsli_32 ($T3,$T0,32-$sigma0[1]);
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T4,&Dhi(@X[3]),$sigma1[0]);
eval(shift(@insns));
eval(shift(@insns));
&veor ($T1,$T1,$T3); # sigma0(X[1..4])
eval(shift(@insns));
eval(shift(@insns));
&vsli_32 ($T4,&Dhi(@X[3]),32-$sigma1[0]);
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T5,&Dhi(@X[3]),$sigma1[2]);
eval(shift(@insns));
eval(shift(@insns));
&vadd_i32 (@X[0],@X[0],$T1); # X[0..3] += sigma0(X[1..4])
eval(shift(@insns));
eval(shift(@insns));
&veor ($T5,$T5,$T4);
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T4,&Dhi(@X[3]),$sigma1[1]);
eval(shift(@insns));
eval(shift(@insns));
&vsli_32 ($T4,&Dhi(@X[3]),32-$sigma1[1]);
eval(shift(@insns));
eval(shift(@insns));
&veor ($T5,$T5,$T4); # sigma1(X[14..15])
eval(shift(@insns));
eval(shift(@insns));
&vadd_i32 (&Dlo(@X[0]),&Dlo(@X[0]),$T5);# X[0..1] += sigma1(X[14..15])
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T4,&Dlo(@X[0]),$sigma1[0]);
eval(shift(@insns));
eval(shift(@insns));
&vsli_32 ($T4,&Dlo(@X[0]),32-$sigma1[0]);
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T5,&Dlo(@X[0]),$sigma1[2]);
eval(shift(@insns));
eval(shift(@insns));
&veor ($T5,$T5,$T4);
eval(shift(@insns));
eval(shift(@insns));
&vshr_u32 ($T4,&Dlo(@X[0]),$sigma1[1]);
eval(shift(@insns));
eval(shift(@insns));
&vld1_32 ("{$T0}","[$Ktbl,:128]!");
eval(shift(@insns));
eval(shift(@insns));
&vsli_32 ($T4,&Dlo(@X[0]),32-$sigma1[1]);
eval(shift(@insns));
eval(shift(@insns));
&veor ($T5,$T5,$T4); # sigma1(X[16..17])
eval(shift(@insns));
eval(shift(@insns));
&vadd_i32 (&Dhi(@X[0]),&Dhi(@X[0]),$T5);# X[2..3] += sigma1(X[16..17])
eval(shift(@insns));
eval(shift(@insns));
&vadd_i32 ($T0,$T0,@X[0]);
while($#insns>=2) { eval(shift(@insns)); }
&vst1_32 ("{$T0}","[$Xfer,:128]!");
eval(shift(@insns));
eval(shift(@insns));
push(@X,shift(@X)); # "rotate" X[]
}
sub Xpreload()
{ use integer;
my $body = shift;
my @insns = (&$body,&$body,&$body,&$body);
my ($a,$b,$c,$d,$e,$f,$g,$h);
eval(shift(@insns));
eval(shift(@insns));
eval(shift(@insns));
eval(shift(@insns));
&vld1_32 ("{$T0}","[$Ktbl,:128]!");
eval(shift(@insns));
eval(shift(@insns));
eval(shift(@insns));
eval(shift(@insns));
&vrev32_8 (@X[0],@X[0]);
eval(shift(@insns));
eval(shift(@insns));
eval(shift(@insns));
eval(shift(@insns));
&vadd_i32 ($T0,$T0,@X[0]);
foreach (@insns) { eval; } # remaining instructions
&vst1_32 ("{$T0}","[$Xfer,:128]!");
push(@X,shift(@X)); # "rotate" X[]
}
sub body_00_15 () {
(
'($a,$b,$c,$d,$e,$f,$g,$h)=@V;'.
'&add ($h,$h,$t1)', # h+=X[i]+K[i]
'&eor ($t1,$f,$g)',
'&eor ($t0,$e,$e,"ror#".($Sigma1[1]-$Sigma1[0]))',
'&add ($a,$a,$t2)', # h+=Maj(a,b,c) from the past
'&and ($t1,$t1,$e)',
'&eor ($t2,$t0,$e,"ror#".($Sigma1[2]-$Sigma1[0]))', # Sigma1(e)
'&eor ($t0,$a,$a,"ror#".($Sigma0[1]-$Sigma0[0]))',
'&eor ($t1,$t1,$g)', # Ch(e,f,g)
'&add ($h,$h,$t2,"ror#$Sigma1[0]")', # h+=Sigma1(e)
'&eor ($t2,$a,$b)', # a^b, b^c in next round
'&eor ($t0,$t0,$a,"ror#".($Sigma0[2]-$Sigma0[0]))', # Sigma0(a)
'&add ($h,$h,$t1)', # h+=Ch(e,f,g)
'&ldr ($t1,sprintf "[sp,#%d]",4*(($j+1)&15)) if (($j&15)!=15);'.
'&ldr ($t1,"[$Ktbl]") if ($j==15);'.
'&ldr ($t1,"[sp,#64]") if ($j==31)',
'&and ($t3,$t3,$t2)', # (b^c)&=(a^b)
'&add ($d,$d,$h)', # d+=h
'&add ($h,$h,$t0,"ror#$Sigma0[0]");'. # h+=Sigma0(a)
'&eor ($t3,$t3,$b)', # Maj(a,b,c)
'$j++; unshift(@V,pop(@V)); ($t2,$t3)=($t3,$t2);'
)
}
$code.=<<___;
#if __ARM_MAX_ARCH__>=7
.arch armv7-a
.fpu neon
.global sha256_block_data_order_neon
.type sha256_block_data_order_neon,%function
.align 4
sha256_block_data_order_neon:
.LNEON:
stmdb sp!,{r4-r12,lr}
sub $H,sp,#16*4+16
adr $Ktbl,K256
bic $H,$H,#15 @ align for 128-bit stores
mov $t2,sp
mov sp,$H @ alloca
add $len,$inp,$len,lsl#6 @ len to point at the end of inp
vld1.8 {@X[0]},[$inp]!
vld1.8 {@X[1]},[$inp]!
vld1.8 {@X[2]},[$inp]!
vld1.8 {@X[3]},[$inp]!
vld1.32 {$T0},[$Ktbl,:128]!
vld1.32 {$T1},[$Ktbl,:128]!
vld1.32 {$T2},[$Ktbl,:128]!
vld1.32 {$T3},[$Ktbl,:128]!
vrev32.8 @X[0],@X[0] @ yes, even on
str $ctx,[sp,#64]
vrev32.8 @X[1],@X[1] @ big-endian
str $inp,[sp,#68]
mov $Xfer,sp
vrev32.8 @X[2],@X[2]
str $len,[sp,#72]
vrev32.8 @X[3],@X[3]
str $t2,[sp,#76] @ save original sp
vadd.i32 $T0,$T0,@X[0]
vadd.i32 $T1,$T1,@X[1]
vst1.32 {$T0},[$Xfer,:128]!
vadd.i32 $T2,$T2,@X[2]
vst1.32 {$T1},[$Xfer,:128]!
vadd.i32 $T3,$T3,@X[3]
vst1.32 {$T2},[$Xfer,:128]!
vst1.32 {$T3},[$Xfer,:128]!
ldmia $ctx,{$A-$H}
sub $Xfer,$Xfer,#64
ldr $t1,[sp,#0]
eor $t2,$t2,$t2
eor $t3,$B,$C
b .L_00_48
.align 4
.L_00_48:
___
&Xupdate(\&body_00_15);
&Xupdate(\&body_00_15);
&Xupdate(\&body_00_15);
&Xupdate(\&body_00_15);
$code.=<<___;
teq $t1,#0 @ check for K256 terminator
ldr $t1,[sp,#0]
sub $Xfer,$Xfer,#64
bne .L_00_48
ldr $inp,[sp,#68]
ldr $t0,[sp,#72]
sub $Ktbl,$Ktbl,#256 @ rewind $Ktbl
teq $inp,$t0
it eq
subeq $inp,$inp,#64 @ avoid SEGV
vld1.8 {@X[0]},[$inp]! @ load next input block
vld1.8 {@X[1]},[$inp]!
vld1.8 {@X[2]},[$inp]!
vld1.8 {@X[3]},[$inp]!
it ne
strne $inp,[sp,#68]
mov $Xfer,sp
___
&Xpreload(\&body_00_15);
&Xpreload(\&body_00_15);
&Xpreload(\&body_00_15);
&Xpreload(\&body_00_15);
$code.=<<___;
ldr $t0,[$t1,#0]
add $A,$A,$t2 @ h+=Maj(a,b,c) from the past
ldr $t2,[$t1,#4]
ldr $t3,[$t1,#8]
ldr $t4,[$t1,#12]
add $A,$A,$t0 @ accumulate
ldr $t0,[$t1,#16]
add $B,$B,$t2
ldr $t2,[$t1,#20]
add $C,$C,$t3
ldr $t3,[$t1,#24]
add $D,$D,$t4
ldr $t4,[$t1,#28]
add $E,$E,$t0
str $A,[$t1],#4
add $F,$F,$t2
str $B,[$t1],#4
add $G,$G,$t3
str $C,[$t1],#4
add $H,$H,$t4
str $D,[$t1],#4
stmia $t1,{$E-$H}
ittte ne
movne $Xfer,sp
ldrne $t1,[sp,#0]
eorne $t2,$t2,$t2
ldreq sp,[sp,#76] @ restore original sp
itt ne
eorne $t3,$B,$C
bne .L_00_48
ldmia sp!,{r4-r12,pc}
.size sha256_block_data_order_neon,.-sha256_block_data_order_neon
#endif
___
}}}
######################################################################
# ARMv8 stuff
#
{{{
my ($ABCD,$EFGH,$abcd)=map("q$_",(0..2));
my @MSG=map("q$_",(8..11));
my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15));
my $Ktbl="r3";
$code.=<<___;
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
# ifdef __thumb2__
# define INST(a,b,c,d) .byte c,d|0xc,a,b
# else
# define INST(a,b,c,d) .byte a,b,c,d
# endif
.type sha256_block_data_order_armv8,%function
.align 5
sha256_block_data_order_armv8:
.LARMv8:
vld1.32 {$ABCD,$EFGH},[$ctx]
# ifdef __thumb2__
adr $Ktbl,.LARMv8
sub $Ktbl,$Ktbl,#.LARMv8-K256
# else
adrl $Ktbl,K256
# endif
add $len,$inp,$len,lsl#6 @ len to point at the end of inp
.Loop_v8:
vld1.8 {@MSG[0]-@MSG[1]},[$inp]!
vld1.8 {@MSG[2]-@MSG[3]},[$inp]!
vld1.32 {$W0},[$Ktbl]!
vrev32.8 @MSG[0],@MSG[0]
vrev32.8 @MSG[1],@MSG[1]
vrev32.8 @MSG[2],@MSG[2]
vrev32.8 @MSG[3],@MSG[3]
vmov $ABCD_SAVE,$ABCD @ offload
vmov $EFGH_SAVE,$EFGH
teq $inp,$len
___
for($i=0;$i<12;$i++) {
$code.=<<___;
vld1.32 {$W1},[$Ktbl]!
vadd.i32 $W0,$W0,@MSG[0]
sha256su0 @MSG[0],@MSG[1]
vmov $abcd,$ABCD
sha256h $ABCD,$EFGH,$W0
sha256h2 $EFGH,$abcd,$W0
sha256su1 @MSG[0],@MSG[2],@MSG[3]
___
($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
}
$code.=<<___;
vld1.32 {$W1},[$Ktbl]!
vadd.i32 $W0,$W0,@MSG[0]
vmov $abcd,$ABCD
sha256h $ABCD,$EFGH,$W0
sha256h2 $EFGH,$abcd,$W0
vld1.32 {$W0},[$Ktbl]!
vadd.i32 $W1,$W1,@MSG[1]
vmov $abcd,$ABCD
sha256h $ABCD,$EFGH,$W1
sha256h2 $EFGH,$abcd,$W1
vld1.32 {$W1},[$Ktbl]
vadd.i32 $W0,$W0,@MSG[2]
sub $Ktbl,$Ktbl,#256-16 @ rewind
vmov $abcd,$ABCD
sha256h $ABCD,$EFGH,$W0
sha256h2 $EFGH,$abcd,$W0
vadd.i32 $W1,$W1,@MSG[3]
vmov $abcd,$ABCD
sha256h $ABCD,$EFGH,$W1
sha256h2 $EFGH,$abcd,$W1
vadd.i32 $ABCD,$ABCD,$ABCD_SAVE
vadd.i32 $EFGH,$EFGH,$EFGH_SAVE
it ne
bne .Loop_v8
vst1.32 {$ABCD,$EFGH},[$ctx]
ret @ bx lr
.size sha256_block_data_order_armv8,.-sha256_block_data_order_armv8
#endif
___
}}}
$code.=<<___;
.asciz "SHA256 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
.align 2
#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
.comm OPENSSL_armcap_P,4,4
#endif
___
open SELF,$0;
while(<SELF>) {
next if (/^#!/);
last if (!s/^#/@/ and !/^$/);
print;
}
close SELF;
{ my %opcode = (
"sha256h" => 0xf3000c40, "sha256h2" => 0xf3100c40,
"sha256su0" => 0xf3ba03c0, "sha256su1" => 0xf3200c40 );
sub unsha256 {
my ($mnemonic,$arg)=@_;
if ($arg =~ m/q([0-9]+)(?:,\s*q([0-9]+))?,\s*q([0-9]+)/o) {
my $word = $opcode{$mnemonic}|(($1&7)<<13)|(($1&8)<<19)
|(($2&7)<<17)|(($2&8)<<4)
|(($3&7)<<1) |(($3&8)<<2);
# since ARMv7 instructions are always encoded little-endian.
# correct solution is to use .inst directive, but older
# assemblers don't implement it:-(
sprintf "INST(0x%02x,0x%02x,0x%02x,0x%02x)\t@ %s %s",
$word&0xff,($word>>8)&0xff,
($word>>16)&0xff,($word>>24)&0xff,
$mnemonic,$arg;
}
}
}
foreach (split($/,$code)) {
s/\`([^\`]*)\`/eval $1/geo;
s/\b(sha256\w+)\s+(q.*)/unsha256($1,$2)/geo;
s/\bret\b/bx lr/go or
s/\bbx\s+lr\b/.word\t0xe12fff1e/go; # make it possible to compile with -march=armv4
print $_,"\n";
}
close STDOUT; # enforce flush
|
{
"language": "Assembly"
}
|
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
dech x0
// CHECK-INST: dech x0
// CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
dech x0, all
// CHECK-INST: dech x0
// CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
dech x0, all, mul #1
// CHECK-INST: dech x0
// CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
dech x0, all, mul #16
// CHECK-INST: dech x0, all, mul #16
// CHECK-ENCODING: [0xe0,0xe7,0x7f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 e7 7f 04 <unknown>
dech x0, pow2
// CHECK-INST: dech x0, pow2
// CHECK-ENCODING: [0x00,0xe4,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 e4 70 04 <unknown>
dech x0, vl1
// CHECK-INST: dech x0, vl1
// CHECK-ENCODING: [0x20,0xe4,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 e4 70 04 <unknown>
dech x0, vl2
// CHECK-INST: dech x0, vl2
// CHECK-ENCODING: [0x40,0xe4,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 40 e4 70 04 <unknown>
dech x0, vl3
// CHECK-INST: dech x0, vl3
// CHECK-ENCODING: [0x60,0xe4,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 e4 70 04 <unknown>
dech x0, vl4
// CHECK-INST: dech x0, vl4
// CHECK-ENCODING: [0x80,0xe4,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 e4 70 04 <unknown>
dech x0, vl5
// CHECK-INST: dech x0, vl5
// CHECK-ENCODING: [0xa0,0xe4,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 e4 70 04 <unknown>
dech x0, vl6
// CHECK-INST: dech x0, vl6
// CHECK-ENCODING: [0xc0,0xe4,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 e4 70 04 <unknown>
dech x0, vl7
// CHECK-INST: dech x0, vl7
// CHECK-ENCODING: [0xe0,0xe4,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 e4 70 04 <unknown>
dech x0, vl8
// CHECK-INST: dech x0, vl8
// CHECK-ENCODING: [0x00,0xe5,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 e5 70 04 <unknown>
dech x0, vl16
// CHECK-INST: dech x0, vl16
// CHECK-ENCODING: [0x20,0xe5,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 e5 70 04 <unknown>
dech x0, vl32
// CHECK-INST: dech x0, vl32
// CHECK-ENCODING: [0x40,0xe5,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 40 e5 70 04 <unknown>
dech x0, vl64
// CHECK-INST: dech x0, vl64
// CHECK-ENCODING: [0x60,0xe5,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 e5 70 04 <unknown>
dech x0, vl128
// CHECK-INST: dech x0, vl128
// CHECK-ENCODING: [0x80,0xe5,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 e5 70 04 <unknown>
dech x0, vl256
// CHECK-INST: dech x0, vl256
// CHECK-ENCODING: [0xa0,0xe5,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 e5 70 04 <unknown>
dech x0, #14
// CHECK-INST: dech x0, #14
// CHECK-ENCODING: [0xc0,0xe5,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 e5 70 04 <unknown>
dech x0, #28
// CHECK-INST: dech x0, #28
// CHECK-ENCODING: [0x80,0xe7,0x70,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 e7 70 04 <unknown>
|
{
"language": "Assembly"
}
|
.text
.globl target
.type target, @function
#! file-offset 0
#! rip-offset 0
#! capacity 4 bytes
# Text # Line RIP Bytes Opcode
.target: # 0 0 OPC=<label>
movq $0xffffffffffffffff, %r14 # 1 0 10 OPC=movq_r64_imm64
movswq %bx, %r12 # 2 0xa 4 OPC=movswq_r64_r16
xorw %r14w, %r12w # 3 0xe 4 OPC=xorw_r16_r16
movslq %r12d, %rbx # 4 0x12 3 OPC=movslq_r64_r32
retq # 5 0x15 1 OPC=retq
.size target, .-target
|
{
"language": "Assembly"
}
|
# frv testcase for fcbullr $FCCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global fcbullr
fcbullr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_fcc 0x0 0
fcbullr fcc0,0,0
set_spr_addr ok2,lr
set_fcc 0x1 1
fcbullr fcc1,0,1
fail
ok2:
set_spr_addr bad,lr
set_fcc 0x2 2
fcbullr fcc2,0,2
set_spr_addr ok4,lr
set_fcc 0x3 3
fcbullr fcc3,0,3
fail
ok4:
set_spr_addr ok5,lr
set_fcc 0x4 0
fcbullr fcc0,0,0
fail
ok5:
set_spr_addr ok6,lr
set_fcc 0x5 1
fcbullr fcc1,0,1
fail
ok6:
set_spr_addr ok7,lr
set_fcc 0x6 2
fcbullr fcc2,0,2
fail
ok7:
set_spr_addr ok8,lr
set_fcc 0x7 3
fcbullr fcc3,0,3
fail
ok8:
set_spr_addr bad,lr
set_fcc 0x8 0
fcbullr fcc0,0,0
set_spr_addr oka,lr
set_fcc 0x9 1
fcbullr fcc1,0,1
fail
oka:
set_spr_addr bad,lr
set_fcc 0xa 2
fcbullr fcc2,0,2
set_spr_addr okc,lr
set_fcc 0xb 3
fcbullr fcc3,0,3
fail
okc:
set_spr_addr okd,lr
set_fcc 0xc 0
fcbullr fcc0,0,0
fail
okd:
set_spr_addr oke,lr
set_fcc 0xd 1
fcbullr fcc1,0,1
fail
oke:
set_spr_addr okf,lr
set_fcc 0xe 2
fcbullr fcc2,0,2
fail
okf:
set_spr_addr okg,lr
set_fcc 0xf 3
fcbullr fcc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_fcc 0x0 0
fcbullr fcc0,1,0
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_fcc 0x1 1
fcbullr fcc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_fcc 0x2 2
fcbullr fcc2,1,2
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_fcc 0x3 3
fcbullr fcc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_fcc 0x4 0
fcbullr fcc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_fcc 0x5 1
fcbullr fcc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_fcc 0x6 2
fcbullr fcc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_fcc 0x7 3
fcbullr fcc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_fcc 0x8 0
fcbullr fcc0,1,0
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_fcc 0x9 1
fcbullr fcc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_fcc 0xa 2
fcbullr fcc2,1,2
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_fcc 0xb 3
fcbullr fcc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_fcc 0xc 0
fcbullr fcc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_fcc 0xd 1
fcbullr fcc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_fcc 0xe 2
fcbullr fcc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_fcc 0xf 3
fcbullr fcc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_fcc 0x0 0
fcbullr fcc0,1,0
set_fcc 0x1 1
fcbullr fcc1,1,1
set_fcc 0x2 2
fcbullr fcc2,1,2
set_fcc 0x3 3
fcbullr fcc3,1,3
set_fcc 0x4 0
fcbullr fcc0,1,0
set_fcc 0x5 1
fcbullr fcc1,1,1
set_fcc 0x6 2
fcbullr fcc2,1,2
set_fcc 0x7 3
fcbullr fcc3,1,3
set_fcc 0x8 0
fcbullr fcc0,1,0
set_fcc 0x9 1
fcbullr fcc1,1,1
set_fcc 0xa 2
fcbullr fcc2,1,2
set_fcc 0xb 3
fcbullr fcc3,1,3
set_fcc 0xc 0
fcbullr fcc0,1,0
set_fcc 0xd 1
fcbullr fcc1,1,1
set_fcc 0xe 2
fcbullr fcc2,1,2
set_fcc 0xf 3
fcbullr fcc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_fcc 0x0 0
fcbullr fcc0,0,0
set_spr_immed 1,lcr
set_fcc 0x1 1
fcbullr fcc1,0,1
set_spr_immed 1,lcr
set_fcc 0x2 2
fcbullr fcc2,0,2
set_spr_immed 1,lcr
set_fcc 0x3 3
fcbullr fcc3,0,3
set_spr_immed 1,lcr
set_fcc 0x4 0
fcbullr fcc0,0,0
set_spr_immed 1,lcr
set_fcc 0x5 1
fcbullr fcc1,0,1
set_spr_immed 1,lcr
set_fcc 0x6 2
fcbullr fcc2,0,2
set_spr_immed 1,lcr
set_fcc 0x7 3
fcbullr fcc3,0,3
set_spr_immed 1,lcr
set_fcc 0x8 0
fcbullr fcc0,0,0
set_spr_immed 1,lcr
set_fcc 0x9 1
fcbullr fcc1,0,1
set_spr_immed 1,lcr
set_fcc 0xa 2
fcbullr fcc2,0,2
set_spr_immed 1,lcr
set_fcc 0xb 3
fcbullr fcc3,0,3
set_spr_immed 1,lcr
set_fcc 0xc 0
fcbullr fcc0,0,0
set_spr_immed 1,lcr
set_fcc 0xd 1
fcbullr fcc1,0,1
set_spr_immed 1,lcr
set_fcc 0xe 2
fcbullr fcc2,0,2
set_spr_immed 1,lcr
set_fcc 0xf 3
fcbullr fcc3,0,3
pass
bad:
fail
|
{
"language": "Assembly"
}
|
INCLUDE "constants.asm"
SECTION "data/maps/objects/CaveMinecarts3.asm", ROMX
map_attributes CaveMinecarts3, CAVE_MINECARTS_3, 0
CaveMinecarts3_MapEvents::
dw $0 ; unknown
def_warp_events
def_bg_events
def_object_events
CaveMinecarts3_Blocks::
INCBIN "maps/CaveMinecarts3.blk"
|
{
"language": "Assembly"
}
|
.setcpu "6502"
.import nmi_int, init, irq_int ; Declared in lib/crt0.s
.segment "VECTORS" ; The linker script ld.cfg ensures
; that this segment is placed at
; the correct memory address
.addr nmi_int ; NMI vector
.addr init ; Reset vector
.addr irq_int ; IRQ/BRK vector
|
{
"language": "Assembly"
}
|
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-feature +htm -DHTM_HEADER -ffreestanding -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-feature +htm -DHTM_HEADER -ffreestanding -emit-llvm -x c++ -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-feature +htm -DHTMXL_HEADER -ffreestanding -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-feature +htm -DHTMXL_HEADER -ffreestanding -emit-llvm -x c++ -o - %s | FileCheck %s
#ifdef HTM_HEADER
#include <htmintrin.h>
#endif
#ifdef HTMXL_HEADER
#include <htmxlintrin.h>
#endif
// Verify that simply including the headers does not generate any code
// (i.e. all inline routines in the header are marked "static")
// CHECK: target triple = "powerpc64
// CHECK-NEXT: {{^$}}
// CHECK-NEXT: {{llvm\..*}}
|
{
"language": "Assembly"
}
|
; RUN: opt < %s -gvn -S | FileCheck %s
;
%0 = type { i64, i1 }
define i64 @test1(i64 %a, i64 %b) nounwind ssp {
entry:
%uadd = tail call %0 @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%uadd.0 = extractvalue %0 %uadd, 0
%add1 = add i64 %a, %b
ret i64 %add1
}
; CHECK-LABEL: @test1(
; CHECK-NOT: add1
; CHECK: ret
define i64 @test2(i64 %a, i64 %b) nounwind ssp {
entry:
%usub = tail call %0 @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%usub.0 = extractvalue %0 %usub, 0
%sub1 = sub i64 %a, %b
ret i64 %sub1
}
; CHECK-LABEL: @test2(
; CHECK-NOT: sub1
; CHECK: ret
define i64 @test3(i64 %a, i64 %b) nounwind ssp {
entry:
%umul = tail call %0 @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
%umul.0 = extractvalue %0 %umul, 0
%mul1 = mul i64 %a, %b
ret i64 %mul1
}
; CHECK-LABEL: @test3(
; CHECK-NOT: mul1
; CHECK: ret
define i64 @test4(i64 %a, i64 %b) nounwind ssp {
entry:
%sadd = tail call %0 @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
%sadd.0 = extractvalue %0 %sadd, 0
%add1 = add i64 %a, %b
ret i64 %add1
}
; CHECK-LABEL: @test4(
; CHECK-NOT: add1
; CHECK: ret
define i64 @test5(i64 %a, i64 %b) nounwind ssp {
entry:
%ssub = tail call %0 @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%ssub.0 = extractvalue %0 %ssub, 0
%sub1 = sub i64 %a, %b
ret i64 %sub1
}
; CHECK-LABEL: @test5(
; CHECK-NOT: sub1
; CHECK: ret
define i64 @test6(i64 %a, i64 %b) nounwind ssp {
entry:
%smul = tail call %0 @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
%smul.0 = extractvalue %0 %smul, 0
%mul1 = mul i64 %a, %b
ret i64 %mul1
}
; CHECK-LABEL: @test6(
; CHECK-NOT: mul1
; CHECK: ret
declare void @exit(i32) noreturn
declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
declare %0 @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
declare %0 @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
declare %0 @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
declare %0 @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
declare %0 @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
|
{
"language": "Assembly"
}
|
// RUN: llvm-mc %s -triple=aarch64-none-linux-gnu -filetype=asm -o - \
// RUN: | FileCheck %s --check-prefix=CHECK-ASM
// RUN: llvm-mc %s -triple=aarch64-none-linux-gnu -filetype=obj -o %t
// RUN: llvm-readobj -s -sd %t | FileCheck %s --check-prefix=CHECK-OBJ
// RUN: llvm-objdump -t %t | FileCheck %s --check-prefix=CHECK-SYMS
// RUN: llvm-mc %s -triple=aarch64_be-none-linux-gnu -filetype=asm -o - \
// RUN: | FileCheck %s --check-prefix=CHECK-ASM
// RUN: llvm-mc %s -triple=aarch64_be-none-linux-gnu -filetype=obj -o %t
// RUN: llvm-readobj -s -sd %t | FileCheck %s --check-prefix=CHECK-OBJ
// RUN: llvm-objdump -t %t | FileCheck %s --check-prefix=CHECK-SYMS
.section .inst.aarch64_inst
.p2align 2
.global aarch64_inst
.type aarch64_inst,%function
aarch64_inst:
.inst 0x5e104020
// CHECK-ASM: .p2align 2
// CHECK-ASM: .globl aarch64_inst
// CHECK-ASM: .type aarch64_inst,@function
// CHECK-ASM: aarch64_inst:
// CHECK-ASM: .inst 0x5e104020
// CHECK-OBJ: Section {
// CHECK-OBJ: Name: .inst.aarch64_inst
// CHECK-OBJ: SectionData (
// CHECK-OBJ-NEXT: 0000: 2040105E
// CHECK-OBJ-NEXT: )
// CHECK-SYMS-NOT: 0000000000000000 .inst.aarch64_inst 00000000 $d
// CHECK-SYMS: 0000000000000000 .inst.aarch64_inst 00000000 $x
// CHECK-SYMS-NOT: 0000000000000000 .inst.aarch64_inst 00000000 $d
|
{
"language": "Assembly"
}
|
config CRAMFS
tristate "Compressed ROM file system support (cramfs)"
select ZLIB_INFLATE
help
Saying Y here includes support for CramFs (Compressed ROM File
System). CramFs is designed to be a simple, small, and compressed
file system for ROM based embedded systems. CramFs is read-only,
limited to 256MB file systems (with 16MB files), and doesn't support
16/32 bits uid/gid, hard links and timestamps.
See <file:Documentation/filesystems/cramfs.txt> and
<file:fs/cramfs/README> for further information.
To compile this as a module, choose M here: the module will be called
cramfs. Note that the root file system (the one containing the
directory /) cannot be compiled as a module.
This filesystem is limited in capabilities and performance on
purpose to remain small and low on RAM usage. It is most suitable
for small embedded systems. If you have ample RAM to spare, you may
consider a more capable compressed filesystem such as SquashFS
which is much better in terms of performance and features.
If unsure, say N.
config CRAMFS_BLOCKDEV
bool "Support CramFs image over a regular block device" if EXPERT
depends on CRAMFS && BLOCK
default y
help
This option allows the CramFs driver to load data from a regular
block device such a disk partition or a ramdisk.
config CRAMFS_MTD
bool "Support CramFs image directly mapped in physical memory"
depends on CRAMFS && CRAMFS <= MTD
default y if !CRAMFS_BLOCKDEV
help
This option allows the CramFs driver to load data directly from
a linear adressed memory range (usually non volatile memory
like flash) instead of going through the block device layer.
This saves some memory since no intermediate buffering is
necessary.
The location of the CramFs image is determined by a
MTD device capable of direct memory mapping e.g. from
the 'physmap' map driver or a resulting MTD partition.
For example, this would mount the cramfs image stored in
the MTD partition named "xip_fs" on the /mnt mountpoint:
mount -t cramfs mtd:xip_fs /mnt
If unsure, say N.
|
{
"language": "Assembly"
}
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_iutsh/c_dsp32mac_dr_a1a0_iutsh.dsp
// Spec Reference: dsp32mac dr_a1a0 iutsh
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xb2bcfec7;
imm32 r2, 0xc1348679;
imm32 r3, 0xd0049007;
imm32 r4, 0x2efbc556;
imm32 r5, 0xcd35560b;
imm32 r6, 0xe00c807d;
imm32 r7, 0xf78e9008;
A1 = A0 = 0;
R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L) (IS);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L) (FU);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.L * R5.L) (M), R2.L = (A0 += R4.H * R5.H) (T);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H) (S2RND);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x13545ABD;
CHECKREG r1, 0x6BD10000;
CHECKREG r2, 0xEC48ED5B;
CHECKREG r3, 0x8000CEBE;
CHECKREG r4, 0x9CE8AA82;
CHECKREG r5, 0xE75ED19A;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0xF78E9008;
CHECKREG p1, 0x20296F89;
CHECKREG p2, 0x20296F89;
CHECKREG p3, 0x6BD12CD8;
CHECKREG p4, 0x00000000;
CHECKREG p5, 0xEC485EB2;
CHECKREG fp, 0xED5B71EE;
imm32 r0, 0x13545abd;
imm32 r1, 0x22bcfec7;
imm32 r2, 0x43348679;
imm32 r3, 0x50049007;
imm32 r4, 0x6fbc5569;
imm32 r5, 0x7d35560b;
imm32 r6, 0x800c807d;
imm32 r7, 0xf98e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L) (IU);
P1 = A1.w;
P2 = A0.w;
R6.H = (A1 += R2.L * R2.H), R6.L = (A0 = R2.H * R2.L) (TFU);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H) (ISS2);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H) (IH);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0x22BCFEC7;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x0F955721;
CHECKREG r4, 0x0F951905;
CHECKREG r5, 0x5721369E;
CHECKREG r6, 0x3689234C;
CHECKREG r7, 0xF98E9008;
CHECKREG p1, 0x133C5E4C;
CHECKREG p2, 0x5A4E0EEB;
CHECKREG p3, 0x368959E0;
CHECKREG p4, 0x234CFB94;
CHECKREG p5, 0x0CC36623;
CHECKREG fp, 0x59F2E980;
imm32 r0, 0x13545abd;
imm32 r1, 0x42bcfec7;
imm32 r2, 0x51348679;
imm32 r3, 0x60049007;
imm32 r4, 0x7fbc5569;
imm32 r5, 0x8d35560b;
imm32 r6, 0x900c807d;
imm32 r7, 0xa78e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.H * R0.L), R0.L = (A0 = R1.L * R0.L) (IS);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L) (IU);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H) (ISS2);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 -= R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H) (IH);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x7FFFFFFF;
CHECKREG r2, 0x7FFF8000;
CHECKREG r3, 0x69EBC4A8;
CHECKREG r4, 0x69EB64B4;
CHECKREG r5, 0xC4A864C1;
CHECKREG r6, 0x900C807D;
CHECKREG r7, 0xA78E9008;
CHECKREG p1, 0x17A75CCC;
CHECKREG p2, 0xFF910EEB;
CHECKREG p3, 0x4556D538;
CHECKREG p4, 0xD1E1967F;
CHECKREG p5, 0x2AEEA514;
CHECKREG fp, 0x989A946B;
imm32 r0, 0x03545abd;
imm32 r1, 0xb3bcfec7;
imm32 r2, 0x24348679;
imm32 r3, 0x60049007;
imm32 r4, 0x7fbc5569;
imm32 r5, 0x9d35560b;
imm32 r6, 0xa00c807d;
imm32 r7, 0x078e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L) (FU);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.H * R3.H), R1.L = (A0 = R2.H * R3.L) (TFU);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H) (IU);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 -= R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H) (S2RND);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x02560000;
CHECKREG r1, 0x0FEA145E;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x5145A344;
CHECKREG r5, 0x5B485C04;
CHECKREG r6, 0xA00C807D;
CHECKREG r7, 0x078E9008;
CHECKREG p1, 0x02562DB0;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x0FEA3E80;
CHECKREG p4, 0x145E3D6C;
CHECKREG p5, 0x4E70BDEC;
CHECKREG fp, 0x62CEFB58;
pass
|
{
"language": "Assembly"
}
|
/*
* RELIC is an Efficient LIbrary for Cryptography
* Copyright (C) 2007-2017 RELIC Authors
*
* This file is part of RELIC. RELIC is legal property of its developers,
* whose names are not listed here. Please refer to the COPYRIGHT file
* for contact information.
*
* RELIC is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* RELIC is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with RELIC. If not, see <http://www.gnu.org/licenses/>.
*/
#include "macro.s"
.text
.global cdecl(fp_muln_low)
.global cdecl(fp_mulm_low)
cdecl(fp_mulm_low):
push %r12
push %r13
push %r14
subq $64, %rsp
movq %rdx,%rcx
FP_MULN_LOW %rsp, %r8, %r9, %r10, 0(%rsi), 8(%rsi), 16(%rsi), 24(%rsi), 0(%rcx), 8(%rcx), 16(%rcx), 24(%rcx)
FP_RDCN_LOW %rdi, %rsp
addq $64, %rsp
pop %r14
pop %r13
pop %r12
ret
cdecl(fp_muln_low):
movq %rdx,%rcx
FP_MULN_LOW %rdi, %r8, %r9, %r10, 0(%rsi), 8(%rsi), 16(%rsi), 24(%rsi), 0(%rcx), 8(%rcx), 16(%rcx), 24(%rcx)
ret
|
{
"language": "Assembly"
}
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2020 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.67, "a"
.align 2
.weak _nds32_jmptbl_67
.type _nds32_jmptbl_67, @object
_nds32_jmptbl_67:
.word 0
.size _nds32_jmptbl_67, .-_nds32_jmptbl_67
|
{
"language": "Assembly"
}
|
; Copyright Oliver Kowalke 2009.
; Distributed under the Boost Software License, Version 1.0.
; (See accompanying file LICENSE_1_0.txt or copy at
; http://www.boost.org/LICENSE_1_0.txt)
; ---------------------------------------------------------------------------------
; | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
; ---------------------------------------------------------------------------------
; | 0h | 04h | 08h | 0ch | 010h | 014h | 018h | 01ch |
; ---------------------------------------------------------------------------------
; | fc_mxcsr|fc_x87_cw| fc_strg |fc_deallo| limit | base | fc_seh | EDI |
; ---------------------------------------------------------------------------------
; ---------------------------------------------------------------------------------
; | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
; ---------------------------------------------------------------------------------
; | 020h | 024h | 028h | 02ch | 030h | 034h | 038h | 03ch |
; ---------------------------------------------------------------------------------
; | ESI | EBX | EBP | EIP | to | data | EH NXT |SEH HNDLR|
; ---------------------------------------------------------------------------------
.386
.XMM
.model flat, c
.code
jump_fcontext PROC BOOST_CONTEXT_EXPORT
; prepare stack
lea esp, [esp-02ch]
IFNDEF BOOST_USE_TSX
; save MMX control- and status-word
stmxcsr [esp]
; save x87 control-word
fnstcw [esp+04h]
ENDIF
assume fs:nothing
; load NT_TIB into ECX
mov edx, fs:[018h]
assume fs:error
; load fiber local storage
mov eax, [edx+010h]
mov [esp+08h], eax
; load current deallocation stack
mov eax, [edx+0e0ch]
mov [esp+0ch], eax
; load current stack limit
mov eax, [edx+08h]
mov [esp+010h], eax
; load current stack base
mov eax, [edx+04h]
mov [esp+014h], eax
; load current SEH exception list
mov eax, [edx]
mov [esp+018h], eax
mov [esp+01ch], edi ; save EDI
mov [esp+020h], esi ; save ESI
mov [esp+024h], ebx ; save EBX
mov [esp+028h], ebp ; save EBP
; store ESP (pointing to context-data) in EAX
mov eax, esp
; firstarg of jump_fcontext() == fcontext to jump to
mov ecx, [esp+030h]
; restore ESP (pointing to context-data) from ECX
mov esp, ecx
IFNDEF BOOST_USE_TSX
; restore MMX control- and status-word
ldmxcsr [esp]
; restore x87 control-word
fldcw [esp+04h]
ENDIF
assume fs:nothing
; load NT_TIB into EDX
mov edx, fs:[018h]
assume fs:error
; restore fiber local storage
mov ecx, [esp+08h]
mov [edx+010h], ecx
; restore current deallocation stack
mov ecx, [esp+0ch]
mov [edx+0e0ch], ecx
; restore current stack limit
mov ecx, [esp+010h]
mov [edx+08h], ecx
; restore current stack base
mov ecx, [esp+014h]
mov [edx+04h], ecx
; restore current SEH exception list
mov ecx, [esp+018h]
mov [edx], ecx
mov ecx, [esp+02ch] ; restore EIP
mov edi, [esp+01ch] ; restore EDI
mov esi, [esp+020h] ; restore ESI
mov ebx, [esp+024h] ; restore EBX
mov ebp, [esp+028h] ; restore EBP
; prepare stack
lea esp, [esp+030h]
; return transfer_t
; FCTX == EAX, DATA == EDX
mov edx, [eax+034h]
; jump to context
jmp ecx
jump_fcontext ENDP
END
|
{
"language": "Assembly"
}
|
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <fcntl.h>
#ifndef _WIN32
#include <sys/mman.h>
#else
# include <windows.h>
#endif
/* LLONG_MAX came in after inttypes.h, limits.h is very old. */
#include <limits.h>
#if _POSIX_VERSION >= 199506L || defined(LLONG_MAX)
#include <inttypes.h>
#endif
#include "bf2any.h"
/*
* dasm64 translation from BF, runs at about 5,000,000,000 instructions per second.
*/
static gen_code_t gen_code;
struct be_interface_s be_interface = {.gen_code=gen_code, .cells_are_ints=1 };
#if defined(__x86_64__) || defined(__amd64__) || defined(_M_AMD64)
#define CPUCHECK 64
#define DASM_FOUND_CPU_X86_64
#elif defined(__i386__) || defined(_M_IX86)
#define CPUCHECK 32
#define DASM_FOUND_CPU_X86_32
#else
#warning "Supported processor not detected."
#endif
#ifndef DETECT_ONLY
#if !CPUCHECK
void outcmd(int ch, int count, char * strn) {
fprintf(stderr, "Build failed: Supported processor not detected.\n");
exit(255);
}
#else
#define DASM_FDEF static
#include "dynasm/dasm_proto.h"
#include "dynasm/dasm_x86.h"
/* The rest of the file is processed by DynASM then C.
*
* The Makefile takes care of making sure that the I386 flag matches
* the processor that the compiler detects by first preprocessing this
* code with 'DETECT_ONLY' enabled.
*/
/*
* The "actionlist" command defines the name of the data blob that
* the first pass of the assembler will use to pass it's data to the
* runtime pass.
*
* The "globals" command defines the prefix used for the data structure
* to store 'global label' numbers
*
* You can have multiple code sections, eg: for library routines. But in
* general you probably won't need to as you can probably run over your
* parse tree in the 'right' order.
*
* Note, it is possibly to use #if commands to break up pieces of
* code, but the assembler (pass1) will see ALL the lines of assembly
* irrespective of these directives; therefor all '.define' commands
* within a '#ifdef' will be active.
*
*/
|.if I386
||#define CPUID "i686"
||enum { okay=1/(CPUCHECK==32) };
|.arch x86
|.else
||#define CPUID "x86_64"
||enum { okay=1/(CPUCHECK==64) };
|.arch x64
|.endif
|.actionlist actions
|.section code
|.globals GLOB_
/* Using 32 bit working registers for both 32 and 64 bit. The REG_P register
* is 64 bit on x64 so that the memory can be malloc'd beyond the 2GB limit.
*
* Function pointers for getchar and putchar are used assuming that the
* program has been compiled with -mcmodel=large so that it won't break.
*/
|.if I386
|.define REG_P, esi
|.define REG_A, eax
|.define REG_AL, al
|.define REG_B, ebx
|.define REG_BL, bl
|.define REG_C, ecx
|.else
|.define REG_P, r15
|.define REG_A, eax
|.define REG_AL, al
|.define REG_B, ebx
|.define REG_BL, bl
|.define REG_C, ecx
/* Windows, of course, uses different registers for the parameters.
* This time it may not even be Microsoft's fault!?!? */
|.define PRM, rdi
|.endif
/* The state of the assembler at run time. Note that the 'Dst' name is
* hardcoded into the lua generation script. If you want to have multiple
* states available you must redefine this identifier. It is not safe
* to put any _code_generating_ assembly before this point. */
#define Dst &Dstate
static dasm_State *Dstate;
/* These are the named global labels prefixed in the assembler by the "->"
* sequence. The "GLOB_" prefix is from the .globals identifier above.
* Each label can only appear once in the generated machine code.
*/
static void* global_labels[GLOB__MAX];
/* A stack for a pair of labels for each open while loop. */
static struct stkdat { struct stkdat * up; int id; } *sp = 0;
/* This is the highest allocated dynamically generated label number */
static int maxpc = 0;
static void link_and_run(dasm_State **state);
static size_t tape_step = sizeof(int);
typedef int (*fnptr)(char * memory);
static char * tapemem;
static int acc_loaded = 0;
static int acc_offset = 0;
static int acc_dirty = 0;
static int acc_hi_dirty = 0;
static int imov = 0;
/* Make sure REG_A has been written out to the tape */
static void
clean_acc(void)
{
if (acc_loaded && acc_dirty) {
if (tape_step > 1) {
if (acc_offset) {
| mov [REG_P+acc_offset * tape_step], REG_A
} else {
| mov [REG_P], REG_A
}
} else {
if (acc_offset) {
| mov byte [REG_P+acc_offset], REG_AL
} else {
| mov byte [REG_P], REG_AL
}
}
acc_dirty = 0;
}
}
/* Set REG_A to contain the contents of tape cell "offset" but DO NOT read the
* current value from the tape.
* Save anything that was in REG_A before if needed.
*/
static void
set_acc_offset(int offset)
{
if (acc_loaded && acc_dirty && acc_offset != offset)
clean_acc();
acc_offset = offset;
acc_loaded = 1;
acc_dirty = 1;
acc_hi_dirty = 1;
}
/* Load the tape cell "offset" into REG_A, save anything that was in
* REG_A before if needed.
*/
static void
load_acc_offset(int offset)
{
if (acc_loaded) {
if (acc_offset == offset) return;
if (acc_dirty)
clean_acc();
}
acc_offset = offset;
if (tape_step > 1) {
if (acc_offset) {
| mov REG_A, [REG_P+acc_offset*tape_step]
} else {
| mov REG_A, [REG_P]
}
} else {
if (acc_offset) {
| movzx REG_A, byte [REG_P+acc_offset]
} else {
| movzx REG_A, byte [REG_P]
}
}
acc_loaded = 1;
acc_dirty = 0;
acc_hi_dirty = 0; /* (tape_step*8 != cell_size); */
}
static void
move_tape(void)
{
if (acc_loaded) acc_offset -= imov;
if (imov>0) {
| add REG_P, imov*tape_step
}
if (imov<0) {
| sub REG_P, -imov*tape_step
}
imov = 0;
}
static void failout(void) { fprintf(stderr, "STOP Command executed.\n"); exit(1); }
/* Called from the front end as normal */
static void
gen_code(int ch, int count, char * strn)
{
switch(ch) {
case '!':
/* dasm_init sets up the Dst data structure, the second argument is
* the number of code sections used by the ".section" command, I
* only need one. */
dasm_init(Dst, 1);
/* This is some boilerplate for the "->" global names, after
* the function dasm_encode is called the 'global_labels'
* array will have pointers to these labels. For example the
* start label below is in global_labels[GLOB_start]
*/
dasm_setupglobal(Dst, global_labels, GLOB__MAX);
/* Link up the C library to the generated blob of assembled data */
dasm_setup(Dst, actions);
if (bytecell) tape_step = 1; else tape_step = sizeof(int);
/* Create Stack frame. */
| ->start:
|.if I386
| push ebp
| push edi
| push esi
| push ebx
| mov ebp, esp
|
| mov REG_P, dword [ebp+20]
|.else
| push rbp
| push r15
| push r14
| push r13
| push rbx
|
| mov rbp, rsp
| sub rsp, 64 // Some shadow space for Windows.
|
#ifndef _WIN32
| mov REG_P, PRM
#else
| mov REG_P, rcx
#endif
|.endif
break;
case '>': imov += count; break;
case '<': imov -= count; break;
case '=':
set_acc_offset(imov);
if (count == 0) {
| xor REG_A, REG_A
} else {
| mov REG_A, count
}
break;
case 'B':
load_acc_offset(imov);
if (bytecell && acc_hi_dirty) {
| and REG_A, 255
acc_hi_dirty = 0;
}
| mov REG_B,REG_A
break;
case 'M':
load_acc_offset(imov);
set_acc_offset(imov);
| imul REG_C,REG_B,count
| add REG_A,REG_C
break;
case 'N':
load_acc_offset(imov);
set_acc_offset(imov);
| imul REG_C,REG_B,count
| sub REG_A,REG_C
break;
case 'S':
load_acc_offset(imov);
set_acc_offset(imov);
| add REG_A,REG_B
break;
case 'T':
load_acc_offset(imov);
set_acc_offset(imov);
| sub REG_A,REG_B
break;
case '*':
load_acc_offset(imov);
set_acc_offset(imov);
| imul REG_A,REG_B
break;
case 'C':
set_acc_offset(imov);
| imul REG_A,REG_B,count
break;
case 'D':
set_acc_offset(imov);
| imul REG_A,REG_B,-count
break;
case 'V':
set_acc_offset(imov);
| mov REG_A,REG_B
break;
case 'W':
set_acc_offset(imov);
| mov REG_A,REG_B
| neg REG_A
break;
case '+':
load_acc_offset(imov);
set_acc_offset(imov);
| add REG_A, count
break;
case '-':
load_acc_offset(imov);
set_acc_offset(imov);
| sub REG_A, count
break;
case 'X':
|.if I386
| call &failout
|.else
#if (defined(__code_model_small__) && !defined(__PIC__)) || defined(__ILP32__)
| mov eax, (uintptr_t) failout
#else
| mov64 rax, (uintptr_t) failout
#endif
| call rax
|.endif
break;
case '[':
{
struct stkdat * n = malloc(sizeof*n);
n->up = sp;
sp = n;
maxpc += 2;
n->id = maxpc;
dasm_growpc(Dst, maxpc);
clean_acc();
move_tape();
load_acc_offset(0);
clean_acc();
if (bytecell) {
| cmp REG_AL, 0
} else {
| cmp REG_A, 0
}
| jz =>(maxpc-2)
| =>(maxpc-1):
/* The "=>" style labels are the most useful form, they give you
* an indefinite set of normal labels for use as jump targets.
* You MUST allocate space for a label with "dasm_growpc" before
* you process the assembler that references it.
*/
}
break;
case ']':
{
struct stkdat * n = sp;
int setpc;
sp = n->up;
setpc = n->id;
free(n);
clean_acc();
move_tape();
load_acc_offset(0);
clean_acc();
if (bytecell) {
| cmp REG_AL, 0
} else {
| cmp REG_A, 0
}
| jne =>(setpc-1)
| =>(setpc-2):
}
break;
case 'I':
{
struct stkdat * n = malloc(sizeof*n);
n->up = sp;
sp = n;
maxpc += 1;
n->id = maxpc;
dasm_growpc(Dst, maxpc);
clean_acc();
move_tape();
load_acc_offset(0);
clean_acc();
if (bytecell) {
| cmp REG_AL, 0
} else {
| cmp REG_A, 0
}
| jz =>(maxpc-1)
/* The "=>" style labels are the most useful form, they give you
* an indefinite set of normal labels for use as jump targets.
* You MUST allocate space for a label with "dasm_growpc" before
* you process the assembler that references it.
*/
}
break;
case 'E':
{
struct stkdat * n = sp;
int setpc;
sp = n->up;
setpc = n->id;
free(n);
clean_acc();
move_tape();
acc_loaded = 0;
| =>(setpc-1):
}
break;
case ',':
/* Note: REG_A must be eax/rax */
clean_acc();
set_acc_offset(imov);
|.if I386
| call &getchar
|.else
#if (defined(__code_model_small__) && !defined(__PIC__)) || defined(__ILP32__)
| mov eax, (uintptr_t) getchar
| call rax
#else
| mov64 rax, (uintptr_t) getchar
| call rax
#endif
|.endif
| cmp REG_A, -1
| jz >1
clean_acc();
acc_loaded = 0;
| 1:
/* The ">1" and "1:" are local labels where you can jump forward or
* backward to (only) the next label with that number.
*
* Unfortunatly there are only ten of these so I could not use them
* for the main while() loop processing as I've done in the bf2gas
* generator.
*/
break;
case '.':
clean_acc();
move_tape();
acc_loaded = 0;
|.if I386
| movzx eax, byte [REG_P]
| push eax
| call &putchar
| pop eax
|.else
#ifndef _WIN32
| movzx PRM, byte [REG_P]
#else
| movzx rcx, byte [REG_P]
#endif
#if (defined(__code_model_small__) && !defined(__PIC__)) || defined(__ILP32__)
| mov eax, (uintptr_t) putchar
| call rax
#else
| mov64 rax, (uintptr_t) putchar
| call rax
#endif
|.endif
break;
case '"':
{
char * str = strn;
if (!str) break;
clean_acc();
move_tape();
acc_loaded = 0;
for(; *str; str++) {
|.if I386
| mov eax, *str
| push eax
| call &putchar
| pop eax
|.else
#ifndef _WIN32
| mov PRM, *str
#else
| mov rcx, *str
#endif
#if (defined(__code_model_small__) && !defined(__PIC__)) || defined(__ILP32__)
| mov eax, (uintptr_t) putchar
| call rax
#else
| mov64 rax, (uintptr_t) putchar
| call rax
#endif
|.endif
}
}
break;
case '~':
clean_acc();
|.if I386
| xor eax, eax
| mov esp, ebp
| pop ebx
| pop esi
| pop edi
| pop ebp
|.else
| xor rax, rax
| mov rsp, rbp
| pop rbx
| pop r13
| pop r14
| pop r15
| pop rbp
|.endif
| ret
link_and_run(Dst);
break;
}
}
#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
#define MAP_ANONYMOUS MAP_ANON
#endif
#if defined(__minix__)
#define NO_MPROTECT
#endif
#if !defined(MAP_FAILED)
#define MAP_FAILED (-1)
#endif
static void
link_and_run(dasm_State ** state)
{
/* dasm_link is the second pass of the assembler, the first phase of the
* first pass is the lua code which converts the assembler into code
* fragments in the C file generated from the 'dasc' file. The second
* phase happens at run time and orders and duplicates these fragments
* when 'outcmd' is called.
*
* This pass resolves all the labels relative to the segments and joins
* the segments together onto one unit of code. The size of this code
* is returned in the 'size' argument.
*/
fnptr code = 0;
char *codeptr;
size_t codelen;
int dasm_status = dasm_link(state, &codelen);
if (dasm_status != DASM_S_OK) {
fprintf(stderr, "Process dasm_link() failed\n");
exit(1);
}
(void)dasm_getpclabel; /* Unused */
#ifndef _WIN32
#ifdef MAP_ANONYMOUS
/* I allocate this with a 'PROT_EXEC' flag set so the kernel can choose
* to put it in the 'code area' if there is such a thing (i386) */
codeptr =
(char *) mmap(NULL, codelen,
#ifdef NO_MPROTECT
PROT_WRITE |
#endif
PROT_READ | PROT_EXEC,
MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
#else
/* This'll probably only work with Linux ... Oh, FreeBSD too. */
{
int fd = open("/dev/zero", O_RDWR);
if (fd >= 0) {
codeptr =
(char *) mmap(NULL, codelen,
#ifdef NO_MPROTECT
PROT_WRITE |
#endif
PROT_READ | PROT_EXEC, MAP_PRIVATE, fd, 0);
close(fd);
} else
codeptr = MAP_FAILED;
}
#endif
if (codeptr == MAP_FAILED) {
perror("Unable to allocate memory for executable");
exit(1);
}
#ifndef NO_MPROTECT
if (mprotect(codeptr, codelen, PROT_WRITE | PROT_READ) != 0) {
perror("mprotect to enable code writing");
};
#endif
#else /*_WIN32*/
codeptr = (char*) VirtualAlloc(0, codelen, MEM_COMMIT, PAGE_EXECUTE_READWRITE);
if (!codeptr) {
perror("Unable to allocate executable memory");
exit(1);
}
#endif
/* Last phase: Stream out the code fragments into proper machine
* code doing the final absolute relocations.
*
* Also after this phase completes the globals array and
* dasm_getpclabel can be used to find the addresses for
* '->' and '=>' style labels respectivly.
*/
dasm_encode(state, codeptr);
/* This frees up all state for the assembler, everything must go. */
/* In particular 'dasm_getpclabel()' can no longer be called */
dasm_free(state);
/* Make it read only before we run it; also means that a context switch
* happens so there won't be any 'bad cache' effects */
#ifndef __WIN32
#ifndef NO_MPROTECT
if (mprotect(codeptr, codelen, PROT_EXEC | PROT_READ) != 0) {
perror("mprotect read only");
};
#endif
#else
DWORD oldProt = 0;
if (!VirtualProtect(codeptr, codelen, PAGE_EXECUTE_READ, &oldProt)) {
perror("VirtualProtect read only failed");
}
#endif
#if 0
/* Write generated machine code to a temporary file.
* View with:
* objdump -D -b binary -mi386 -Mx86,intel code.bin
* or
* ndisasm -b32 code.bin
*/
FILE *f = fopen("/tmp/code.bin", "w");
fwrite(codeptr, codelen, 1, f);
fclose(f);
fprintf(stderr, "codeptr = 0x%lx\n", (unsigned long) codeptr);
fprintf(stderr, "codelen = 0x%lx\n", (unsigned long) codelen);
fprintf(stderr, "putchar = 0x%lx\n", (unsigned long) &putchar);
fprintf(stderr, "getchar = 0x%lx\n", (unsigned long) &getchar);
#endif
/* Remove the stdout output buffer */
if (isatty(STDOUT_FILENO)) setbuf(stdout, 0);
/* Memory for the tape. */
tapemem = calloc(tapesz, tape_step);
/* The C99 standard leaves casting from "void *" to a function
pointer undefined. The assignment used below is the POSIX.1-2003
(Technical Corrigendum 1) workaround; see the Rationale for the
POSIX specification of dlsym(). */
/* -- Linux man page dlsym() */
*(void **) (&code) = (void *) codeptr;
code(tapemem + tape_step * tapeinit);
/* Discard code and data */
#ifndef _WIN32
if (munmap(codeptr, codelen) != 0)
perror("munmap(codeptr, codelen)");
#else
(void)VirtualFree(codeptr, 0, MEM_RELEASE);
#endif
free(tapemem);
}
#endif
#endif
|
{
"language": "Assembly"
}
|
; RUN: opt -lowertypetests -lowertypetests-summary-action=export -lowertypetests-write-summary=%t -o /dev/null %s
; RUN: FileCheck %s < %t
; CHECK: ---
; CHECK-NEXT: GlobalValueMap:
; CHECK-NEXT: TypeIdMap:
; CHECK-NEXT: ...
|
{
"language": "Assembly"
}
|
config BR2_PACKAGE_LIBSVGTINY
bool "libsvgtiny"
select BR2_PACKAGE_LIBXML2
help
Libsvgtiny is an implementation of SVG Tiny, written in C.
It is currently in development for use with NetSurf and is
intended to be suitable for use in other projects too.
http://www.netsurf-browser.org/projects/libsvgtiny/
|
{
"language": "Assembly"
}
|
// Modified by Princeton University on June 9th, 2015
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: tso_int_stress1.s
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/***************************************************************************
***
*** Test Description : interrupts
***
**********************************************************************/
#define ASI_SWVR_INTR_RECEIVE 0x72
#define ASI_SWVR_UDB_INTR_W 0x73
#define ASI_SWVR_UDB_INTR_R 0x74
#define H_T0_Trap_Instruction_0
#define My_T0_Trap_Instruction_0 \
ta 0x90; \
done;
#define H_HT0_HTrap_Instruction_0 intr0x190_custom_trap
#define My_HT0_HTrap_Instruction_0 \
stxa %o0, [%g0] ASI_SWVR_UDB_INTR_W; \
done;
#define H_HT0_Interrupt_0x60 intr0x60_custom_trap
#define MAIN_TEXT_DATA_ALSO
#include "boot.s"
.text
.global main
main:
setx 0x80, %l1, %l7
th_fork(th_main, %l0)
!----------------------
th_main_0:
add %g0, 0, %i0
setx user_data_start, %l1, %o1
nop
ploop0: ! wait for the other
brnz %l7, ploop0
st %l7, [%o1]
ba normal_end
nop
!----------------------
th_main_1:
add %g0, 1, %i0
loop1:
ba loop1
nop
!----------------------------
th_main_2:
th_main_3:
add %g0, 2, %i0
setx ploop0, %l1, %o1
loop2:
ldx [%o1], %o2
ba loop2
stx %o2, [%o1]
!----------------------------
th_main_4:
add %g0, 0x0, %o0
add %g0, 0x80, %l0
setx user_data_start, %l1, %o1
loop4:
ld [%o1], %i1
ta 0x30
loop4i:
ld [%o1], %i2
sub %i1, %i2, %i2
brz %i2, loop4i
nop
dec %l0
brnz %l0, loop4
nop
ba normal_end
nop
!----------------------------
th_main_5:
th_main_6:
th_main_7:
th_main_8:
th_main_9:
th_main_10:
th_main_11:
th_main_12:
th_main_13:
th_main_14:
th_main_15:
th_main_16:
th_main_17:
th_main_18:
th_main_19:
th_main_20:
th_main_21:
th_main_22:
th_main_23:
th_main_24:
th_main_25:
th_main_26:
th_main_27:
th_main_28:
th_main_29:
th_main_30:
th_main_31:
th_main_32:
add %g0, 0x100, %o0
inf_loop:
ba inf_loop
ta 0x30
normal_end:
ta T_GOOD_TRAP
bad_end:
ta T_BAD_TRAP
user_text_end:
/***********************************************************************
Test case data start
***********************************************************************/
.data
user_data_start:
.word 0x80
.skip 1000
user_data_end:
SECTION .MY_HYP_SEC TEXT_VA = 0x1100150000, DATA_VA = 0x1100160000
attr_text {
Name=.MY_HYP_SEC,
hypervisor
}
! this is the interrupt trap. Both producer and consumer get it.
! consumer checks data and tells the producer to proceed.
! producer proceeds when it got this trap.
.global intr0x60_custom_trap
intr0x60_custom_trap:
ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g2;
ldxa [%g0] ASI_SWVR_UDB_INTR_R, %g1;
brnz %i0, bypass_dec
nop
dec %l7
bypass_dec:
retry
!-----------------------------------------------------------------------
! this is the user defined producer trap.
.global intr0x190_custom_trap
intr0x190_custom_trap:
stxa %o0, [%g0] ASI_SWVR_UDB_INTR_W; ! send an interrupt
done;
!-----------------------------------------------------------------------
attr_data {
Name=.MY_HYP_SEC,
hypervisor
}
.global my_hyp_data
.align 0x40
my_hyp_data:
.skip 0x200
.end
|
{
"language": "Assembly"
}
|
# RUN: llvm-mc -triple x86_64-pc-linux %s -filetype=obj | \
# RUN: not llvm-dwarfdump -verify - | FileCheck %s
# CHECK: error: NameIndex @ 0x0: Abbreviation 0x2: DW_IDX_compile_unit uses an unexpected form DW_FORM_ref1 (expected form class constant).
# CHECK: error: NameIndex @ 0x0: Abbreviation 0x2: DW_IDX_type_unit uses an unexpected form DW_FORM_ref1 (expected form class constant).
# CHECK: error: NameIndex @ 0x0: Abbreviation 0x2: DW_IDX_type_hash uses an unexpected form DW_FORM_data4 (should be DW_FORM_data8).
# CHECK: warning: NameIndex @ 0x0: Abbreviation 0x2 contains an unknown index attribute: DW_IDX_unknown_2020.
# CHECK: error: NameIndex @ 0x0: Abbreviation 0x4 contains multiple DW_IDX_die_offset attributes.
# CHECK: NameIndex @ 0x0: Abbreviation 0x1: DW_IDX_die_offset uses an unknown form: DW_FORM_unknown_1fff.
# CHECK: warning: NameIndex @ 0x0: Abbreviation 0x3 references an unknown tag: DW_TAG_unknown_8080.
# CHECK: error: NameIndex @ 0x0: Abbreviation 0x5 has no DW_IDX_die_offset attribute.
# CHECK: error: NameIndex @ 0x55: Indexing multiple compile units and abbreviation 0x1 has no DW_IDX_compile_unit attribute.
.section .debug_str,"MS",@progbits,1
.Lstring_producer:
.asciz "Hand-written dwarf"
.section .debug_abbrev,"",@progbits
.Lsection_abbrev:
.byte 1 # Abbreviation Code
.byte 17 # DW_TAG_compile_unit
.byte 1 # DW_CHILDREN_yes
.byte 37 # DW_AT_producer
.byte 14 # DW_FORM_strp
.byte 19 # DW_AT_language
.byte 5 # DW_FORM_data2
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 0 # EOM(3)
.section .debug_info,"",@progbits
.Lcu_begin0:
.long .Lcu_end0-.Lcu_start0 # Length of Unit
.Lcu_start0:
.short 4 # DWARF version number
.long .Lsection_abbrev # Offset Into Abbrev. Section
.byte 8 # Address Size (in bytes)
.byte 1 # Abbrev [1] DW_TAG_compile_unit
.long .Lstring_producer # DW_AT_producer
.short 12 # DW_AT_language
.byte 0 # End Of Children Mark
.Lcu_end0:
.Lcu_begin1:
.long .Lcu_end1-.Lcu_start1 # Length of Unit
.Lcu_start1:
.short 4 # DWARF version number
.long .Lsection_abbrev # Offset Into Abbrev. Section
.byte 8 # Address Size (in bytes)
.byte 1 # Abbrev [1] DW_TAG_compile_unit
.long .Lstring_producer # DW_AT_producer
.short 12 # DW_AT_language
.byte 0 # End Of Children Mark
.Lcu_end1:
.Lcu_begin2:
.long .Lcu_end2-.Lcu_start2 # Length of Unit
.Lcu_start2:
.short 4 # DWARF version number
.long .Lsection_abbrev # Offset Into Abbrev. Section
.byte 8 # Address Size (in bytes)
.byte 1 # Abbrev [1] DW_TAG_compile_unit
.long .Lstring_producer # DW_AT_producer
.short 12 # DW_AT_language
.byte 0 # End Of Children Mark
.Lcu_end2:
.section .debug_names,"",@progbits
.long .Lnames_end0-.Lnames_start0 # Header: contribution length
.Lnames_start0:
.short 5 # Header: version
.short 0 # Header: padding
.long 1 # Header: compilation unit count
.long 0 # Header: local type unit count
.long 0 # Header: foreign type unit count
.long 0 # Header: bucket count
.long 0 # Header: name count
.long .Lnames_abbrev_end0-.Lnames_abbrev_start0 # Header: abbreviation table size
.long 0 # Header: augmentation length
.long .Lcu_begin0 # Compilation unit 0
.Lnames_abbrev_start0:
.byte 1 # Abbrev code
.byte 46 # DW_TAG_subprogram
.byte 3 # DW_IDX_die_offset
.uleb128 0x1fff # DW_FORM_unknown_1fff
.byte 0 # End of abbrev
.byte 0 # End of abbrev
.byte 2 # Abbrev code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_IDX_compile_unit
.byte 17 # DW_FORM_ref1
.byte 2 # DW_IDX_type_unit
.byte 17 # DW_FORM_ref1
.byte 2 # DW_IDX_type_unit
.byte 5 # DW_FORM_data2
.byte 5 # DW_IDX_type_hash
.byte 6 # DW_FORM_data4
.uleb128 0x2020 # DW_IDX_unknown_2020
.byte 6 # DW_FORM_data4
.byte 0 # End of abbrev
.byte 0 # End of abbrev
.byte 3 # Abbrev code
.uleb128 0x8080 # DW_TAG_unknown_8080
.byte 3 # DW_IDX_die_offset
.byte 17 # DW_FORM_ref1
.byte 0 # End of abbrev
.byte 0 # End of abbrev
.byte 4 # Abbrev code
.byte 46 # DW_TAG_subprogram
.byte 3 # DW_IDX_die_offset
.byte 17 # DW_FORM_ref1
.byte 3 # DW_IDX_die_offset
.byte 17 # DW_FORM_ref1
.byte 0 # End of abbrev
.byte 0 # End of abbrev
.byte 5 # Abbrev code
.byte 46 # DW_TAG_subprogram
.byte 4 # DW_IDX_parent
.byte 5 # DW_FORM_data2
.byte 0 # End of abbrev
.byte 0 # End of abbrev
.byte 0 # End of abbrev list
.Lnames_abbrev_end0:
.Lnames_end0:
.long .Lnames_end1-.Lnames_start1 # Header: contribution length
.Lnames_start1:
.short 5 # Header: version
.short 0 # Header: padding
.long 2 # Header: compilation unit count
.long 0 # Header: local type unit count
.long 0 # Header: foreign type unit count
.long 0 # Header: bucket count
.long 0 # Header: name count
.long .Lnames_abbrev_end1-.Lnames_abbrev_start1 # Header: abbreviation table size
.long 0 # Header: augmentation length
.long .Lcu_begin1 # Compilation unit 0
.long .Lcu_begin2 # Compilation unit 1
.Lnames_abbrev_start1:
.byte 1 # Abbrev code
.byte 46 # DW_TAG_subprogram
.byte 3 # DW_IDX_die_offset
.byte 17 # DW_FORM_ref1
.byte 0 # End of abbrev
.byte 0 # End of abbrev
.byte 0 # End of abbrev list
.Lnames_abbrev_end1:
.Lnames_end1:
|
{
"language": "Assembly"
}
|
http://gcc.gnu.org/ml/gcc-patches/2008-10/msg00269.html
On glibc the libc.so carries a copy of the math function copysignl() but
on uClibc math functions like copysignl() live in libm. Since libgcc_s
contains unresolved symbols, any attempt to link against libgcc_s
without explicitely specifying -lm fails, resulting in a broken
bootstrap of the compiler.
Forward port to gcc 4.5.1 by Gustavo Zacarias <gustavo@zacarias.com.ar>
---
libgcc/Makefile.in | 4 +++-
libgcc/configure | 32 ++++++++++++++++++++++++++++++++
libgcc/configure.ac | 21 +++++++++++++++++++++
3 files changed, 56 insertions(+), 1 deletion(-)
Index: gcc-4.8.0/libgcc/Makefile.in
===================================================================
--- gcc-4.8.0.orig/libgcc/Makefile.in 2013-02-04 20:06:20.000000000 +0100
+++ gcc-4.8.0/libgcc/Makefile.in 2013-03-24 09:12:43.000000000 +0100
@@ -41,6 +41,7 @@
decimal_float = @decimal_float@
enable_decimal_float = @enable_decimal_float@
fixed_point = @fixed_point@
+LIBGCC_LIBM = @LIBGCC_LIBM@
host_noncanonical = @host_noncanonical@
target_noncanonical = @target_noncanonical@
@@ -927,9 +928,10 @@
@multilib_dir@,$(MULTIDIR),$(subst \
@shlib_objs@,$(objects) libgcc.a,$(subst \
@shlib_base_name@,libgcc_s,$(subst \
+ @libgcc_libm@,$(LIBGCC_LIBM),$(subst \
@shlib_map_file@,$(mapfile),$(subst \
@shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(subst \
- @shlib_slibdir@,$(shlib_slibdir),$(SHLIB_LINK))))))))
+ @shlib_slibdir@,$(shlib_slibdir),$(SHLIB_LINK)))))))))
libunwind$(SHLIB_EXT): $(libunwind-s-objects) $(extra-parts)
# @multilib_flags@ is still needed because this may use
Index: gcc-4.8.0/libgcc/configure
===================================================================
--- gcc-4.8.0.orig/libgcc/configure 2012-11-05 00:08:42.000000000 +0100
+++ gcc-4.8.0/libgcc/configure 2013-03-24 09:12:43.000000000 +0100
@@ -564,6 +564,7 @@
tmake_file
sfp_machine_header
set_use_emutls
+LIBGCC_LIBM
set_have_cc_tls
vis_hide
fixed_point
@@ -4481,6 +4482,37 @@
fi
fi
+# On powerpc libgcc_s references copysignl which is a libm function but
+# glibc apparently also provides it via libc as opposed to uClibc where
+# it lives in libm.
+echo "$as_me:$LINENO: checking for library containing copysignl" >&5
+echo $ECHO_N "checking for library containing copysignl... $ECHO_C" >&6
+if test "${libgcc_cv_copysignl_lib+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+
+ echo '#include <features.h>' > conftest.c
+ echo 'int the_libc = __UCLIBC__ + __powerpc__;' >> conftest.c
+ libgcc_cv_copysignl_lib="-lc"
+ if { ac_try='${CC-cc} -S conftest.c -o conftest.s 1>&5'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }
+ then
+ libgcc_cv_copysignl_lib="-lm"
+ fi
+ rm -f conftest.*
+
+fi
+echo "$as_me:$LINENO: result: $libgcc_cv_copysignl_lib" >&5
+echo "${ECHO_T}$libgcc_cv_copysignl_lib" >&6
+
+case /${libgcc_cv_copysignl_lib}/ in
+ /-lm/) LIBGCC_LIBM="$LIBGCC_LIBM -lm" ;;
+ *) LIBGCC_LIBM= ;;
+esac
# Conditionalize the makefile for this target machine.
tmake_file_=
Index: gcc-4.8.0/libgcc/configure.ac
===================================================================
--- gcc-4.8.0.orig/libgcc/configure.ac 2012-10-15 15:10:30.000000000 +0200
+++ gcc-4.8.0/libgcc/configure.ac 2013-03-24 09:12:43.000000000 +0100
@@ -326,6 +326,27 @@
fi
AC_SUBST(set_have_cc_tls)
+# On powerpc libgcc_s references copysignl which is a libm function but
+# glibc apparently also provides it via libc as opposed to uClibc where
+# it lives in libm.
+AC_CACHE_CHECK
+ libgcc_cv_copysignl_lib,
+ echo '#include <features.h>' > conftest.c
+ echo 'int the_libc = __UCLIBC__ + __powerpc__;' >> conftest.c
+ libgcc_cv_copysignl_lib="-lc"
+ if AC_TRY_COMMAND(${CC-cc} -S conftest.c -o conftest.s 1>&AS_MESSAGE_LOG_FD)
+ then
+ libgcc_cv_copysignl_lib="-lm"
+ fi
+ rm -f conftest.*
+ ])
+
+case /${libgcc_cv_copysignl_lib}/ in
+ /-lm/) LIBGCC_LIBM="$LIBGCC_LIBM -lm" ;;
+ *) LIBGCC_LIBM= ;;
+esac
+AC_SUBST(LIBGCC_LIBM)
+
# See if we have emulated thread-local storage.
GCC_CHECK_EMUTLS
set_use_emutls=
|
{
"language": "Assembly"
}
|
// Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build go1.11,!gccgo,!purego
#include "textflag.h"
#define NUM_ROUNDS 10
// func xorKeyStreamVX(dst, src []byte, key *[8]uint32, nonce *[3]uint32, counter *uint32)
TEXT ·xorKeyStreamVX(SB), NOSPLIT, $0
MOVD dst+0(FP), R1
MOVD src+24(FP), R2
MOVD src_len+32(FP), R3
MOVD key+48(FP), R4
MOVD nonce+56(FP), R6
MOVD counter+64(FP), R7
MOVD $·constants(SB), R10
MOVD $·incRotMatrix(SB), R11
MOVW (R7), R20
AND $~255, R3, R13
ADD R2, R13, R12 // R12 for block end
AND $255, R3, R13
loop:
MOVD $NUM_ROUNDS, R21
VLD1 (R11), [V30.S4, V31.S4]
// load contants
// VLD4R (R10), [V0.S4, V1.S4, V2.S4, V3.S4]
WORD $0x4D60E940
// load keys
// VLD4R 16(R4), [V4.S4, V5.S4, V6.S4, V7.S4]
WORD $0x4DFFE884
// VLD4R 16(R4), [V8.S4, V9.S4, V10.S4, V11.S4]
WORD $0x4DFFE888
SUB $32, R4
// load counter + nonce
// VLD1R (R7), [V12.S4]
WORD $0x4D40C8EC
// VLD3R (R6), [V13.S4, V14.S4, V15.S4]
WORD $0x4D40E8CD
// update counter
VADD V30.S4, V12.S4, V12.S4
chacha:
// V0..V3 += V4..V7
// V12..V15 <<<= ((V12..V15 XOR V0..V3), 16)
VADD V0.S4, V4.S4, V0.S4
VADD V1.S4, V5.S4, V1.S4
VADD V2.S4, V6.S4, V2.S4
VADD V3.S4, V7.S4, V3.S4
VEOR V12.B16, V0.B16, V12.B16
VEOR V13.B16, V1.B16, V13.B16
VEOR V14.B16, V2.B16, V14.B16
VEOR V15.B16, V3.B16, V15.B16
VREV32 V12.H8, V12.H8
VREV32 V13.H8, V13.H8
VREV32 V14.H8, V14.H8
VREV32 V15.H8, V15.H8
// V8..V11 += V12..V15
// V4..V7 <<<= ((V4..V7 XOR V8..V11), 12)
VADD V8.S4, V12.S4, V8.S4
VADD V9.S4, V13.S4, V9.S4
VADD V10.S4, V14.S4, V10.S4
VADD V11.S4, V15.S4, V11.S4
VEOR V8.B16, V4.B16, V16.B16
VEOR V9.B16, V5.B16, V17.B16
VEOR V10.B16, V6.B16, V18.B16
VEOR V11.B16, V7.B16, V19.B16
VSHL $12, V16.S4, V4.S4
VSHL $12, V17.S4, V5.S4
VSHL $12, V18.S4, V6.S4
VSHL $12, V19.S4, V7.S4
VSRI $20, V16.S4, V4.S4
VSRI $20, V17.S4, V5.S4
VSRI $20, V18.S4, V6.S4
VSRI $20, V19.S4, V7.S4
// V0..V3 += V4..V7
// V12..V15 <<<= ((V12..V15 XOR V0..V3), 8)
VADD V0.S4, V4.S4, V0.S4
VADD V1.S4, V5.S4, V1.S4
VADD V2.S4, V6.S4, V2.S4
VADD V3.S4, V7.S4, V3.S4
VEOR V12.B16, V0.B16, V12.B16
VEOR V13.B16, V1.B16, V13.B16
VEOR V14.B16, V2.B16, V14.B16
VEOR V15.B16, V3.B16, V15.B16
VTBL V31.B16, [V12.B16], V12.B16
VTBL V31.B16, [V13.B16], V13.B16
VTBL V31.B16, [V14.B16], V14.B16
VTBL V31.B16, [V15.B16], V15.B16
// V8..V11 += V12..V15
// V4..V7 <<<= ((V4..V7 XOR V8..V11), 7)
VADD V12.S4, V8.S4, V8.S4
VADD V13.S4, V9.S4, V9.S4
VADD V14.S4, V10.S4, V10.S4
VADD V15.S4, V11.S4, V11.S4
VEOR V8.B16, V4.B16, V16.B16
VEOR V9.B16, V5.B16, V17.B16
VEOR V10.B16, V6.B16, V18.B16
VEOR V11.B16, V7.B16, V19.B16
VSHL $7, V16.S4, V4.S4
VSHL $7, V17.S4, V5.S4
VSHL $7, V18.S4, V6.S4
VSHL $7, V19.S4, V7.S4
VSRI $25, V16.S4, V4.S4
VSRI $25, V17.S4, V5.S4
VSRI $25, V18.S4, V6.S4
VSRI $25, V19.S4, V7.S4
// V0..V3 += V5..V7, V4
// V15,V12-V14 <<<= ((V15,V12-V14 XOR V0..V3), 16)
VADD V0.S4, V5.S4, V0.S4
VADD V1.S4, V6.S4, V1.S4
VADD V2.S4, V7.S4, V2.S4
VADD V3.S4, V4.S4, V3.S4
VEOR V15.B16, V0.B16, V15.B16
VEOR V12.B16, V1.B16, V12.B16
VEOR V13.B16, V2.B16, V13.B16
VEOR V14.B16, V3.B16, V14.B16
VREV32 V12.H8, V12.H8
VREV32 V13.H8, V13.H8
VREV32 V14.H8, V14.H8
VREV32 V15.H8, V15.H8
// V10 += V15; V5 <<<= ((V10 XOR V5), 12)
// ...
VADD V15.S4, V10.S4, V10.S4
VADD V12.S4, V11.S4, V11.S4
VADD V13.S4, V8.S4, V8.S4
VADD V14.S4, V9.S4, V9.S4
VEOR V10.B16, V5.B16, V16.B16
VEOR V11.B16, V6.B16, V17.B16
VEOR V8.B16, V7.B16, V18.B16
VEOR V9.B16, V4.B16, V19.B16
VSHL $12, V16.S4, V5.S4
VSHL $12, V17.S4, V6.S4
VSHL $12, V18.S4, V7.S4
VSHL $12, V19.S4, V4.S4
VSRI $20, V16.S4, V5.S4
VSRI $20, V17.S4, V6.S4
VSRI $20, V18.S4, V7.S4
VSRI $20, V19.S4, V4.S4
// V0 += V5; V15 <<<= ((V0 XOR V15), 8)
// ...
VADD V5.S4, V0.S4, V0.S4
VADD V6.S4, V1.S4, V1.S4
VADD V7.S4, V2.S4, V2.S4
VADD V4.S4, V3.S4, V3.S4
VEOR V0.B16, V15.B16, V15.B16
VEOR V1.B16, V12.B16, V12.B16
VEOR V2.B16, V13.B16, V13.B16
VEOR V3.B16, V14.B16, V14.B16
VTBL V31.B16, [V12.B16], V12.B16
VTBL V31.B16, [V13.B16], V13.B16
VTBL V31.B16, [V14.B16], V14.B16
VTBL V31.B16, [V15.B16], V15.B16
// V10 += V15; V5 <<<= ((V10 XOR V5), 7)
// ...
VADD V15.S4, V10.S4, V10.S4
VADD V12.S4, V11.S4, V11.S4
VADD V13.S4, V8.S4, V8.S4
VADD V14.S4, V9.S4, V9.S4
VEOR V10.B16, V5.B16, V16.B16
VEOR V11.B16, V6.B16, V17.B16
VEOR V8.B16, V7.B16, V18.B16
VEOR V9.B16, V4.B16, V19.B16
VSHL $7, V16.S4, V5.S4
VSHL $7, V17.S4, V6.S4
VSHL $7, V18.S4, V7.S4
VSHL $7, V19.S4, V4.S4
VSRI $25, V16.S4, V5.S4
VSRI $25, V17.S4, V6.S4
VSRI $25, V18.S4, V7.S4
VSRI $25, V19.S4, V4.S4
SUB $1, R21
CBNZ R21, chacha
// VLD4R (R10), [V16.S4, V17.S4, V18.S4, V19.S4]
WORD $0x4D60E950
// VLD4R 16(R4), [V20.S4, V21.S4, V22.S4, V23.S4]
WORD $0x4DFFE894
VADD V30.S4, V12.S4, V12.S4
VADD V16.S4, V0.S4, V0.S4
VADD V17.S4, V1.S4, V1.S4
VADD V18.S4, V2.S4, V2.S4
VADD V19.S4, V3.S4, V3.S4
// VLD4R 16(R4), [V24.S4, V25.S4, V26.S4, V27.S4]
WORD $0x4DFFE898
// restore R4
SUB $32, R4
// load counter + nonce
// VLD1R (R7), [V28.S4]
WORD $0x4D40C8FC
// VLD3R (R6), [V29.S4, V30.S4, V31.S4]
WORD $0x4D40E8DD
VADD V20.S4, V4.S4, V4.S4
VADD V21.S4, V5.S4, V5.S4
VADD V22.S4, V6.S4, V6.S4
VADD V23.S4, V7.S4, V7.S4
VADD V24.S4, V8.S4, V8.S4
VADD V25.S4, V9.S4, V9.S4
VADD V26.S4, V10.S4, V10.S4
VADD V27.S4, V11.S4, V11.S4
VADD V28.S4, V12.S4, V12.S4
VADD V29.S4, V13.S4, V13.S4
VADD V30.S4, V14.S4, V14.S4
VADD V31.S4, V15.S4, V15.S4
VZIP1 V1.S4, V0.S4, V16.S4
VZIP2 V1.S4, V0.S4, V17.S4
VZIP1 V3.S4, V2.S4, V18.S4
VZIP2 V3.S4, V2.S4, V19.S4
VZIP1 V5.S4, V4.S4, V20.S4
VZIP2 V5.S4, V4.S4, V21.S4
VZIP1 V7.S4, V6.S4, V22.S4
VZIP2 V7.S4, V6.S4, V23.S4
VZIP1 V9.S4, V8.S4, V24.S4
VZIP2 V9.S4, V8.S4, V25.S4
VZIP1 V11.S4, V10.S4, V26.S4
VZIP2 V11.S4, V10.S4, V27.S4
VZIP1 V13.S4, V12.S4, V28.S4
VZIP2 V13.S4, V12.S4, V29.S4
VZIP1 V15.S4, V14.S4, V30.S4
VZIP2 V15.S4, V14.S4, V31.S4
VZIP1 V18.D2, V16.D2, V0.D2
VZIP2 V18.D2, V16.D2, V4.D2
VZIP1 V19.D2, V17.D2, V8.D2
VZIP2 V19.D2, V17.D2, V12.D2
VLD1.P 64(R2), [V16.B16, V17.B16, V18.B16, V19.B16]
VZIP1 V22.D2, V20.D2, V1.D2
VZIP2 V22.D2, V20.D2, V5.D2
VZIP1 V23.D2, V21.D2, V9.D2
VZIP2 V23.D2, V21.D2, V13.D2
VLD1.P 64(R2), [V20.B16, V21.B16, V22.B16, V23.B16]
VZIP1 V26.D2, V24.D2, V2.D2
VZIP2 V26.D2, V24.D2, V6.D2
VZIP1 V27.D2, V25.D2, V10.D2
VZIP2 V27.D2, V25.D2, V14.D2
VLD1.P 64(R2), [V24.B16, V25.B16, V26.B16, V27.B16]
VZIP1 V30.D2, V28.D2, V3.D2
VZIP2 V30.D2, V28.D2, V7.D2
VZIP1 V31.D2, V29.D2, V11.D2
VZIP2 V31.D2, V29.D2, V15.D2
VLD1.P 64(R2), [V28.B16, V29.B16, V30.B16, V31.B16]
VEOR V0.B16, V16.B16, V16.B16
VEOR V1.B16, V17.B16, V17.B16
VEOR V2.B16, V18.B16, V18.B16
VEOR V3.B16, V19.B16, V19.B16
VST1.P [V16.B16, V17.B16, V18.B16, V19.B16], 64(R1)
VEOR V4.B16, V20.B16, V20.B16
VEOR V5.B16, V21.B16, V21.B16
VEOR V6.B16, V22.B16, V22.B16
VEOR V7.B16, V23.B16, V23.B16
VST1.P [V20.B16, V21.B16, V22.B16, V23.B16], 64(R1)
VEOR V8.B16, V24.B16, V24.B16
VEOR V9.B16, V25.B16, V25.B16
VEOR V10.B16, V26.B16, V26.B16
VEOR V11.B16, V27.B16, V27.B16
VST1.P [V24.B16, V25.B16, V26.B16, V27.B16], 64(R1)
VEOR V12.B16, V28.B16, V28.B16
VEOR V13.B16, V29.B16, V29.B16
VEOR V14.B16, V30.B16, V30.B16
VEOR V15.B16, V31.B16, V31.B16
VST1.P [V28.B16, V29.B16, V30.B16, V31.B16], 64(R1)
ADD $4, R20
MOVW R20, (R7) // update counter
CMP R2, R12
BGT loop
RET
DATA ·constants+0x00(SB)/4, $0x61707865
DATA ·constants+0x04(SB)/4, $0x3320646e
DATA ·constants+0x08(SB)/4, $0x79622d32
DATA ·constants+0x0c(SB)/4, $0x6b206574
GLOBL ·constants(SB), NOPTR|RODATA, $32
DATA ·incRotMatrix+0x00(SB)/4, $0x00000000
DATA ·incRotMatrix+0x04(SB)/4, $0x00000001
DATA ·incRotMatrix+0x08(SB)/4, $0x00000002
DATA ·incRotMatrix+0x0c(SB)/4, $0x00000003
DATA ·incRotMatrix+0x10(SB)/4, $0x02010003
DATA ·incRotMatrix+0x14(SB)/4, $0x06050407
DATA ·incRotMatrix+0x18(SB)/4, $0x0A09080B
DATA ·incRotMatrix+0x1c(SB)/4, $0x0E0D0C0F
GLOBL ·incRotMatrix(SB), NOPTR|RODATA, $32
|
{
"language": "Assembly"
}
|
/* RUN: %clang_cc1 -fsyntax-only -verify %s
* expected-no-diagnostics */
# define XRECORD(x, c_name) e##c (x, __LINE__)
int ec(int, int);
void x() {
XRECORD (XRECORD (1, 1), 1);
}
|
{
"language": "Assembly"
}
|
/**
******************************************************************************
* @file startup_stm32.S
* @author MCD Application Team
* @version V2.0.0
* @date 18-February-2014
* @brief STM32Fxxxxx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4/M7 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
/*bl __libc_init_array*/
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M4/M7. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* CRYP crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word DSIHOST_IRQHandler /* DSI host */
.word DFSDM1_FLT0_IRQHandler /* DFSDM1 filter 0 */
.word DFSDM1_FLT1_IRQHandler /* DFSDM1 filter 1 */
.word DFSDM1_FLT2_IRQHandler /* DFSDM1 filter 2 */
.word DFSDM1_FLT3_IRQHandler /* DFSDM1 filter 3 */
.word SDMMC2_IRQHandler /* SDMMC2 */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak DSIHOST_IRQHandler
.thumb_set DSIHOST_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
{
"language": "Assembly"
}
|
#ifndef CAPSTONE_X86_H
#define CAPSTONE_X86_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
// Calculate relative address for X86-64, given cs_insn structure
#define X86_REL_ADDR(insn) (((insn).detail->x86.operands[0].type == X86_OP_IMM) \
? (uint64_t)((insn).detail->x86.operands[0].imm) \
: (((insn).address + (insn).size) + (uint64_t)(insn).detail->x86.disp))
//> X86 registers
typedef enum x86_reg {
X86_REG_INVALID = 0,
X86_REG_AH, X86_REG_AL, X86_REG_AX, X86_REG_BH, X86_REG_BL,
X86_REG_BP, X86_REG_BPL, X86_REG_BX, X86_REG_CH, X86_REG_CL,
X86_REG_CS, X86_REG_CX, X86_REG_DH, X86_REG_DI, X86_REG_DIL,
X86_REG_DL, X86_REG_DS, X86_REG_DX, X86_REG_EAX, X86_REG_EBP,
X86_REG_EBX, X86_REG_ECX, X86_REG_EDI, X86_REG_EDX, X86_REG_EFLAGS,
X86_REG_EIP, X86_REG_EIZ, X86_REG_ES, X86_REG_ESI, X86_REG_ESP,
X86_REG_FPSW, X86_REG_FS, X86_REG_GS, X86_REG_IP, X86_REG_RAX,
X86_REG_RBP, X86_REG_RBX, X86_REG_RCX, X86_REG_RDI, X86_REG_RDX,
X86_REG_RIP, X86_REG_RIZ, X86_REG_RSI, X86_REG_RSP, X86_REG_SI,
X86_REG_SIL, X86_REG_SP, X86_REG_SPL, X86_REG_SS, X86_REG_CR0,
X86_REG_CR1, X86_REG_CR2, X86_REG_CR3, X86_REG_CR4, X86_REG_CR5,
X86_REG_CR6, X86_REG_CR7, X86_REG_CR8, X86_REG_CR9, X86_REG_CR10,
X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15,
X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4,
X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_FP0, X86_REG_FP1,
X86_REG_FP2, X86_REG_FP3, X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7,
X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4,
X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1,
X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6,
X86_REG_MM7, X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
X86_REG_ST0, X86_REG_ST1, X86_REG_ST2, X86_REG_ST3,
X86_REG_ST4, X86_REG_ST5, X86_REG_ST6, X86_REG_ST7,
X86_REG_XMM0, X86_REG_XMM1, X86_REG_XMM2, X86_REG_XMM3, X86_REG_XMM4,
X86_REG_XMM5, X86_REG_XMM6, X86_REG_XMM7, X86_REG_XMM8, X86_REG_XMM9,
X86_REG_XMM10, X86_REG_XMM11, X86_REG_XMM12, X86_REG_XMM13, X86_REG_XMM14,
X86_REG_XMM15, X86_REG_XMM16, X86_REG_XMM17, X86_REG_XMM18, X86_REG_XMM19,
X86_REG_XMM20, X86_REG_XMM21, X86_REG_XMM22, X86_REG_XMM23, X86_REG_XMM24,
X86_REG_XMM25, X86_REG_XMM26, X86_REG_XMM27, X86_REG_XMM28, X86_REG_XMM29,
X86_REG_XMM30, X86_REG_XMM31, X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2,
X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7,
X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12,
X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, X86_REG_YMM16, X86_REG_YMM17,
X86_REG_YMM18, X86_REG_YMM19, X86_REG_YMM20, X86_REG_YMM21, X86_REG_YMM22,
X86_REG_YMM23, X86_REG_YMM24, X86_REG_YMM25, X86_REG_YMM26, X86_REG_YMM27,
X86_REG_YMM28, X86_REG_YMM29, X86_REG_YMM30, X86_REG_YMM31, X86_REG_ZMM0,
X86_REG_ZMM1, X86_REG_ZMM2, X86_REG_ZMM3, X86_REG_ZMM4, X86_REG_ZMM5,
X86_REG_ZMM6, X86_REG_ZMM7, X86_REG_ZMM8, X86_REG_ZMM9, X86_REG_ZMM10,
X86_REG_ZMM11, X86_REG_ZMM12, X86_REG_ZMM13, X86_REG_ZMM14, X86_REG_ZMM15,
X86_REG_ZMM16, X86_REG_ZMM17, X86_REG_ZMM18, X86_REG_ZMM19, X86_REG_ZMM20,
X86_REG_ZMM21, X86_REG_ZMM22, X86_REG_ZMM23, X86_REG_ZMM24, X86_REG_ZMM25,
X86_REG_ZMM26, X86_REG_ZMM27, X86_REG_ZMM28, X86_REG_ZMM29, X86_REG_ZMM30,
X86_REG_ZMM31, X86_REG_R8B, X86_REG_R9B, X86_REG_R10B, X86_REG_R11B,
X86_REG_R12B, X86_REG_R13B, X86_REG_R14B, X86_REG_R15B, X86_REG_R8D,
X86_REG_R9D, X86_REG_R10D, X86_REG_R11D, X86_REG_R12D, X86_REG_R13D,
X86_REG_R14D, X86_REG_R15D, X86_REG_R8W, X86_REG_R9W, X86_REG_R10W,
X86_REG_R11W, X86_REG_R12W, X86_REG_R13W, X86_REG_R14W, X86_REG_R15W,
X86_REG_ENDING // <-- mark the end of the list of registers
} x86_reg;
//> Operand type for instruction's operands
typedef enum x86_op_type {
X86_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
X86_OP_REG, // = CS_OP_REG (Register operand).
X86_OP_IMM, // = CS_OP_IMM (Immediate operand).
X86_OP_MEM, // = CS_OP_MEM (Memory operand).
X86_OP_FP, // = CS_OP_FP (Floating-Point operand).
} x86_op_type;
//> AVX broadcast type
typedef enum x86_avx_bcast {
X86_AVX_BCAST_INVALID = 0, // Uninitialized.
X86_AVX_BCAST_2, // AVX512 broadcast type {1to2}
X86_AVX_BCAST_4, // AVX512 broadcast type {1to4}
X86_AVX_BCAST_8, // AVX512 broadcast type {1to8}
X86_AVX_BCAST_16, // AVX512 broadcast type {1to16}
} x86_avx_bcast;
//> SSE Code Condition type
typedef enum x86_sse_cc {
X86_SSE_CC_INVALID = 0, // Uninitialized.
X86_SSE_CC_EQ,
X86_SSE_CC_LT,
X86_SSE_CC_LE,
X86_SSE_CC_UNORD,
X86_SSE_CC_NEQ,
X86_SSE_CC_NLT,
X86_SSE_CC_NLE,
X86_SSE_CC_ORD,
X86_SSE_CC_EQ_UQ,
X86_SSE_CC_NGE,
X86_SSE_CC_NGT,
X86_SSE_CC_FALSE,
X86_SSE_CC_NEQ_OQ,
X86_SSE_CC_GE,
X86_SSE_CC_GT,
X86_SSE_CC_TRUE,
} x86_sse_cc;
//> AVX Code Condition type
typedef enum x86_avx_cc {
X86_AVX_CC_INVALID = 0, // Uninitialized.
X86_AVX_CC_EQ,
X86_AVX_CC_LT,
X86_AVX_CC_LE,
X86_AVX_CC_UNORD,
X86_AVX_CC_NEQ,
X86_AVX_CC_NLT,
X86_AVX_CC_NLE,
X86_AVX_CC_ORD,
X86_AVX_CC_EQ_UQ,
X86_AVX_CC_NGE,
X86_AVX_CC_NGT,
X86_AVX_CC_FALSE,
X86_AVX_CC_NEQ_OQ,
X86_AVX_CC_GE,
X86_AVX_CC_GT,
X86_AVX_CC_TRUE,
X86_AVX_CC_EQ_OS,
X86_AVX_CC_LT_OQ,
X86_AVX_CC_LE_OQ,
X86_AVX_CC_UNORD_S,
X86_AVX_CC_NEQ_US,
X86_AVX_CC_NLT_UQ,
X86_AVX_CC_NLE_UQ,
X86_AVX_CC_ORD_S,
X86_AVX_CC_EQ_US,
X86_AVX_CC_NGE_UQ,
X86_AVX_CC_NGT_UQ,
X86_AVX_CC_FALSE_OS,
X86_AVX_CC_NEQ_OS,
X86_AVX_CC_GE_OQ,
X86_AVX_CC_GT_OQ,
X86_AVX_CC_TRUE_US,
} x86_avx_cc;
//> AVX static rounding mode type
typedef enum x86_avx_rm {
X86_AVX_RM_INVALID = 0, // Uninitialized.
X86_AVX_RM_RN, // Round to nearest
X86_AVX_RM_RD, // Round down
X86_AVX_RM_RU, // Round up
X86_AVX_RM_RZ, // Round toward zero
} x86_avx_rm;
//> Instruction prefixes - to be used in cs_x86.prefix[]
typedef enum x86_prefix {
X86_PREFIX_LOCK = 0xf0, // lock (cs_x86.prefix[0]
X86_PREFIX_REP = 0xf3, // rep (cs_x86.prefix[0]
X86_PREFIX_REPNE = 0xf2, // repne (cs_x86.prefix[0]
X86_PREFIX_CS = 0x2e, // segment override CS (cs_x86.prefix[1]
X86_PREFIX_SS = 0x36, // segment override SS (cs_x86.prefix[1]
X86_PREFIX_DS = 0x3e, // segment override DS (cs_x86.prefix[1]
X86_PREFIX_ES = 0x26, // segment override ES (cs_x86.prefix[1]
X86_PREFIX_FS = 0x64, // segment override FS (cs_x86.prefix[1]
X86_PREFIX_GS = 0x65, // segment override GS (cs_x86.prefix[1]
X86_PREFIX_OPSIZE = 0x66, // operand-size override (cs_x86.prefix[2]
X86_PREFIX_ADDRSIZE = 0x67, // address-size override (cs_x86.prefix[3]
} x86_prefix;
// Instruction's operand referring to memory
// This is associated with X86_OP_MEM operand type above
typedef struct x86_op_mem {
unsigned int segment; // segment register (or X86_REG_INVALID if irrelevant)
unsigned int base; // base register (or X86_REG_INVALID if irrelevant)
unsigned int index; // index register (or X86_REG_INVALID if irrelevant)
int scale; // scale for index register
int64_t disp; // displacement value
} x86_op_mem;
// Instruction operand
typedef struct cs_x86_op {
x86_op_type type; // operand type
union {
x86_reg reg; // register value for REG operand
int64_t imm; // immediate value for IMM operand
double fp; // floating point value for FP operand
x86_op_mem mem; // base/index/scale/disp value for MEM operand
};
// size of this operand (in bytes).
uint8_t size;
// AVX broadcast type, or 0 if irrelevant
x86_avx_bcast avx_bcast;
// AVX zero opmask {z}
bool avx_zero_opmask;
} cs_x86_op;
// Instruction structure
typedef struct cs_x86 {
// Instruction prefix, which can be up to 4 bytes.
// A prefix byte gets value 0 when irrelevant.
// prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)
// prefix[1] indicates segment override (irrelevant for x86_64):
// See X86_PREFIX_CS/SS/DS/ES/FS/GS above.
// prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)
// prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)
uint8_t prefix[4];
// Instruction opcode, which can be from 1 to 4 bytes in size.
// This contains VEX opcode as well.
// An trailing opcode byte gets value 0 when irrelevant.
uint8_t opcode[4];
// REX prefix: only a non-zero value is relevant for x86_64
uint8_t rex;
// Address size, which can be overridden with above prefix[5].
uint8_t addr_size;
// ModR/M byte
uint8_t modrm;
// SIB value, or 0 when irrelevant.
uint8_t sib;
// Displacement value, or 0 when irrelevant.
int32_t disp;
/* SIB state */
// SIB index register, or X86_REG_INVALID when irrelevant.
x86_reg sib_index;
// SIB scale. only applicable if sib_index is relevant.
int8_t sib_scale;
// SIB base register, or X86_REG_INVALID when irrelevant.
x86_reg sib_base;
// SSE Code Condition
x86_sse_cc sse_cc;
// AVX Code Condition
x86_avx_cc avx_cc;
// AVX Suppress all Exception
bool avx_sae;
// AVX static rounding mode
x86_avx_rm avx_rm;
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
cs_x86_op operands[8]; // operands for this instruction.
} cs_x86;
//> X86 instructions
typedef enum x86_insn {
X86_INS_INVALID = 0,
X86_INS_AAA,
X86_INS_AAD,
X86_INS_AAM,
X86_INS_AAS,
X86_INS_FABS,
X86_INS_ADC,
X86_INS_ADCX,
X86_INS_ADD,
X86_INS_ADDPD,
X86_INS_ADDPS,
X86_INS_ADDSD,
X86_INS_ADDSS,
X86_INS_ADDSUBPD,
X86_INS_ADDSUBPS,
X86_INS_FADD,
X86_INS_FIADD,
X86_INS_FADDP,
X86_INS_ADOX,
X86_INS_AESDECLAST,
X86_INS_AESDEC,
X86_INS_AESENCLAST,
X86_INS_AESENC,
X86_INS_AESIMC,
X86_INS_AESKEYGENASSIST,
X86_INS_AND,
X86_INS_ANDN,
X86_INS_ANDNPD,
X86_INS_ANDNPS,
X86_INS_ANDPD,
X86_INS_ANDPS,
X86_INS_ARPL,
X86_INS_BEXTR,
X86_INS_BLCFILL,
X86_INS_BLCI,
X86_INS_BLCIC,
X86_INS_BLCMSK,
X86_INS_BLCS,
X86_INS_BLENDPD,
X86_INS_BLENDPS,
X86_INS_BLENDVPD,
X86_INS_BLENDVPS,
X86_INS_BLSFILL,
X86_INS_BLSI,
X86_INS_BLSIC,
X86_INS_BLSMSK,
X86_INS_BLSR,
X86_INS_BOUND,
X86_INS_BSF,
X86_INS_BSR,
X86_INS_BSWAP,
X86_INS_BT,
X86_INS_BTC,
X86_INS_BTR,
X86_INS_BTS,
X86_INS_BZHI,
X86_INS_CALL,
X86_INS_CBW,
X86_INS_CDQ,
X86_INS_CDQE,
X86_INS_FCHS,
X86_INS_CLAC,
X86_INS_CLC,
X86_INS_CLD,
X86_INS_CLFLUSH,
X86_INS_CLGI,
X86_INS_CLI,
X86_INS_CLTS,
X86_INS_CMC,
X86_INS_CMOVA,
X86_INS_CMOVAE,
X86_INS_CMOVB,
X86_INS_CMOVBE,
X86_INS_FCMOVBE,
X86_INS_FCMOVB,
X86_INS_CMOVE,
X86_INS_FCMOVE,
X86_INS_CMOVG,
X86_INS_CMOVGE,
X86_INS_CMOVL,
X86_INS_CMOVLE,
X86_INS_FCMOVNBE,
X86_INS_FCMOVNB,
X86_INS_CMOVNE,
X86_INS_FCMOVNE,
X86_INS_CMOVNO,
X86_INS_CMOVNP,
X86_INS_FCMOVNU,
X86_INS_CMOVNS,
X86_INS_CMOVO,
X86_INS_CMOVP,
X86_INS_FCMOVU,
X86_INS_CMOVS,
X86_INS_CMP,
X86_INS_CMPPD,
X86_INS_CMPPS,
X86_INS_CMPSB,
X86_INS_CMPSD,
X86_INS_CMPSQ,
X86_INS_CMPSS,
X86_INS_CMPSW,
X86_INS_CMPXCHG16B,
X86_INS_CMPXCHG,
X86_INS_CMPXCHG8B,
X86_INS_COMISD,
X86_INS_COMISS,
X86_INS_FCOMP,
X86_INS_FCOMPI,
X86_INS_FCOMI,
X86_INS_FCOM,
X86_INS_FCOS,
X86_INS_CPUID,
X86_INS_CQO,
X86_INS_CRC32,
X86_INS_CVTDQ2PD,
X86_INS_CVTDQ2PS,
X86_INS_CVTPD2DQ,
X86_INS_CVTPD2PS,
X86_INS_CVTPS2DQ,
X86_INS_CVTPS2PD,
X86_INS_CVTSD2SI,
X86_INS_CVTSD2SS,
X86_INS_CVTSI2SD,
X86_INS_CVTSI2SS,
X86_INS_CVTSS2SD,
X86_INS_CVTSS2SI,
X86_INS_CVTTPD2DQ,
X86_INS_CVTTPS2DQ,
X86_INS_CVTTSD2SI,
X86_INS_CVTTSS2SI,
X86_INS_CWD,
X86_INS_CWDE,
X86_INS_DAA,
X86_INS_DAS,
X86_INS_DATA16,
X86_INS_DEC,
X86_INS_DIV,
X86_INS_DIVPD,
X86_INS_DIVPS,
X86_INS_FDIVR,
X86_INS_FIDIVR,
X86_INS_FDIVRP,
X86_INS_DIVSD,
X86_INS_DIVSS,
X86_INS_FDIV,
X86_INS_FIDIV,
X86_INS_FDIVP,
X86_INS_DPPD,
X86_INS_DPPS,
X86_INS_RET,
X86_INS_ENCLS,
X86_INS_ENCLU,
X86_INS_ENTER,
X86_INS_EXTRACTPS,
X86_INS_EXTRQ,
X86_INS_F2XM1,
X86_INS_LCALL,
X86_INS_LJMP,
X86_INS_FBLD,
X86_INS_FBSTP,
X86_INS_FCOMPP,
X86_INS_FDECSTP,
X86_INS_FEMMS,
X86_INS_FFREE,
X86_INS_FICOM,
X86_INS_FICOMP,
X86_INS_FINCSTP,
X86_INS_FLDCW,
X86_INS_FLDENV,
X86_INS_FLDL2E,
X86_INS_FLDL2T,
X86_INS_FLDLG2,
X86_INS_FLDLN2,
X86_INS_FLDPI,
X86_INS_FNCLEX,
X86_INS_FNINIT,
X86_INS_FNOP,
X86_INS_FNSTCW,
X86_INS_FNSTSW,
X86_INS_FPATAN,
X86_INS_FPREM,
X86_INS_FPREM1,
X86_INS_FPTAN,
X86_INS_FRNDINT,
X86_INS_FRSTOR,
X86_INS_FNSAVE,
X86_INS_FSCALE,
X86_INS_FSETPM,
X86_INS_FSINCOS,
X86_INS_FNSTENV,
X86_INS_FXAM,
X86_INS_FXRSTOR,
X86_INS_FXRSTOR64,
X86_INS_FXSAVE,
X86_INS_FXSAVE64,
X86_INS_FXTRACT,
X86_INS_FYL2X,
X86_INS_FYL2XP1,
X86_INS_MOVAPD,
X86_INS_MOVAPS,
X86_INS_ORPD,
X86_INS_ORPS,
X86_INS_VMOVAPD,
X86_INS_VMOVAPS,
X86_INS_XORPD,
X86_INS_XORPS,
X86_INS_GETSEC,
X86_INS_HADDPD,
X86_INS_HADDPS,
X86_INS_HLT,
X86_INS_HSUBPD,
X86_INS_HSUBPS,
X86_INS_IDIV,
X86_INS_FILD,
X86_INS_IMUL,
X86_INS_IN,
X86_INS_INC,
X86_INS_INSB,
X86_INS_INSERTPS,
X86_INS_INSERTQ,
X86_INS_INSD,
X86_INS_INSW,
X86_INS_INT,
X86_INS_INT1,
X86_INS_INT3,
X86_INS_INTO,
X86_INS_INVD,
X86_INS_INVEPT,
X86_INS_INVLPG,
X86_INS_INVLPGA,
X86_INS_INVPCID,
X86_INS_INVVPID,
X86_INS_IRET,
X86_INS_IRETD,
X86_INS_IRETQ,
X86_INS_FISTTP,
X86_INS_FIST,
X86_INS_FISTP,
X86_INS_UCOMISD,
X86_INS_UCOMISS,
X86_INS_VCMP,
X86_INS_VCOMISD,
X86_INS_VCOMISS,
X86_INS_VCVTSD2SS,
X86_INS_VCVTSI2SD,
X86_INS_VCVTSI2SS,
X86_INS_VCVTSS2SD,
X86_INS_VCVTTSD2SI,
X86_INS_VCVTTSD2USI,
X86_INS_VCVTTSS2SI,
X86_INS_VCVTTSS2USI,
X86_INS_VCVTUSI2SD,
X86_INS_VCVTUSI2SS,
X86_INS_VUCOMISD,
X86_INS_VUCOMISS,
X86_INS_JAE,
X86_INS_JA,
X86_INS_JBE,
X86_INS_JB,
X86_INS_JCXZ,
X86_INS_JECXZ,
X86_INS_JE,
X86_INS_JGE,
X86_INS_JG,
X86_INS_JLE,
X86_INS_JL,
X86_INS_JMP,
X86_INS_JNE,
X86_INS_JNO,
X86_INS_JNP,
X86_INS_JNS,
X86_INS_JO,
X86_INS_JP,
X86_INS_JRCXZ,
X86_INS_JS,
X86_INS_KANDB,
X86_INS_KANDD,
X86_INS_KANDNB,
X86_INS_KANDND,
X86_INS_KANDNQ,
X86_INS_KANDNW,
X86_INS_KANDQ,
X86_INS_KANDW,
X86_INS_KMOVB,
X86_INS_KMOVD,
X86_INS_KMOVQ,
X86_INS_KMOVW,
X86_INS_KNOTB,
X86_INS_KNOTD,
X86_INS_KNOTQ,
X86_INS_KNOTW,
X86_INS_KORB,
X86_INS_KORD,
X86_INS_KORQ,
X86_INS_KORTESTW,
X86_INS_KORW,
X86_INS_KSHIFTLW,
X86_INS_KSHIFTRW,
X86_INS_KUNPCKBW,
X86_INS_KXNORB,
X86_INS_KXNORD,
X86_INS_KXNORQ,
X86_INS_KXNORW,
X86_INS_KXORB,
X86_INS_KXORD,
X86_INS_KXORQ,
X86_INS_KXORW,
X86_INS_LAHF,
X86_INS_LAR,
X86_INS_LDDQU,
X86_INS_LDMXCSR,
X86_INS_LDS,
X86_INS_FLDZ,
X86_INS_FLD1,
X86_INS_FLD,
X86_INS_LEA,
X86_INS_LEAVE,
X86_INS_LES,
X86_INS_LFENCE,
X86_INS_LFS,
X86_INS_LGDT,
X86_INS_LGS,
X86_INS_LIDT,
X86_INS_LLDT,
X86_INS_LMSW,
X86_INS_OR,
X86_INS_SUB,
X86_INS_XOR,
X86_INS_LODSB,
X86_INS_LODSD,
X86_INS_LODSQ,
X86_INS_LODSW,
X86_INS_LOOP,
X86_INS_LOOPE,
X86_INS_LOOPNE,
X86_INS_RETF,
X86_INS_RETFQ,
X86_INS_LSL,
X86_INS_LSS,
X86_INS_LTR,
X86_INS_XADD,
X86_INS_LZCNT,
X86_INS_MASKMOVDQU,
X86_INS_MAXPD,
X86_INS_MAXPS,
X86_INS_MAXSD,
X86_INS_MAXSS,
X86_INS_MFENCE,
X86_INS_MINPD,
X86_INS_MINPS,
X86_INS_MINSD,
X86_INS_MINSS,
X86_INS_CVTPD2PI,
X86_INS_CVTPI2PD,
X86_INS_CVTPI2PS,
X86_INS_CVTPS2PI,
X86_INS_CVTTPD2PI,
X86_INS_CVTTPS2PI,
X86_INS_EMMS,
X86_INS_MASKMOVQ,
X86_INS_MOVD,
X86_INS_MOVDQ2Q,
X86_INS_MOVNTQ,
X86_INS_MOVQ2DQ,
X86_INS_MOVQ,
X86_INS_PABSB,
X86_INS_PABSD,
X86_INS_PABSW,
X86_INS_PACKSSDW,
X86_INS_PACKSSWB,
X86_INS_PACKUSWB,
X86_INS_PADDB,
X86_INS_PADDD,
X86_INS_PADDQ,
X86_INS_PADDSB,
X86_INS_PADDSW,
X86_INS_PADDUSB,
X86_INS_PADDUSW,
X86_INS_PADDW,
X86_INS_PALIGNR,
X86_INS_PANDN,
X86_INS_PAND,
X86_INS_PAVGB,
X86_INS_PAVGW,
X86_INS_PCMPEQB,
X86_INS_PCMPEQD,
X86_INS_PCMPEQW,
X86_INS_PCMPGTB,
X86_INS_PCMPGTD,
X86_INS_PCMPGTW,
X86_INS_PEXTRW,
X86_INS_PHADDSW,
X86_INS_PHADDW,
X86_INS_PHADDD,
X86_INS_PHSUBD,
X86_INS_PHSUBSW,
X86_INS_PHSUBW,
X86_INS_PINSRW,
X86_INS_PMADDUBSW,
X86_INS_PMADDWD,
X86_INS_PMAXSW,
X86_INS_PMAXUB,
X86_INS_PMINSW,
X86_INS_PMINUB,
X86_INS_PMOVMSKB,
X86_INS_PMULHRSW,
X86_INS_PMULHUW,
X86_INS_PMULHW,
X86_INS_PMULLW,
X86_INS_PMULUDQ,
X86_INS_POR,
X86_INS_PSADBW,
X86_INS_PSHUFB,
X86_INS_PSHUFW,
X86_INS_PSIGNB,
X86_INS_PSIGND,
X86_INS_PSIGNW,
X86_INS_PSLLD,
X86_INS_PSLLQ,
X86_INS_PSLLW,
X86_INS_PSRAD,
X86_INS_PSRAW,
X86_INS_PSRLD,
X86_INS_PSRLQ,
X86_INS_PSRLW,
X86_INS_PSUBB,
X86_INS_PSUBD,
X86_INS_PSUBQ,
X86_INS_PSUBSB,
X86_INS_PSUBSW,
X86_INS_PSUBUSB,
X86_INS_PSUBUSW,
X86_INS_PSUBW,
X86_INS_PUNPCKHBW,
X86_INS_PUNPCKHDQ,
X86_INS_PUNPCKHWD,
X86_INS_PUNPCKLBW,
X86_INS_PUNPCKLDQ,
X86_INS_PUNPCKLWD,
X86_INS_PXOR,
X86_INS_MONITOR,
X86_INS_MONTMUL,
X86_INS_MOV,
X86_INS_MOVABS,
X86_INS_MOVBE,
X86_INS_MOVDDUP,
X86_INS_MOVDQA,
X86_INS_MOVDQU,
X86_INS_MOVHLPS,
X86_INS_MOVHPD,
X86_INS_MOVHPS,
X86_INS_MOVLHPS,
X86_INS_MOVLPD,
X86_INS_MOVLPS,
X86_INS_MOVMSKPD,
X86_INS_MOVMSKPS,
X86_INS_MOVNTDQA,
X86_INS_MOVNTDQ,
X86_INS_MOVNTI,
X86_INS_MOVNTPD,
X86_INS_MOVNTPS,
X86_INS_MOVNTSD,
X86_INS_MOVNTSS,
X86_INS_MOVSB,
X86_INS_MOVSD,
X86_INS_MOVSHDUP,
X86_INS_MOVSLDUP,
X86_INS_MOVSQ,
X86_INS_MOVSS,
X86_INS_MOVSW,
X86_INS_MOVSX,
X86_INS_MOVSXD,
X86_INS_MOVUPD,
X86_INS_MOVUPS,
X86_INS_MOVZX,
X86_INS_MPSADBW,
X86_INS_MUL,
X86_INS_MULPD,
X86_INS_MULPS,
X86_INS_MULSD,
X86_INS_MULSS,
X86_INS_MULX,
X86_INS_FMUL,
X86_INS_FIMUL,
X86_INS_FMULP,
X86_INS_MWAIT,
X86_INS_NEG,
X86_INS_NOP,
X86_INS_NOT,
X86_INS_OUT,
X86_INS_OUTSB,
X86_INS_OUTSD,
X86_INS_OUTSW,
X86_INS_PACKUSDW,
X86_INS_PAUSE,
X86_INS_PAVGUSB,
X86_INS_PBLENDVB,
X86_INS_PBLENDW,
X86_INS_PCLMULQDQ,
X86_INS_PCMPEQQ,
X86_INS_PCMPESTRI,
X86_INS_PCMPESTRM,
X86_INS_PCMPGTQ,
X86_INS_PCMPISTRI,
X86_INS_PCMPISTRM,
X86_INS_PDEP,
X86_INS_PEXT,
X86_INS_PEXTRB,
X86_INS_PEXTRD,
X86_INS_PEXTRQ,
X86_INS_PF2ID,
X86_INS_PF2IW,
X86_INS_PFACC,
X86_INS_PFADD,
X86_INS_PFCMPEQ,
X86_INS_PFCMPGE,
X86_INS_PFCMPGT,
X86_INS_PFMAX,
X86_INS_PFMIN,
X86_INS_PFMUL,
X86_INS_PFNACC,
X86_INS_PFPNACC,
X86_INS_PFRCPIT1,
X86_INS_PFRCPIT2,
X86_INS_PFRCP,
X86_INS_PFRSQIT1,
X86_INS_PFRSQRT,
X86_INS_PFSUBR,
X86_INS_PFSUB,
X86_INS_PHMINPOSUW,
X86_INS_PI2FD,
X86_INS_PI2FW,
X86_INS_PINSRB,
X86_INS_PINSRD,
X86_INS_PINSRQ,
X86_INS_PMAXSB,
X86_INS_PMAXSD,
X86_INS_PMAXUD,
X86_INS_PMAXUW,
X86_INS_PMINSB,
X86_INS_PMINSD,
X86_INS_PMINUD,
X86_INS_PMINUW,
X86_INS_PMOVSXBD,
X86_INS_PMOVSXBQ,
X86_INS_PMOVSXBW,
X86_INS_PMOVSXDQ,
X86_INS_PMOVSXWD,
X86_INS_PMOVSXWQ,
X86_INS_PMOVZXBD,
X86_INS_PMOVZXBQ,
X86_INS_PMOVZXBW,
X86_INS_PMOVZXDQ,
X86_INS_PMOVZXWD,
X86_INS_PMOVZXWQ,
X86_INS_PMULDQ,
X86_INS_PMULHRW,
X86_INS_PMULLD,
X86_INS_POP,
X86_INS_POPAW,
X86_INS_POPAL,
X86_INS_POPCNT,
X86_INS_POPF,
X86_INS_POPFD,
X86_INS_POPFQ,
X86_INS_PREFETCH,
X86_INS_PREFETCHNTA,
X86_INS_PREFETCHT0,
X86_INS_PREFETCHT1,
X86_INS_PREFETCHT2,
X86_INS_PREFETCHW,
X86_INS_PSHUFD,
X86_INS_PSHUFHW,
X86_INS_PSHUFLW,
X86_INS_PSLLDQ,
X86_INS_PSRLDQ,
X86_INS_PSWAPD,
X86_INS_PTEST,
X86_INS_PUNPCKHQDQ,
X86_INS_PUNPCKLQDQ,
X86_INS_PUSH,
X86_INS_PUSHAW,
X86_INS_PUSHAL,
X86_INS_PUSHF,
X86_INS_PUSHFD,
X86_INS_PUSHFQ,
X86_INS_RCL,
X86_INS_RCPPS,
X86_INS_RCPSS,
X86_INS_RCR,
X86_INS_RDFSBASE,
X86_INS_RDGSBASE,
X86_INS_RDMSR,
X86_INS_RDPMC,
X86_INS_RDRAND,
X86_INS_RDSEED,
X86_INS_RDTSC,
X86_INS_RDTSCP,
X86_INS_ROL,
X86_INS_ROR,
X86_INS_RORX,
X86_INS_ROUNDPD,
X86_INS_ROUNDPS,
X86_INS_ROUNDSD,
X86_INS_ROUNDSS,
X86_INS_RSM,
X86_INS_RSQRTPS,
X86_INS_RSQRTSS,
X86_INS_SAHF,
X86_INS_SAL,
X86_INS_SALC,
X86_INS_SAR,
X86_INS_SARX,
X86_INS_SBB,
X86_INS_SCASB,
X86_INS_SCASD,
X86_INS_SCASQ,
X86_INS_SCASW,
X86_INS_SETAE,
X86_INS_SETA,
X86_INS_SETBE,
X86_INS_SETB,
X86_INS_SETE,
X86_INS_SETGE,
X86_INS_SETG,
X86_INS_SETLE,
X86_INS_SETL,
X86_INS_SETNE,
X86_INS_SETNO,
X86_INS_SETNP,
X86_INS_SETNS,
X86_INS_SETO,
X86_INS_SETP,
X86_INS_SETS,
X86_INS_SFENCE,
X86_INS_SGDT,
X86_INS_SHA1MSG1,
X86_INS_SHA1MSG2,
X86_INS_SHA1NEXTE,
X86_INS_SHA1RNDS4,
X86_INS_SHA256MSG1,
X86_INS_SHA256MSG2,
X86_INS_SHA256RNDS2,
X86_INS_SHL,
X86_INS_SHLD,
X86_INS_SHLX,
X86_INS_SHR,
X86_INS_SHRD,
X86_INS_SHRX,
X86_INS_SHUFPD,
X86_INS_SHUFPS,
X86_INS_SIDT,
X86_INS_FSIN,
X86_INS_SKINIT,
X86_INS_SLDT,
X86_INS_SMSW,
X86_INS_SQRTPD,
X86_INS_SQRTPS,
X86_INS_SQRTSD,
X86_INS_SQRTSS,
X86_INS_FSQRT,
X86_INS_STAC,
X86_INS_STC,
X86_INS_STD,
X86_INS_STGI,
X86_INS_STI,
X86_INS_STMXCSR,
X86_INS_STOSB,
X86_INS_STOSD,
X86_INS_STOSQ,
X86_INS_STOSW,
X86_INS_STR,
X86_INS_FST,
X86_INS_FSTP,
X86_INS_FSTPNCE,
X86_INS_SUBPD,
X86_INS_SUBPS,
X86_INS_FSUBR,
X86_INS_FISUBR,
X86_INS_FSUBRP,
X86_INS_SUBSD,
X86_INS_SUBSS,
X86_INS_FSUB,
X86_INS_FISUB,
X86_INS_FSUBP,
X86_INS_SWAPGS,
X86_INS_SYSCALL,
X86_INS_SYSENTER,
X86_INS_SYSEXIT,
X86_INS_SYSRET,
X86_INS_T1MSKC,
X86_INS_TEST,
X86_INS_UD2,
X86_INS_FTST,
X86_INS_TZCNT,
X86_INS_TZMSK,
X86_INS_FUCOMPI,
X86_INS_FUCOMI,
X86_INS_FUCOMPP,
X86_INS_FUCOMP,
X86_INS_FUCOM,
X86_INS_UD2B,
X86_INS_UNPCKHPD,
X86_INS_UNPCKHPS,
X86_INS_UNPCKLPD,
X86_INS_UNPCKLPS,
X86_INS_VADDPD,
X86_INS_VADDPS,
X86_INS_VADDSD,
X86_INS_VADDSS,
X86_INS_VADDSUBPD,
X86_INS_VADDSUBPS,
X86_INS_VAESDECLAST,
X86_INS_VAESDEC,
X86_INS_VAESENCLAST,
X86_INS_VAESENC,
X86_INS_VAESIMC,
X86_INS_VAESKEYGENASSIST,
X86_INS_VALIGND,
X86_INS_VALIGNQ,
X86_INS_VANDNPD,
X86_INS_VANDNPS,
X86_INS_VANDPD,
X86_INS_VANDPS,
X86_INS_VBLENDMPD,
X86_INS_VBLENDMPS,
X86_INS_VBLENDPD,
X86_INS_VBLENDPS,
X86_INS_VBLENDVPD,
X86_INS_VBLENDVPS,
X86_INS_VBROADCASTF128,
X86_INS_VBROADCASTI128,
X86_INS_VBROADCASTI32X4,
X86_INS_VBROADCASTI64X4,
X86_INS_VBROADCASTSD,
X86_INS_VBROADCASTSS,
X86_INS_VCMPPD,
X86_INS_VCMPPS,
X86_INS_VCMPSD,
X86_INS_VCMPSS,
X86_INS_VCVTDQ2PD,
X86_INS_VCVTDQ2PS,
X86_INS_VCVTPD2DQX,
X86_INS_VCVTPD2DQ,
X86_INS_VCVTPD2PSX,
X86_INS_VCVTPD2PS,
X86_INS_VCVTPD2UDQ,
X86_INS_VCVTPH2PS,
X86_INS_VCVTPS2DQ,
X86_INS_VCVTPS2PD,
X86_INS_VCVTPS2PH,
X86_INS_VCVTPS2UDQ,
X86_INS_VCVTSD2SI,
X86_INS_VCVTSD2USI,
X86_INS_VCVTSS2SI,
X86_INS_VCVTSS2USI,
X86_INS_VCVTTPD2DQX,
X86_INS_VCVTTPD2DQ,
X86_INS_VCVTTPD2UDQ,
X86_INS_VCVTTPS2DQ,
X86_INS_VCVTTPS2UDQ,
X86_INS_VCVTUDQ2PD,
X86_INS_VCVTUDQ2PS,
X86_INS_VDIVPD,
X86_INS_VDIVPS,
X86_INS_VDIVSD,
X86_INS_VDIVSS,
X86_INS_VDPPD,
X86_INS_VDPPS,
X86_INS_VERR,
X86_INS_VERW,
X86_INS_VEXTRACTF128,
X86_INS_VEXTRACTF32X4,
X86_INS_VEXTRACTF64X4,
X86_INS_VEXTRACTI128,
X86_INS_VEXTRACTI32X4,
X86_INS_VEXTRACTI64X4,
X86_INS_VEXTRACTPS,
X86_INS_VFMADD132PD,
X86_INS_VFMADD132PS,
X86_INS_VFMADD213PD,
X86_INS_VFMADD213PS,
X86_INS_VFMADDPD,
X86_INS_VFMADD231PD,
X86_INS_VFMADDPS,
X86_INS_VFMADD231PS,
X86_INS_VFMADDSD,
X86_INS_VFMADD213SD,
X86_INS_VFMADD132SD,
X86_INS_VFMADD231SD,
X86_INS_VFMADDSS,
X86_INS_VFMADD213SS,
X86_INS_VFMADD132SS,
X86_INS_VFMADD231SS,
X86_INS_VFMADDSUB132PD,
X86_INS_VFMADDSUB132PS,
X86_INS_VFMADDSUB213PD,
X86_INS_VFMADDSUB213PS,
X86_INS_VFMADDSUBPD,
X86_INS_VFMADDSUB231PD,
X86_INS_VFMADDSUBPS,
X86_INS_VFMADDSUB231PS,
X86_INS_VFMSUB132PD,
X86_INS_VFMSUB132PS,
X86_INS_VFMSUB213PD,
X86_INS_VFMSUB213PS,
X86_INS_VFMSUBADD132PD,
X86_INS_VFMSUBADD132PS,
X86_INS_VFMSUBADD213PD,
X86_INS_VFMSUBADD213PS,
X86_INS_VFMSUBADDPD,
X86_INS_VFMSUBADD231PD,
X86_INS_VFMSUBADDPS,
X86_INS_VFMSUBADD231PS,
X86_INS_VFMSUBPD,
X86_INS_VFMSUB231PD,
X86_INS_VFMSUBPS,
X86_INS_VFMSUB231PS,
X86_INS_VFMSUBSD,
X86_INS_VFMSUB213SD,
X86_INS_VFMSUB132SD,
X86_INS_VFMSUB231SD,
X86_INS_VFMSUBSS,
X86_INS_VFMSUB213SS,
X86_INS_VFMSUB132SS,
X86_INS_VFMSUB231SS,
X86_INS_VFNMADD132PD,
X86_INS_VFNMADD132PS,
X86_INS_VFNMADD213PD,
X86_INS_VFNMADD213PS,
X86_INS_VFNMADDPD,
X86_INS_VFNMADD231PD,
X86_INS_VFNMADDPS,
X86_INS_VFNMADD231PS,
X86_INS_VFNMADDSD,
X86_INS_VFNMADD213SD,
X86_INS_VFNMADD132SD,
X86_INS_VFNMADD231SD,
X86_INS_VFNMADDSS,
X86_INS_VFNMADD213SS,
X86_INS_VFNMADD132SS,
X86_INS_VFNMADD231SS,
X86_INS_VFNMSUB132PD,
X86_INS_VFNMSUB132PS,
X86_INS_VFNMSUB213PD,
X86_INS_VFNMSUB213PS,
X86_INS_VFNMSUBPD,
X86_INS_VFNMSUB231PD,
X86_INS_VFNMSUBPS,
X86_INS_VFNMSUB231PS,
X86_INS_VFNMSUBSD,
X86_INS_VFNMSUB213SD,
X86_INS_VFNMSUB132SD,
X86_INS_VFNMSUB231SD,
X86_INS_VFNMSUBSS,
X86_INS_VFNMSUB213SS,
X86_INS_VFNMSUB132SS,
X86_INS_VFNMSUB231SS,
X86_INS_VFRCZPD,
X86_INS_VFRCZPS,
X86_INS_VFRCZSD,
X86_INS_VFRCZSS,
X86_INS_VORPD,
X86_INS_VORPS,
X86_INS_VXORPD,
X86_INS_VXORPS,
X86_INS_VGATHERDPD,
X86_INS_VGATHERDPS,
X86_INS_VGATHERPF0DPD,
X86_INS_VGATHERPF0DPS,
X86_INS_VGATHERPF0QPD,
X86_INS_VGATHERPF0QPS,
X86_INS_VGATHERPF1DPD,
X86_INS_VGATHERPF1DPS,
X86_INS_VGATHERPF1QPD,
X86_INS_VGATHERPF1QPS,
X86_INS_VGATHERQPD,
X86_INS_VGATHERQPS,
X86_INS_VHADDPD,
X86_INS_VHADDPS,
X86_INS_VHSUBPD,
X86_INS_VHSUBPS,
X86_INS_VINSERTF128,
X86_INS_VINSERTF32X4,
X86_INS_VINSERTF64X4,
X86_INS_VINSERTI128,
X86_INS_VINSERTI32X4,
X86_INS_VINSERTI64X4,
X86_INS_VINSERTPS,
X86_INS_VLDDQU,
X86_INS_VLDMXCSR,
X86_INS_VMASKMOVDQU,
X86_INS_VMASKMOVPD,
X86_INS_VMASKMOVPS,
X86_INS_VMAXPD,
X86_INS_VMAXPS,
X86_INS_VMAXSD,
X86_INS_VMAXSS,
X86_INS_VMCALL,
X86_INS_VMCLEAR,
X86_INS_VMFUNC,
X86_INS_VMINPD,
X86_INS_VMINPS,
X86_INS_VMINSD,
X86_INS_VMINSS,
X86_INS_VMLAUNCH,
X86_INS_VMLOAD,
X86_INS_VMMCALL,
X86_INS_VMOVQ,
X86_INS_VMOVDDUP,
X86_INS_VMOVD,
X86_INS_VMOVDQA32,
X86_INS_VMOVDQA64,
X86_INS_VMOVDQA,
X86_INS_VMOVDQU16,
X86_INS_VMOVDQU32,
X86_INS_VMOVDQU64,
X86_INS_VMOVDQU8,
X86_INS_VMOVDQU,
X86_INS_VMOVHLPS,
X86_INS_VMOVHPD,
X86_INS_VMOVHPS,
X86_INS_VMOVLHPS,
X86_INS_VMOVLPD,
X86_INS_VMOVLPS,
X86_INS_VMOVMSKPD,
X86_INS_VMOVMSKPS,
X86_INS_VMOVNTDQA,
X86_INS_VMOVNTDQ,
X86_INS_VMOVNTPD,
X86_INS_VMOVNTPS,
X86_INS_VMOVSD,
X86_INS_VMOVSHDUP,
X86_INS_VMOVSLDUP,
X86_INS_VMOVSS,
X86_INS_VMOVUPD,
X86_INS_VMOVUPS,
X86_INS_VMPSADBW,
X86_INS_VMPTRLD,
X86_INS_VMPTRST,
X86_INS_VMREAD,
X86_INS_VMRESUME,
X86_INS_VMRUN,
X86_INS_VMSAVE,
X86_INS_VMULPD,
X86_INS_VMULPS,
X86_INS_VMULSD,
X86_INS_VMULSS,
X86_INS_VMWRITE,
X86_INS_VMXOFF,
X86_INS_VMXON,
X86_INS_VPABSB,
X86_INS_VPABSD,
X86_INS_VPABSQ,
X86_INS_VPABSW,
X86_INS_VPACKSSDW,
X86_INS_VPACKSSWB,
X86_INS_VPACKUSDW,
X86_INS_VPACKUSWB,
X86_INS_VPADDB,
X86_INS_VPADDD,
X86_INS_VPADDQ,
X86_INS_VPADDSB,
X86_INS_VPADDSW,
X86_INS_VPADDUSB,
X86_INS_VPADDUSW,
X86_INS_VPADDW,
X86_INS_VPALIGNR,
X86_INS_VPANDD,
X86_INS_VPANDND,
X86_INS_VPANDNQ,
X86_INS_VPANDN,
X86_INS_VPANDQ,
X86_INS_VPAND,
X86_INS_VPAVGB,
X86_INS_VPAVGW,
X86_INS_VPBLENDD,
X86_INS_VPBLENDMD,
X86_INS_VPBLENDMQ,
X86_INS_VPBLENDVB,
X86_INS_VPBLENDW,
X86_INS_VPBROADCASTB,
X86_INS_VPBROADCASTD,
X86_INS_VPBROADCASTMB2Q,
X86_INS_VPBROADCASTMW2D,
X86_INS_VPBROADCASTQ,
X86_INS_VPBROADCASTW,
X86_INS_VPCLMULQDQ,
X86_INS_VPCMOV,
X86_INS_VPCMP,
X86_INS_VPCMPD,
X86_INS_VPCMPEQB,
X86_INS_VPCMPEQD,
X86_INS_VPCMPEQQ,
X86_INS_VPCMPEQW,
X86_INS_VPCMPESTRI,
X86_INS_VPCMPESTRM,
X86_INS_VPCMPGTB,
X86_INS_VPCMPGTD,
X86_INS_VPCMPGTQ,
X86_INS_VPCMPGTW,
X86_INS_VPCMPISTRI,
X86_INS_VPCMPISTRM,
X86_INS_VPCMPQ,
X86_INS_VPCMPUD,
X86_INS_VPCMPUQ,
X86_INS_VPCOMB,
X86_INS_VPCOMD,
X86_INS_VPCOMQ,
X86_INS_VPCOMUB,
X86_INS_VPCOMUD,
X86_INS_VPCOMUQ,
X86_INS_VPCOMUW,
X86_INS_VPCOMW,
X86_INS_VPCONFLICTD,
X86_INS_VPCONFLICTQ,
X86_INS_VPERM2F128,
X86_INS_VPERM2I128,
X86_INS_VPERMD,
X86_INS_VPERMI2D,
X86_INS_VPERMI2PD,
X86_INS_VPERMI2PS,
X86_INS_VPERMI2Q,
X86_INS_VPERMIL2PD,
X86_INS_VPERMIL2PS,
X86_INS_VPERMILPD,
X86_INS_VPERMILPS,
X86_INS_VPERMPD,
X86_INS_VPERMPS,
X86_INS_VPERMQ,
X86_INS_VPERMT2D,
X86_INS_VPERMT2PD,
X86_INS_VPERMT2PS,
X86_INS_VPERMT2Q,
X86_INS_VPEXTRB,
X86_INS_VPEXTRD,
X86_INS_VPEXTRQ,
X86_INS_VPEXTRW,
X86_INS_VPGATHERDD,
X86_INS_VPGATHERDQ,
X86_INS_VPGATHERQD,
X86_INS_VPGATHERQQ,
X86_INS_VPHADDBD,
X86_INS_VPHADDBQ,
X86_INS_VPHADDBW,
X86_INS_VPHADDDQ,
X86_INS_VPHADDD,
X86_INS_VPHADDSW,
X86_INS_VPHADDUBD,
X86_INS_VPHADDUBQ,
X86_INS_VPHADDUBW,
X86_INS_VPHADDUDQ,
X86_INS_VPHADDUWD,
X86_INS_VPHADDUWQ,
X86_INS_VPHADDWD,
X86_INS_VPHADDWQ,
X86_INS_VPHADDW,
X86_INS_VPHMINPOSUW,
X86_INS_VPHSUBBW,
X86_INS_VPHSUBDQ,
X86_INS_VPHSUBD,
X86_INS_VPHSUBSW,
X86_INS_VPHSUBWD,
X86_INS_VPHSUBW,
X86_INS_VPINSRB,
X86_INS_VPINSRD,
X86_INS_VPINSRQ,
X86_INS_VPINSRW,
X86_INS_VPLZCNTD,
X86_INS_VPLZCNTQ,
X86_INS_VPMACSDD,
X86_INS_VPMACSDQH,
X86_INS_VPMACSDQL,
X86_INS_VPMACSSDD,
X86_INS_VPMACSSDQH,
X86_INS_VPMACSSDQL,
X86_INS_VPMACSSWD,
X86_INS_VPMACSSWW,
X86_INS_VPMACSWD,
X86_INS_VPMACSWW,
X86_INS_VPMADCSSWD,
X86_INS_VPMADCSWD,
X86_INS_VPMADDUBSW,
X86_INS_VPMADDWD,
X86_INS_VPMASKMOVD,
X86_INS_VPMASKMOVQ,
X86_INS_VPMAXSB,
X86_INS_VPMAXSD,
X86_INS_VPMAXSQ,
X86_INS_VPMAXSW,
X86_INS_VPMAXUB,
X86_INS_VPMAXUD,
X86_INS_VPMAXUQ,
X86_INS_VPMAXUW,
X86_INS_VPMINSB,
X86_INS_VPMINSD,
X86_INS_VPMINSQ,
X86_INS_VPMINSW,
X86_INS_VPMINUB,
X86_INS_VPMINUD,
X86_INS_VPMINUQ,
X86_INS_VPMINUW,
X86_INS_VPMOVDB,
X86_INS_VPMOVDW,
X86_INS_VPMOVMSKB,
X86_INS_VPMOVQB,
X86_INS_VPMOVQD,
X86_INS_VPMOVQW,
X86_INS_VPMOVSDB,
X86_INS_VPMOVSDW,
X86_INS_VPMOVSQB,
X86_INS_VPMOVSQD,
X86_INS_VPMOVSQW,
X86_INS_VPMOVSXBD,
X86_INS_VPMOVSXBQ,
X86_INS_VPMOVSXBW,
X86_INS_VPMOVSXDQ,
X86_INS_VPMOVSXWD,
X86_INS_VPMOVSXWQ,
X86_INS_VPMOVUSDB,
X86_INS_VPMOVUSDW,
X86_INS_VPMOVUSQB,
X86_INS_VPMOVUSQD,
X86_INS_VPMOVUSQW,
X86_INS_VPMOVZXBD,
X86_INS_VPMOVZXBQ,
X86_INS_VPMOVZXBW,
X86_INS_VPMOVZXDQ,
X86_INS_VPMOVZXWD,
X86_INS_VPMOVZXWQ,
X86_INS_VPMULDQ,
X86_INS_VPMULHRSW,
X86_INS_VPMULHUW,
X86_INS_VPMULHW,
X86_INS_VPMULLD,
X86_INS_VPMULLW,
X86_INS_VPMULUDQ,
X86_INS_VPORD,
X86_INS_VPORQ,
X86_INS_VPOR,
X86_INS_VPPERM,
X86_INS_VPROTB,
X86_INS_VPROTD,
X86_INS_VPROTQ,
X86_INS_VPROTW,
X86_INS_VPSADBW,
X86_INS_VPSCATTERDD,
X86_INS_VPSCATTERDQ,
X86_INS_VPSCATTERQD,
X86_INS_VPSCATTERQQ,
X86_INS_VPSHAB,
X86_INS_VPSHAD,
X86_INS_VPSHAQ,
X86_INS_VPSHAW,
X86_INS_VPSHLB,
X86_INS_VPSHLD,
X86_INS_VPSHLQ,
X86_INS_VPSHLW,
X86_INS_VPSHUFB,
X86_INS_VPSHUFD,
X86_INS_VPSHUFHW,
X86_INS_VPSHUFLW,
X86_INS_VPSIGNB,
X86_INS_VPSIGND,
X86_INS_VPSIGNW,
X86_INS_VPSLLDQ,
X86_INS_VPSLLD,
X86_INS_VPSLLQ,
X86_INS_VPSLLVD,
X86_INS_VPSLLVQ,
X86_INS_VPSLLW,
X86_INS_VPSRAD,
X86_INS_VPSRAQ,
X86_INS_VPSRAVD,
X86_INS_VPSRAVQ,
X86_INS_VPSRAW,
X86_INS_VPSRLDQ,
X86_INS_VPSRLD,
X86_INS_VPSRLQ,
X86_INS_VPSRLVD,
X86_INS_VPSRLVQ,
X86_INS_VPSRLW,
X86_INS_VPSUBB,
X86_INS_VPSUBD,
X86_INS_VPSUBQ,
X86_INS_VPSUBSB,
X86_INS_VPSUBSW,
X86_INS_VPSUBUSB,
X86_INS_VPSUBUSW,
X86_INS_VPSUBW,
X86_INS_VPTESTMD,
X86_INS_VPTESTMQ,
X86_INS_VPTESTNMD,
X86_INS_VPTESTNMQ,
X86_INS_VPTEST,
X86_INS_VPUNPCKHBW,
X86_INS_VPUNPCKHDQ,
X86_INS_VPUNPCKHQDQ,
X86_INS_VPUNPCKHWD,
X86_INS_VPUNPCKLBW,
X86_INS_VPUNPCKLDQ,
X86_INS_VPUNPCKLQDQ,
X86_INS_VPUNPCKLWD,
X86_INS_VPXORD,
X86_INS_VPXORQ,
X86_INS_VPXOR,
X86_INS_VRCP14PD,
X86_INS_VRCP14PS,
X86_INS_VRCP14SD,
X86_INS_VRCP14SS,
X86_INS_VRCP28PD,
X86_INS_VRCP28PS,
X86_INS_VRCP28SD,
X86_INS_VRCP28SS,
X86_INS_VRCPPS,
X86_INS_VRCPSS,
X86_INS_VRNDSCALEPD,
X86_INS_VRNDSCALEPS,
X86_INS_VRNDSCALESD,
X86_INS_VRNDSCALESS,
X86_INS_VROUNDPD,
X86_INS_VROUNDPS,
X86_INS_VROUNDSD,
X86_INS_VROUNDSS,
X86_INS_VRSQRT14PD,
X86_INS_VRSQRT14PS,
X86_INS_VRSQRT14SD,
X86_INS_VRSQRT14SS,
X86_INS_VRSQRT28PD,
X86_INS_VRSQRT28PS,
X86_INS_VRSQRT28SD,
X86_INS_VRSQRT28SS,
X86_INS_VRSQRTPS,
X86_INS_VRSQRTSS,
X86_INS_VSCATTERDPD,
X86_INS_VSCATTERDPS,
X86_INS_VSCATTERPF0DPD,
X86_INS_VSCATTERPF0DPS,
X86_INS_VSCATTERPF0QPD,
X86_INS_VSCATTERPF0QPS,
X86_INS_VSCATTERPF1DPD,
X86_INS_VSCATTERPF1DPS,
X86_INS_VSCATTERPF1QPD,
X86_INS_VSCATTERPF1QPS,
X86_INS_VSCATTERQPD,
X86_INS_VSCATTERQPS,
X86_INS_VSHUFPD,
X86_INS_VSHUFPS,
X86_INS_VSQRTPD,
X86_INS_VSQRTPS,
X86_INS_VSQRTSD,
X86_INS_VSQRTSS,
X86_INS_VSTMXCSR,
X86_INS_VSUBPD,
X86_INS_VSUBPS,
X86_INS_VSUBSD,
X86_INS_VSUBSS,
X86_INS_VTESTPD,
X86_INS_VTESTPS,
X86_INS_VUNPCKHPD,
X86_INS_VUNPCKHPS,
X86_INS_VUNPCKLPD,
X86_INS_VUNPCKLPS,
X86_INS_VZEROALL,
X86_INS_VZEROUPPER,
X86_INS_WAIT,
X86_INS_WBINVD,
X86_INS_WRFSBASE,
X86_INS_WRGSBASE,
X86_INS_WRMSR,
X86_INS_XABORT,
X86_INS_XACQUIRE,
X86_INS_XBEGIN,
X86_INS_XCHG,
X86_INS_FXCH,
X86_INS_XCRYPTCBC,
X86_INS_XCRYPTCFB,
X86_INS_XCRYPTCTR,
X86_INS_XCRYPTECB,
X86_INS_XCRYPTOFB,
X86_INS_XEND,
X86_INS_XGETBV,
X86_INS_XLATB,
X86_INS_XRELEASE,
X86_INS_XRSTOR,
X86_INS_XRSTOR64,
X86_INS_XSAVE,
X86_INS_XSAVE64,
X86_INS_XSAVEOPT,
X86_INS_XSAVEOPT64,
X86_INS_XSETBV,
X86_INS_XSHA1,
X86_INS_XSHA256,
X86_INS_XSTORE,
X86_INS_XTEST,
X86_INS_ENDING, // mark the end of the list of insn
} x86_insn;
//> Group of X86 instructions
typedef enum x86_insn_group {
X86_GRP_INVALID = 0, // = CS_GRP_INVALID
//> Generic groups
// all jump instructions (conditional+direct+indirect jumps)
X86_GRP_JUMP, // = CS_GRP_JUMP
// all call instructions
X86_GRP_CALL, // = CS_GRP_CALL
// all return instructions
X86_GRP_RET, // = CS_GRP_RET
// all interrupt instructions (int+syscall)
X86_GRP_INT, // = CS_GRP_INT
// all interrupt return instructions
X86_GRP_IRET, // = CS_GRP_IRET
//> Architecture-specific groups
X86_GRP_VM = 128, // all virtualization instructions (VT-x + AMD-V)
X86_GRP_3DNOW,
X86_GRP_AES,
X86_GRP_ADX,
X86_GRP_AVX,
X86_GRP_AVX2,
X86_GRP_AVX512,
X86_GRP_BMI,
X86_GRP_BMI2,
X86_GRP_CMOV,
X86_GRP_F16C,
X86_GRP_FMA,
X86_GRP_FMA4,
X86_GRP_FSGSBASE,
X86_GRP_HLE,
X86_GRP_MMX,
X86_GRP_MODE32,
X86_GRP_MODE64,
X86_GRP_RTM,
X86_GRP_SHA,
X86_GRP_SSE1,
X86_GRP_SSE2,
X86_GRP_SSE3,
X86_GRP_SSE41,
X86_GRP_SSE42,
X86_GRP_SSE4A,
X86_GRP_SSSE3,
X86_GRP_PCLMUL,
X86_GRP_XOP,
X86_GRP_CDI,
X86_GRP_ERI,
X86_GRP_TBM,
X86_GRP_16BITMODE,
X86_GRP_NOT64BITMODE,
X86_GRP_SGX,
X86_GRP_DQI,
X86_GRP_BWI,
X86_GRP_PFI,
X86_GRP_VLX,
X86_GRP_SMAP,
X86_GRP_NOVLX,
X86_GRP_ENDING
} x86_insn_group;
#ifdef __cplusplus
}
#endif
#endif
|
{
"language": "Assembly"
}
|
// Tencent is pleased to support the open source community by making TNN available.
//
// Copyright (C) 2020 THL A29 Limited, a Tencent company. All rights reserved.
//
// Licensed under the BSD 3-Clause License (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
//
// https://opensource.org/licenses/BSD-3-Clause
//
// Unless required by applicable law or agreed to in writing, software distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
#ifdef __arm__
#ifndef __aarch64__
#include "tnn/device/arm/acc/compute/asm_func_name.S"
.align 5
asm_function GemmInt8Unit4x4
//void GemmInt8Unit4x4(int8_t* src, const int8_t* weight, int8_t* dst, int src_w_step, int dst_depth,
// int cdiv8, float *scale, int32_t*bias)
src .req r0
weight .req r1
dst .req r2
src_w_step .req r3
dst_depth .req r4
cdiv8 .req r5
scale .req r6
bias .req r7
push {r4, r5, r6, r7, r8, lr}
//prefetch data
//assume buffer c>=16, even c==8
vld1.8 {q12, q13}, [weight]!
vld1.8 {q14, q15}, [src]!
ldr r4, [sp, #24]
ldr r5, [sp, #28]
ldr r6, [sp, #32]
ldr r7, [sp, #36]
vpush {q4-q7}
C8Start:
subs cdiv8, cdiv8, #1
vmull.s8 q0, d28, d24
vmull.s8 q1, d30, d24
vmull.s8 q2, d28, d26
vmull.s8 q3, d30, d26
vmlal.s8 q0, d29, d25
vmlal.s8 q1, d31, d25
vrev64.32 q12, q12
vmlal.s8 q2, d29, d27
vmlal.s8 q3, d31, d27
vrev64.32 q13, q13
vpaddl.s16 q4, q0
vmull.s8 q0, d28, d24
vpaddl.s16 q5, q1
vmull.s8 q1, d30, d24
vpaddl.s16 q6, q2
vmull.s8 q2, d28, d26
vpaddl.s16 q7, q3
vmull.s8 q3, d30, d26
vmlal.s8 q0, d29, d25
vmlal.s8 q1, d31, d25
vld1.8 {q12}, [weight]!
vmlal.s8 q2, d29, d27
vmlal.s8 q3, d31, d27
vld1.8 {q13}, [weight]!
vpaddl.s16 q8, q0
vld1.8 {q14, q15}, [src]!
vpaddl.s16 q9, q1
vpaddl.s16 q10, q2
vpaddl.s16 q11, q3
beq LoopEnd
C8Loop:
subs cdiv8, cdiv8, #1
vmull.s8 q0, d28, d24
vmull.s8 q1, d30, d24
vmull.s8 q2, d28, d26
vmull.s8 q3, d30, d26
vmlal.s8 q0, d29, d25
vmlal.s8 q1, d31, d25
vrev64.32 q12, q12
vmlal.s8 q2, d29, d27
vmlal.s8 q3, d31, d27
vrev64.32 q13, q13
vpadal.s16 q4, q0
vmull.s8 q0, d28, d24
vpadal.s16 q5, q1
vmull.s8 q1, d30, d24
vpadal.s16 q6, q2
vmull.s8 q2, d28, d26
vpadal.s16 q7, q3
vmull.s8 q3, d30, d26
vmlal.s8 q0, d29, d25
vmlal.s8 q1, d31, d25
vld1.8 {q12}, [weight]!
vmlal.s8 q2, d29, d27
vmlal.s8 q3, d31, d27
vld1.8 {q13}, [weight]!
vpadal.s16 q8, q0
vpadal.s16 q9, q1
vld1.8 {q14, q15}, [src]!
vpadal.s16 q10, q2
vpadal.s16 q11, q3
bne C8Loop
LoopEnd:
//bias q14, scale q15
vld1.8 {q14}, [bias]
vld1.8 {q15}, [scale]
//q4 ~ q11 --> q4, q5
//c00, c11; c20, c31; d8 -d11
//c02, c13; c22, c33; d12-d15
//c01, c10; c21, c30 d16-d19
//c03, c12; c23, c32 d20-d23
//c00 c01, c02 c03
vpadd.s32 d0, d8, d16
vpadd.s32 d1, d12, d20
//c10 c11, c12 c13
vpadd.s32 d2, d17, d9
vpadd.s32 d3, d21, d13
//c20 c21 c22 c23
vpadd.s32 d4, d10, d18
vpadd.s32 d5, d14, d22
//c32 c31 c32 c33
vpadd.s32 d6, d19, d11
vpadd.s32 d7, d23, d15
//c0x ~ c3x
vqadd.s32 q0, q14
vqadd.s32 q1, q14
vqadd.s32 q2, q14
vqadd.s32 q3, q14
//(q2, q3 + bias) * scale --> q0, q1
vcvt.f32.s32 q0, q0
vcvt.f32.s32 q1, q1
vcvt.f32.s32 q2, q2
vcvt.f32.s32 q3, q3
vmul.f32 q12, q0, q15
vmul.f32 q13, q1, q15
vmul.f32 q4, q2, q15
vmul.f32 q5, q3, q15
//f32 --> s8
// trick: magic num 12582912.0f
ldr r0, .L4
vdup.32 q7, r0
vadd.f32 q12, q12, q7
vadd.f32 q13, q13, q7
vadd.f32 q4, q4, q7
vadd.f32 q5, q5, q7
vsub.s32 q12, q12, q7
vsub.s32 q13, q13, q7
vsub.s32 q4, q4, q7
vsub.s32 q5, q5, q7
vqmovn.s32 d0,q12
vqmovn.s32 d1,q13
vqmovn.s32 d2,q4
vqmovn.s32 d3,q5
vqmovn.s16 d4,q0
vqmovn.s16 d6,q1
vst1.s32 d4[0], [dst], dst_depth
vst1.s32 d4[1], [dst], dst_depth
vst1.s32 d6[0], [dst], dst_depth
vst1.s32 d6[1], [dst]
vpop {q4-q7}
pop {r4, r5, r6, r7, r8, pc}
.L4:
.word 0x4B400000
#endif
#endif
|
{
"language": "Assembly"
}
|
;
; Maciej 'YTM/Alliance' Witkowiak
;
; 30.10.99
; void ToBASIC (void);
.export _ToBASIC
.include "jumptab.inc"
_ToBASIC = ToBASIC
|
{
"language": "Assembly"
}
|
// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// Based on CRYPTOGAMS code with the following comment:
// # ====================================================================
// # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
// # project. The module is, however, dual licensed under OpenSSL and
// # CRYPTOGAMS licenses depending on where you obtain it. For further
// # details see http://www.openssl.org/~appro/cryptogams/.
// # ====================================================================
// Code for the perl script that generates the ppc64 assembler
// can be found in the cryptogams repository at the link below. It is based on
// the original from openssl.
// https://github.com/dot-asm/cryptogams/commit/a60f5b50ed908e91
// The differences in this and the original implementation are
// due to the calling conventions and initialization of constants.
// +build !gccgo,!purego
#include "textflag.h"
#define OUT R3
#define INP R4
#define LEN R5
#define KEY R6
#define CNT R7
#define TMP R15
#define CONSTBASE R16
#define BLOCKS R17
DATA consts<>+0x00(SB)/8, $0x3320646e61707865
DATA consts<>+0x08(SB)/8, $0x6b20657479622d32
DATA consts<>+0x10(SB)/8, $0x0000000000000001
DATA consts<>+0x18(SB)/8, $0x0000000000000000
DATA consts<>+0x20(SB)/8, $0x0000000000000004
DATA consts<>+0x28(SB)/8, $0x0000000000000000
DATA consts<>+0x30(SB)/8, $0x0a0b08090e0f0c0d
DATA consts<>+0x38(SB)/8, $0x0203000106070405
DATA consts<>+0x40(SB)/8, $0x090a0b080d0e0f0c
DATA consts<>+0x48(SB)/8, $0x0102030005060704
DATA consts<>+0x50(SB)/8, $0x6170786561707865
DATA consts<>+0x58(SB)/8, $0x6170786561707865
DATA consts<>+0x60(SB)/8, $0x3320646e3320646e
DATA consts<>+0x68(SB)/8, $0x3320646e3320646e
DATA consts<>+0x70(SB)/8, $0x79622d3279622d32
DATA consts<>+0x78(SB)/8, $0x79622d3279622d32
DATA consts<>+0x80(SB)/8, $0x6b2065746b206574
DATA consts<>+0x88(SB)/8, $0x6b2065746b206574
DATA consts<>+0x90(SB)/8, $0x0000000100000000
DATA consts<>+0x98(SB)/8, $0x0000000300000002
GLOBL consts<>(SB), RODATA, $0xa0
//func chaCha20_ctr32_vsx(out, inp *byte, len int, key *[8]uint32, counter *uint32)
TEXT ·chaCha20_ctr32_vsx(SB),NOSPLIT,$64-40
MOVD out+0(FP), OUT
MOVD inp+8(FP), INP
MOVD len+16(FP), LEN
MOVD key+24(FP), KEY
MOVD counter+32(FP), CNT
// Addressing for constants
MOVD $consts<>+0x00(SB), CONSTBASE
MOVD $16, R8
MOVD $32, R9
MOVD $48, R10
MOVD $64, R11
SRD $6, LEN, BLOCKS
// V16
LXVW4X (CONSTBASE)(R0), VS48
ADD $80,CONSTBASE
// Load key into V17,V18
LXVW4X (KEY)(R0), VS49
LXVW4X (KEY)(R8), VS50
// Load CNT, NONCE into V19
LXVW4X (CNT)(R0), VS51
// Clear V27
VXOR V27, V27, V27
// V28
LXVW4X (CONSTBASE)(R11), VS60
// splat slot from V19 -> V26
VSPLTW $0, V19, V26
VSLDOI $4, V19, V27, V19
VSLDOI $12, V27, V19, V19
VADDUWM V26, V28, V26
MOVD $10, R14
MOVD R14, CTR
loop_outer_vsx:
// V0, V1, V2, V3
LXVW4X (R0)(CONSTBASE), VS32
LXVW4X (R8)(CONSTBASE), VS33
LXVW4X (R9)(CONSTBASE), VS34
LXVW4X (R10)(CONSTBASE), VS35
// splat values from V17, V18 into V4-V11
VSPLTW $0, V17, V4
VSPLTW $1, V17, V5
VSPLTW $2, V17, V6
VSPLTW $3, V17, V7
VSPLTW $0, V18, V8
VSPLTW $1, V18, V9
VSPLTW $2, V18, V10
VSPLTW $3, V18, V11
// VOR
VOR V26, V26, V12
// splat values from V19 -> V13, V14, V15
VSPLTW $1, V19, V13
VSPLTW $2, V19, V14
VSPLTW $3, V19, V15
// splat const values
VSPLTISW $-16, V27
VSPLTISW $12, V28
VSPLTISW $8, V29
VSPLTISW $7, V30
loop_vsx:
VADDUWM V0, V4, V0
VADDUWM V1, V5, V1
VADDUWM V2, V6, V2
VADDUWM V3, V7, V3
VXOR V12, V0, V12
VXOR V13, V1, V13
VXOR V14, V2, V14
VXOR V15, V3, V15
VRLW V12, V27, V12
VRLW V13, V27, V13
VRLW V14, V27, V14
VRLW V15, V27, V15
VADDUWM V8, V12, V8
VADDUWM V9, V13, V9
VADDUWM V10, V14, V10
VADDUWM V11, V15, V11
VXOR V4, V8, V4
VXOR V5, V9, V5
VXOR V6, V10, V6
VXOR V7, V11, V7
VRLW V4, V28, V4
VRLW V5, V28, V5
VRLW V6, V28, V6
VRLW V7, V28, V7
VADDUWM V0, V4, V0
VADDUWM V1, V5, V1
VADDUWM V2, V6, V2
VADDUWM V3, V7, V3
VXOR V12, V0, V12
VXOR V13, V1, V13
VXOR V14, V2, V14
VXOR V15, V3, V15
VRLW V12, V29, V12
VRLW V13, V29, V13
VRLW V14, V29, V14
VRLW V15, V29, V15
VADDUWM V8, V12, V8
VADDUWM V9, V13, V9
VADDUWM V10, V14, V10
VADDUWM V11, V15, V11
VXOR V4, V8, V4
VXOR V5, V9, V5
VXOR V6, V10, V6
VXOR V7, V11, V7
VRLW V4, V30, V4
VRLW V5, V30, V5
VRLW V6, V30, V6
VRLW V7, V30, V7
VADDUWM V0, V5, V0
VADDUWM V1, V6, V1
VADDUWM V2, V7, V2
VADDUWM V3, V4, V3
VXOR V15, V0, V15
VXOR V12, V1, V12
VXOR V13, V2, V13
VXOR V14, V3, V14
VRLW V15, V27, V15
VRLW V12, V27, V12
VRLW V13, V27, V13
VRLW V14, V27, V14
VADDUWM V10, V15, V10
VADDUWM V11, V12, V11
VADDUWM V8, V13, V8
VADDUWM V9, V14, V9
VXOR V5, V10, V5
VXOR V6, V11, V6
VXOR V7, V8, V7
VXOR V4, V9, V4
VRLW V5, V28, V5
VRLW V6, V28, V6
VRLW V7, V28, V7
VRLW V4, V28, V4
VADDUWM V0, V5, V0
VADDUWM V1, V6, V1
VADDUWM V2, V7, V2
VADDUWM V3, V4, V3
VXOR V15, V0, V15
VXOR V12, V1, V12
VXOR V13, V2, V13
VXOR V14, V3, V14
VRLW V15, V29, V15
VRLW V12, V29, V12
VRLW V13, V29, V13
VRLW V14, V29, V14
VADDUWM V10, V15, V10
VADDUWM V11, V12, V11
VADDUWM V8, V13, V8
VADDUWM V9, V14, V9
VXOR V5, V10, V5
VXOR V6, V11, V6
VXOR V7, V8, V7
VXOR V4, V9, V4
VRLW V5, V30, V5
VRLW V6, V30, V6
VRLW V7, V30, V7
VRLW V4, V30, V4
BC 16, LT, loop_vsx
VADDUWM V12, V26, V12
WORD $0x13600F8C // VMRGEW V0, V1, V27
WORD $0x13821F8C // VMRGEW V2, V3, V28
WORD $0x10000E8C // VMRGOW V0, V1, V0
WORD $0x10421E8C // VMRGOW V2, V3, V2
WORD $0x13A42F8C // VMRGEW V4, V5, V29
WORD $0x13C63F8C // VMRGEW V6, V7, V30
XXPERMDI VS32, VS34, $0, VS33
XXPERMDI VS32, VS34, $3, VS35
XXPERMDI VS59, VS60, $0, VS32
XXPERMDI VS59, VS60, $3, VS34
WORD $0x10842E8C // VMRGOW V4, V5, V4
WORD $0x10C63E8C // VMRGOW V6, V7, V6
WORD $0x13684F8C // VMRGEW V8, V9, V27
WORD $0x138A5F8C // VMRGEW V10, V11, V28
XXPERMDI VS36, VS38, $0, VS37
XXPERMDI VS36, VS38, $3, VS39
XXPERMDI VS61, VS62, $0, VS36
XXPERMDI VS61, VS62, $3, VS38
WORD $0x11084E8C // VMRGOW V8, V9, V8
WORD $0x114A5E8C // VMRGOW V10, V11, V10
WORD $0x13AC6F8C // VMRGEW V12, V13, V29
WORD $0x13CE7F8C // VMRGEW V14, V15, V30
XXPERMDI VS40, VS42, $0, VS41
XXPERMDI VS40, VS42, $3, VS43
XXPERMDI VS59, VS60, $0, VS40
XXPERMDI VS59, VS60, $3, VS42
WORD $0x118C6E8C // VMRGOW V12, V13, V12
WORD $0x11CE7E8C // VMRGOW V14, V15, V14
VSPLTISW $4, V27
VADDUWM V26, V27, V26
XXPERMDI VS44, VS46, $0, VS45
XXPERMDI VS44, VS46, $3, VS47
XXPERMDI VS61, VS62, $0, VS44
XXPERMDI VS61, VS62, $3, VS46
VADDUWM V0, V16, V0
VADDUWM V4, V17, V4
VADDUWM V8, V18, V8
VADDUWM V12, V19, V12
CMPU LEN, $64
BLT tail_vsx
// Bottom of loop
LXVW4X (INP)(R0), VS59
LXVW4X (INP)(R8), VS60
LXVW4X (INP)(R9), VS61
LXVW4X (INP)(R10), VS62
VXOR V27, V0, V27
VXOR V28, V4, V28
VXOR V29, V8, V29
VXOR V30, V12, V30
STXVW4X VS59, (OUT)(R0)
STXVW4X VS60, (OUT)(R8)
ADD $64, INP
STXVW4X VS61, (OUT)(R9)
ADD $-64, LEN
STXVW4X VS62, (OUT)(R10)
ADD $64, OUT
BEQ done_vsx
VADDUWM V1, V16, V0
VADDUWM V5, V17, V4
VADDUWM V9, V18, V8
VADDUWM V13, V19, V12
CMPU LEN, $64
BLT tail_vsx
LXVW4X (INP)(R0), VS59
LXVW4X (INP)(R8), VS60
LXVW4X (INP)(R9), VS61
LXVW4X (INP)(R10), VS62
VXOR V27, V0, V27
VXOR V28, V4, V28
VXOR V29, V8, V29
VXOR V30, V12, V30
STXVW4X VS59, (OUT)(R0)
STXVW4X VS60, (OUT)(R8)
ADD $64, INP
STXVW4X VS61, (OUT)(R9)
ADD $-64, LEN
STXVW4X VS62, (OUT)(V10)
ADD $64, OUT
BEQ done_vsx
VADDUWM V2, V16, V0
VADDUWM V6, V17, V4
VADDUWM V10, V18, V8
VADDUWM V14, V19, V12
CMPU LEN, $64
BLT tail_vsx
LXVW4X (INP)(R0), VS59
LXVW4X (INP)(R8), VS60
LXVW4X (INP)(R9), VS61
LXVW4X (INP)(R10), VS62
VXOR V27, V0, V27
VXOR V28, V4, V28
VXOR V29, V8, V29
VXOR V30, V12, V30
STXVW4X VS59, (OUT)(R0)
STXVW4X VS60, (OUT)(R8)
ADD $64, INP
STXVW4X VS61, (OUT)(R9)
ADD $-64, LEN
STXVW4X VS62, (OUT)(R10)
ADD $64, OUT
BEQ done_vsx
VADDUWM V3, V16, V0
VADDUWM V7, V17, V4
VADDUWM V11, V18, V8
VADDUWM V15, V19, V12
CMPU LEN, $64
BLT tail_vsx
LXVW4X (INP)(R0), VS59
LXVW4X (INP)(R8), VS60
LXVW4X (INP)(R9), VS61
LXVW4X (INP)(R10), VS62
VXOR V27, V0, V27
VXOR V28, V4, V28
VXOR V29, V8, V29
VXOR V30, V12, V30
STXVW4X VS59, (OUT)(R0)
STXVW4X VS60, (OUT)(R8)
ADD $64, INP
STXVW4X VS61, (OUT)(R9)
ADD $-64, LEN
STXVW4X VS62, (OUT)(R10)
ADD $64, OUT
MOVD $10, R14
MOVD R14, CTR
BNE loop_outer_vsx
done_vsx:
// Increment counter by number of 64 byte blocks
MOVD (CNT), R14
ADD BLOCKS, R14
MOVD R14, (CNT)
RET
tail_vsx:
ADD $32, R1, R11
MOVD LEN, CTR
// Save values on stack to copy from
STXVW4X VS32, (R11)(R0)
STXVW4X VS36, (R11)(R8)
STXVW4X VS40, (R11)(R9)
STXVW4X VS44, (R11)(R10)
ADD $-1, R11, R12
ADD $-1, INP
ADD $-1, OUT
looptail_vsx:
// Copying the result to OUT
// in bytes.
MOVBZU 1(R12), KEY
MOVBZU 1(INP), TMP
XOR KEY, TMP, KEY
MOVBU KEY, 1(OUT)
BC 16, LT, looptail_vsx
// Clear the stack values
STXVW4X VS48, (R11)(R0)
STXVW4X VS48, (R11)(R8)
STXVW4X VS48, (R11)(R9)
STXVW4X VS48, (R11)(R10)
BR done_vsx
|
{
"language": "Assembly"
}
|
@*****************************************************************************
@ i420_yuyv.S : ARM NEONv1 I420 to YUYV chroma conversion
@*****************************************************************************
@ Copyright (C) 2009-2011 Rémi Denis-Courmont
@
@ This program is free software; you can redistribute it and/or modify
@ it under the terms of the GNU Lesser General Public License as published by
@ the Free Software Foundation; either version 2.1 of the License, or
@ (at your option) any later version.
@
@ This program is distributed in the hope that it will be useful,
@ but WITHOUT ANY WARRANTY; without even the implied warranty of
@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
@ GNU Lesser General Public License for more details.
@
@ You should have received a copy of the GNU Lesser General Public License
@ along with this program; if not, write to the Free Software Foundation,
@ Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301, USA.
@****************************************************************************/
#include "asm.S"
.syntax unified
#if HAVE_AS_FPU_DIRECTIVE
.fpu neon
#endif
.text
#define O1 r0
#define O2 r1
#define WIDTH r2
#define HEIGHT r3
#define Y1 r4
#define Y2 r5
#define U r6
#define V r7
#define YPITCH r8
#define OPAD r10
#define YPAD r11
#define COUNT ip
#define OPITCH lr
.align 2
function i420_yuyv_neon
push {r4-r8,r10-r11,lr}
ldmia r0, {O1, OPITCH}
ldmia r1, {Y1, U, V, YPITCH}
cmp HEIGHT, #0
sub OPAD, OPITCH, WIDTH, lsl #1
sub YPAD, YPITCH, WIDTH
1:
it gt
movsgt COUNT, WIDTH
add O2, O1, OPITCH
add Y2, Y1, YPITCH
it le
pople {r4-r8,r10-r11,pc}
2:
pld [U, #64]
vld1.u8 {d2}, [U,:64]!
pld [V, #64]
vld1.u8 {d3}, [V,:64]!
pld [Y1, #64]
vzip.u8 d2, d3
subs COUNT, COUNT, #16
vld1.u8 {q0}, [Y1,:128]!
pld [Y2, #64]
vmov q3, q1
vzip.u8 q0, q1
vld1.u8 {q2}, [Y2,:128]!
vzip.u8 q2, q3
vst1.u8 {q0-q1}, [O1,:128]!
vst1.u8 {q2-q3}, [O2,:128]!
bgt 2b
subs HEIGHT, #2
add O1, O2, OPAD
add Y1, Y2, YPAD
add U, U, YPAD, lsr #1
add V, V, YPAD, lsr #1
b 1b
function i420_uyvy_neon
push {r4-r8,r10-r11,lr}
ldmia r0, {O1, OPITCH}
ldmia r1, {Y1, U, V, YPITCH}
cmp HEIGHT, #0
sub OPAD, OPITCH, WIDTH, lsl #1
sub YPAD, YPITCH, WIDTH
1:
it gt
movsgt COUNT, WIDTH
add O2, O1, OPITCH
add Y2, Y1, YPITCH
it le
pople {r4-r8,r10-r11,pc}
2:
pld [U, #64]
vld1.u8 {d0}, [U,:64]!
pld [V, #64]
vld1.u8 {d1}, [V,:64]!
pld [Y1, #64]
vzip.u8 d0, d1
subs COUNT, COUNT, #16
vld1.u8 {q1}, [Y1,:128]!
pld [Y2, #64]
vmov q2, q0
vzip.u8 q0, q1
vld1.u8 {q3}, [Y2,:128]!
vzip.u8 q2, q3
vst1.u8 {q0-q1}, [O1,:128]!
vst1.u8 {q2-q3}, [O2,:128]!
bgt 2b
subs HEIGHT, #2
add O1, O2, OPAD
add Y1, Y2, YPAD
add U, U, YPAD, lsr #1
add V, V, YPAD, lsr #1
b 1b
|
{
"language": "Assembly"
}
|
/* This linker script generated from xt-genldscripts.tpp for LSP . */
/* Linker Script for ld -N */
MEMORY
{
dport0_0_seg : org = 0x3FF00000, len = 0x10
dram0_0_seg : org = 0x3FFE8000, len = 0x14000
iram1_0_seg : org = 0x40100000, len = 0x8000
irom0_0_seg : org = 0x40211000, len = 0x6B000
}
PHDRS
{
dport0_0_phdr PT_LOAD;
dram0_0_phdr PT_LOAD;
dram0_0_bss_phdr PT_LOAD;
iram1_0_phdr PT_LOAD;
irom0_0_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(call_user_start)
EXTERN(_DebugExceptionVector)
EXTERN(_DoubleExceptionVector)
EXTERN(_KernelExceptionVector)
EXTERN(_NMIExceptionVector)
EXTERN(_UserExceptionVector)
PROVIDE(_memmap_vecbase_reset = 0x40000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00000110;
_memmap_cacheattr_wt_base = 0x00000110;
_memmap_cacheattr_bp_base = 0x00000220;
_memmap_cacheattr_unused_mask = 0xFFFFF00F;
_memmap_cacheattr_wb_trapnull = 0x2222211F;
_memmap_cacheattr_wba_trapnull = 0x2222211F;
_memmap_cacheattr_wbna_trapnull = 0x2222211F;
_memmap_cacheattr_wt_trapnull = 0x2222211F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFFF11F;
_memmap_cacheattr_wt_strict = 0xFFFFF11F;
_memmap_cacheattr_bp_strict = 0xFFFFF22F;
_memmap_cacheattr_wb_allvalid = 0x22222112;
_memmap_cacheattr_wt_allvalid = 0x22222112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
.dport0.rodata : ALIGN(4)
{
_dport0_rodata_start = ABSOLUTE(.);
*(.dport0.rodata)
*(.dport.rodata)
_dport0_rodata_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.dport0.literal : ALIGN(4)
{
_dport0_literal_start = ABSOLUTE(.);
*(.dport0.literal)
*(.dport.literal)
_dport0_literal_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.dport0.data : ALIGN(4)
{
_dport0_data_start = ABSOLUTE(.);
*(.dport0.data)
*(.dport.data)
_dport0_data_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.sdk.version)
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*(.rodata.*)
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*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.bss ALIGN(8) (NOLOAD) : ALIGN(4)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_heap_start = ABSOLUTE(.);
/* _stack_sentry = ALIGN(0x8); */
} >dram0_0_seg :dram0_0_bss_phdr
/* __stack = 0x3ffc8000; */
.irom0.text : ALIGN(4)
{
_irom0_text_start = ABSOLUTE(.);
*libat.a:(.literal.* .text.*)
*libcrypto.a:(.literal.* .text.*)
*libespnow.a:(.literal.* .text.*)
*libjson.a:(.literal.* .text.*)
*liblwip.a:(.literal.* .text.*)
*libnet80211.a:(.literal.* .text.*)
*libsmartconfig.a:(.literal.* .text.*)
*libssl.a:(.literal.* .text.*)
*libupgrade.a:(.literal.* .text.*)
*libwpa.a:(.literal.* .text.*)
*libwpa2.a:(.literal.* .text.*)
*libwps.a:(.literal.* .text.*)
*libmbedtls.a:(.literal.* .text.*)
*libm.a:(.literal .text .literal.* .text.*)
*(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
_irom0_text_end = ABSOLUTE(.);
} >irom0_0_seg :irom0_0_phdr
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.UserEnter.text)
. = ALIGN(16);
*(.DebugExceptionVector.text)
. = ALIGN(16);
*(.NMIExceptionVector.text)
. = ALIGN(16);
*(.KernelExceptionVector.text)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
. = ALIGN(16);
*(.UserExceptionVector.text)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
. = ALIGN(16);
*(.DoubleExceptionVector.text)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
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{
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*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
} >iram1_0_seg :iram1_0_phdr
}
/* get ROM code address */
INCLUDE "../ld/eagle.rom.addr.v6.ld"
|
{
"language": "Assembly"
}
|
glabel func_80BA5370
/* 028D0 80BA5370 3C010001 */ lui $at, 0x0001 ## $at = 00010000
/* 028D4 80BA5374 27BDFFE8 */ addiu $sp, $sp, 0xFFE8 ## $sp = FFFFFFE8
/* 028D8 80BA5378 00803025 */ or $a2, $a0, $zero ## $a2 = 00000000
/* 028DC 80BA537C 342117A4 */ ori $at, $at, 0x17A4 ## $at = 000117A4
/* 028E0 80BA5380 AFBF0014 */ sw $ra, 0x0014($sp)
/* 028E4 80BA5384 00A12021 */ addu $a0, $a1, $at
/* 028E8 80BA5388 90C51658 */ lbu $a1, 0x1658($a2) ## 00001658
/* 028EC 80BA538C 0C026062 */ jal Object_IsLoaded
/* 028F0 80BA5390 AFA60018 */ sw $a2, 0x0018($sp)
/* 028F4 80BA5394 10400009 */ beq $v0, $zero, .L80BA53BC
/* 028F8 80BA5398 8FA60018 */ lw $a2, 0x0018($sp)
/* 028FC 80BA539C 90CF1658 */ lbu $t7, 0x1658($a2) ## 00001658
/* 02900 80BA53A0 240E0001 */ addiu $t6, $zero, 0x0001 ## $t6 = 00000001
/* 02904 80BA53A4 3C0580BA */ lui $a1, %hi(func_80BA53CC) ## $a1 = 80BA0000
/* 02908 80BA53A8 A0CE1659 */ sb $t6, 0x1659($a2) ## 00001659
/* 0290C 80BA53AC 24A553CC */ addiu $a1, $a1, %lo(func_80BA53CC) ## $a1 = 80BA53CC
/* 02910 80BA53B0 00C02025 */ or $a0, $a2, $zero ## $a0 = 00000000
/* 02914 80BA53B4 0C2E8AA8 */ jal func_80BA2AA0
/* 02918 80BA53B8 A0CF001E */ sb $t7, 0x001E($a2) ## 0000001E
.L80BA53BC:
/* 0291C 80BA53BC 8FBF0014 */ lw $ra, 0x0014($sp)
/* 02920 80BA53C0 27BD0018 */ addiu $sp, $sp, 0x0018 ## $sp = 00000000
/* 02924 80BA53C4 03E00008 */ jr $ra
/* 02928 80BA53C8 00000000 */ nop
|
{
"language": "Assembly"
}
|
// RUN: %clang_cc1 -triple=x86_64-apple-darwin9 -emit-pch -o %t.pch %S/target-options.h
// RUN: not %clang_cc1 -triple=x86_64-unknown-freebsd7.0 -include-pch %t.pch %s -emit-llvm -o - > %t.err 2>&1
// RUN: FileCheck %s < %t.err
// REQUIRES: x86-registered-target
// CHECK: for the target
|
{
"language": "Assembly"
}
|
/*
* downmix.c
* Copyright (C) 2004 Gildas Bazin <gbazin@videolan.org>
* Copyright (C) 2000-2003 Michel Lespinasse <walken@zoy.org>
* Copyright (C) 1999-2000 Aaron Holtzman <aholtzma@ess.engr.uvic.ca>
*
* This file is part of dtsdec, a free DTS Coherent Acoustics stream decoder.
* See http://www.videolan.org/dtsdec.html for updates.
*
* dtsdec is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* dtsdec is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "config.h"
#include <string.h>
#include <inttypes.h>
#include "dts.h"
#include "dts_internal.h"
#define CONVERT(acmod,output) (((output) << DTS_CHANNEL_BITS) + (acmod))
int dts_downmix_init (int input, int flags, level_t * level,
level_t clev, level_t slev)
{
static uint8_t table[11][10] = {
/* DTS_MONO */
{DTS_MONO, DTS_MONO, DTS_MONO, DTS_MONO,
DTS_MONO, DTS_MONO, DTS_MONO, DTS_MONO,
DTS_MONO, DTS_MONO},
/* DTS_CHANNEL */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO},
/* DTS_STEREO */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO},
/* DTS_STEREO_SUMDIFF */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO},
/* DTS_STEREO_TOTAL */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO},
/* DTS_3F */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_3F, DTS_3F, DTS_3F,
DTS_3F, DTS_3F},
/* DTS_2F1R */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_2F1R, DTS_2F1R, DTS_2F1R,
DTS_2F1R, DTS_2F1R},
/* DTS_3F1R */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_3F, DTS_3F1R, DTS_3F1R,
DTS_3F1R, DTS_3F1R},
/* DTS_2F2R */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_STEREO, DTS_2F2R, DTS_2F2R,
DTS_2F2R, DTS_2F2R},
/* DTS_3F2R */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_3F, DTS_3F2R, DTS_3F2R,
DTS_3F2R, DTS_3F2R},
/* DTS_4F2R */
{DTS_MONO, DTS_CHANNEL, DTS_STEREO, DTS_STEREO,
DTS_STEREO, DTS_4F2R, DTS_4F2R, DTS_4F2R,
DTS_4F2R, DTS_4F2R},
};
int output;
output = flags & DTS_CHANNEL_MASK;
if (output > DTS_CHANNEL_MAX)
return -1;
output = table[output][input];
if (output == DTS_STEREO &&
(input == DTS_DOLBY || (input == DTS_3F && clev == LEVEL (LEVEL_3DB))))
output = DTS_DOLBY;
if (flags & DTS_ADJUST_LEVEL) {
level_t adjust;
switch (CONVERT (input & 7, output)) {
case CONVERT (DTS_3F, DTS_MONO):
adjust = (sample_t)(DIV (LEVEL_3DB, LEVEL (1) + clev));
break;
case CONVERT (DTS_STEREO, DTS_MONO):
case CONVERT (DTS_2F2R, DTS_2F1R):
case CONVERT (DTS_3F2R, DTS_3F1R):
level_3db:
adjust = (sample_t)(LEVEL (LEVEL_3DB));
break;
case CONVERT (DTS_3F2R, DTS_2F1R):
if (clev < LEVEL (LEVEL_PLUS3DB - 1))
goto level_3db;
/* break thru */
case CONVERT (DTS_3F, DTS_STEREO):
case CONVERT (DTS_3F1R, DTS_2F1R):
case CONVERT (DTS_3F1R, DTS_2F2R):
case CONVERT (DTS_3F2R, DTS_2F2R):
adjust = DIV (1, LEVEL (1) + clev);
break;
case CONVERT (DTS_2F1R, DTS_MONO):
adjust = (sample_t)(DIV (LEVEL_PLUS3DB, LEVEL (2) + slev));
break;
case CONVERT (DTS_2F1R, DTS_STEREO):
case CONVERT (DTS_3F1R, DTS_3F):
adjust = (sample_t)(DIV (1, LEVEL (1) + MUL_C (slev, LEVEL_3DB)));
break;
case CONVERT (DTS_3F1R, DTS_MONO):
adjust = (sample_t)(DIV (LEVEL_3DB, LEVEL (1) + clev + MUL_C (slev, 0.5)));
break;
case CONVERT (DTS_3F1R, DTS_STEREO):
adjust = (sample_t)(DIV (1, LEVEL (1) + clev + MUL_C (slev, LEVEL_3DB)));
break;
case CONVERT (DTS_2F2R, DTS_MONO):
adjust = (sample_t)(DIV (LEVEL_3DB, LEVEL (1) + slev));
break;
case CONVERT (DTS_2F2R, DTS_STEREO):
case CONVERT (DTS_3F2R, DTS_3F):
adjust = DIV (1, LEVEL (1) + slev);
break;
case CONVERT (DTS_3F2R, DTS_MONO):
adjust = (sample_t)(DIV (LEVEL_3DB, LEVEL (1) + clev + slev));
break;
case CONVERT (DTS_3F2R, DTS_STEREO):
adjust = DIV (1, LEVEL (1) + clev + slev);
break;
case CONVERT (DTS_MONO, DTS_DOLBY):
adjust = (sample_t)(LEVEL (LEVEL_PLUS3DB));
break;
case CONVERT (DTS_3F, DTS_DOLBY):
case CONVERT (DTS_2F1R, DTS_DOLBY):
adjust = (sample_t)(LEVEL (1 / (1 + LEVEL_3DB)));
break;
case CONVERT (DTS_3F1R, DTS_DOLBY):
case CONVERT (DTS_2F2R, DTS_DOLBY):
adjust = (sample_t)(LEVEL (1 / (1 + 2 * LEVEL_3DB)));
break;
case CONVERT (DTS_3F2R, DTS_DOLBY):
adjust = (sample_t)(LEVEL (1 / (1 + 3 * LEVEL_3DB)));
break;
default:
return output;
}
*level = MUL_L (*level, adjust);
}
return output;
}
int dts_downmix_coeff (level_t * coeff, int acmod, int output, level_t level,
level_t clev, level_t slev)
{
level_t level_3db;
level_3db = (sample_t)(MUL_C (level, LEVEL_3DB));
switch (CONVERT (acmod, output & DTS_CHANNEL_MASK)) {
case CONVERT (DTS_CHANNEL, DTS_CHANNEL):
case CONVERT (DTS_MONO, DTS_MONO):
case CONVERT (DTS_STEREO, DTS_STEREO):
case CONVERT (DTS_3F, DTS_3F):
case CONVERT (DTS_2F1R, DTS_2F1R):
case CONVERT (DTS_3F1R, DTS_3F1R):
case CONVERT (DTS_2F2R, DTS_2F2R):
case CONVERT (DTS_3F2R, DTS_3F2R):
case CONVERT (DTS_STEREO, DTS_DOLBY):
coeff[0] = coeff[1] = coeff[2] = coeff[3] = coeff[4] = level;
return 0;
case CONVERT (DTS_CHANNEL, DTS_MONO):
coeff[0] = coeff[1] = (sample_t)(MUL_C (level, LEVEL_6DB));
return 3;
case CONVERT (DTS_STEREO, DTS_MONO):
coeff[0] = coeff[1] = level_3db;
return 3;
case CONVERT (DTS_3F, DTS_MONO):
coeff[0] = coeff[2] = level_3db;
coeff[1] = (sample_t)(MUL_C (MUL_L (level_3db, clev), LEVEL_PLUS6DB));
return 7;
case CONVERT (DTS_2F1R, DTS_MONO):
coeff[0] = coeff[1] = level_3db;
coeff[2] = MUL_L (level_3db, slev);
return 7;
case CONVERT (DTS_2F2R, DTS_MONO):
coeff[0] = coeff[1] = level_3db;
coeff[2] = coeff[3] = MUL_L (level_3db, slev);
return 15;
case CONVERT (DTS_3F1R, DTS_MONO):
coeff[0] = coeff[2] = level_3db;
coeff[1] = (sample_t)(MUL_C (MUL_L (level_3db, clev), LEVEL_PLUS6DB));
coeff[3] = MUL_L (level_3db, slev);
return 15;
case CONVERT (DTS_3F2R, DTS_MONO):
coeff[0] = coeff[2] = level_3db;
coeff[1] = (sample_t)(MUL_C (MUL_L (level_3db, clev), LEVEL_PLUS6DB));
coeff[3] = coeff[4] = MUL_L (level_3db, slev);
return 31;
case CONVERT (DTS_MONO, DTS_DOLBY):
coeff[0] = level_3db;
return 0;
case CONVERT (DTS_3F, DTS_DOLBY):
coeff[0] = coeff[2] = coeff[3] = coeff[4] = level;
coeff[1] = level_3db;
return 7;
case CONVERT (DTS_3F, DTS_STEREO):
case CONVERT (DTS_3F1R, DTS_2F1R):
case CONVERT (DTS_3F2R, DTS_2F2R):
coeff[0] = coeff[2] = coeff[3] = coeff[4] = level;
coeff[1] = MUL_L (level, clev);
return 7;
case CONVERT (DTS_2F1R, DTS_DOLBY):
coeff[0] = coeff[1] = level;
coeff[2] = level_3db;
return 7;
case CONVERT (DTS_2F1R, DTS_STEREO):
coeff[0] = coeff[1] = level;
coeff[2] = MUL_L (level_3db, slev);
return 7;
case CONVERT (DTS_3F1R, DTS_DOLBY):
coeff[0] = coeff[2] = level;
coeff[1] = coeff[3] = level_3db;
return 15;
case CONVERT (DTS_3F1R, DTS_STEREO):
coeff[0] = coeff[2] = level;
coeff[1] = MUL_L (level, clev);
coeff[3] = MUL_L (level_3db, slev);
return 15;
case CONVERT (DTS_2F2R, DTS_DOLBY):
coeff[0] = coeff[1] = level;
coeff[2] = coeff[3] = level_3db;
return 15;
case CONVERT (DTS_2F2R, DTS_STEREO):
coeff[0] = coeff[1] = level;
coeff[2] = coeff[3] = MUL_L (level, slev);
return 15;
case CONVERT (DTS_3F2R, DTS_DOLBY):
coeff[0] = coeff[2] = level;
coeff[1] = coeff[3] = coeff[4] = level_3db;
return 31;
case CONVERT (DTS_3F2R, DTS_2F1R):
coeff[0] = coeff[2] = level;
coeff[1] = MUL_L (level, clev);
coeff[3] = coeff[4] = level_3db;
return 31;
case CONVERT (DTS_3F2R, DTS_STEREO):
coeff[0] = coeff[2] = level;
coeff[1] = MUL_L (level, clev);
coeff[3] = coeff[4] = MUL_L (level, slev);
return 31;
case CONVERT (DTS_3F1R, DTS_3F):
coeff[0] = coeff[1] = coeff[2] = level;
coeff[3] = MUL_L (level_3db, slev);
return 13;
case CONVERT (DTS_3F2R, DTS_3F):
coeff[0] = coeff[1] = coeff[2] = level;
coeff[3] = coeff[4] = MUL_L (level, slev);
return 29;
case CONVERT (DTS_2F2R, DTS_2F1R):
coeff[0] = coeff[1] = level;
coeff[2] = coeff[3] = level_3db;
return 12;
case CONVERT (DTS_3F2R, DTS_3F1R):
coeff[0] = coeff[1] = coeff[2] = level;
coeff[3] = coeff[4] = level_3db;
return 24;
case CONVERT (DTS_2F1R, DTS_2F2R):
coeff[0] = coeff[1] = level;
coeff[2] = level_3db;
return 0;
case CONVERT (DTS_3F1R, DTS_2F2R):
coeff[0] = coeff[2] = level;
coeff[1] = MUL_L (level, clev);
coeff[3] = level_3db;
return 7;
case CONVERT (DTS_3F1R, DTS_3F2R):
coeff[0] = coeff[1] = coeff[2] = level;
coeff[3] = level_3db;
return 0;
}
return -1; /* NOTREACHED */
}
static void mix2to1 (sample_t * dest, sample_t * src, sample_t bias)
{
int i;
for (i = 0; i < 256; i++)
dest[i] += BIAS (src[i]);
}
static void mix3to1 (sample_t * samples, sample_t bias)
{
int i;
for (i = 0; i < 256; i++)
samples[i] += BIAS (samples[i + 256] + samples[i + 512]);
}
static void mix4to1 (sample_t * samples, sample_t bias)
{
int i;
for (i = 0; i < 256; i++)
samples[i] += BIAS (samples[i + 256] + samples[i + 512] +
samples[i + 768]);
}
static void mix5to1 (sample_t * samples, sample_t bias)
{
int i;
for (i = 0; i < 256; i++)
samples[i] += BIAS (samples[i + 256] + samples[i + 512] +
samples[i + 768] + samples[i + 1024]);
}
static void mix3to2 (sample_t * samples, sample_t bias)
{
int i;
sample_t common;
for (i = 0; i < 256; i++) {
common = BIAS (samples[i]);
samples[i] = samples[i + 256] + common;
samples[i + 256] = samples[i + 512] + common;
}
}
static void mix21to2 (sample_t * left, sample_t * right, sample_t bias)
{
int i;
sample_t common;
for (i = 0; i < 256; i++) {
common = BIAS (right[i + 256]);
left[i] += common;
right[i] += common;
}
}
static void mix21toS (sample_t * samples, sample_t bias)
{
int i;
sample_t surround;
for (i = 0; i < 256; i++) {
surround = samples[i + 512];
samples[i] += BIAS (-surround);
samples[i + 256] += BIAS (surround);
}
}
static void mix31to2 (sample_t * samples, sample_t bias)
{
int i;
sample_t common;
for (i = 0; i < 256; i++) {
common = BIAS (samples[i] + samples[i + 768]);
samples[i] = samples[i + 256] + common;
samples[i + 256] = samples[i + 512] + common;
}
}
static void mix31toS (sample_t * samples, sample_t bias)
{
int i;
sample_t common, surround;
for (i = 0; i < 256; i++) {
common = BIAS (samples[i]);
surround = samples[i + 768];
samples[i] = samples[i + 256] + common - surround;
samples[i + 256] = samples[i + 512] + common + surround;
}
}
static void mix22toS (sample_t * samples, sample_t bias)
{
int i;
sample_t surround;
for (i = 0; i < 256; i++) {
surround = samples[i + 512] + samples[i + 768];
samples[i] += BIAS (-surround);
samples[i + 256] += BIAS (surround);
}
}
static void mix32to2 (sample_t * samples, sample_t bias)
{
int i;
sample_t common;
for (i = 0; i < 256; i++) {
common = BIAS (samples[i]);
samples[i] = common + samples[i + 256] + samples[i + 768];
samples[i + 256] = common + samples[i + 512] + samples[i + 1024];
}
}
static void mix32toS (sample_t * samples, sample_t bias)
{
int i;
sample_t common, surround;
for (i = 0; i < 256; i++) {
common = BIAS (samples[i]);
surround = samples[i + 768] + samples[i + 1024];
samples[i] = samples[i + 256] + common - surround;
samples[i + 256] = samples[i + 512] + common + surround;
}
}
static void move2to1 (sample_t * src, sample_t * dest, sample_t bias)
{
int i;
for (i = 0; i < 256; i++)
dest[i] = BIAS (src[i] + src[i + 256]);
}
static void zero (sample_t * samples)
{
int i;
for (i = 0; i < 256; i++)
samples[i] = 0;
}
void dts_downmix (sample_t * samples, int acmod, int output, sample_t bias,
level_t clev, level_t slev)
{
(void)clev;
switch (CONVERT (acmod, output & DTS_CHANNEL_MASK)) {
case CONVERT (DTS_CHANNEL, DTS_MONO):
case CONVERT (DTS_STEREO, DTS_MONO):
mix_2to1:
mix2to1 (samples, samples + 256, bias);
break;
case CONVERT (DTS_2F1R, DTS_MONO):
if (slev == 0)
goto mix_2to1;
case CONVERT (DTS_3F, DTS_MONO):
mix_3to1:
mix3to1 (samples, bias);
break;
case CONVERT (DTS_3F1R, DTS_MONO):
if (slev == 0)
goto mix_3to1;
case CONVERT (DTS_2F2R, DTS_MONO):
if (slev == 0)
goto mix_2to1;
mix4to1 (samples, bias);
break;
case CONVERT (DTS_3F2R, DTS_MONO):
if (slev == 0)
goto mix_3to1;
mix5to1 (samples, bias);
break;
case CONVERT (DTS_MONO, DTS_DOLBY):
memcpy (samples + 256, samples, 256 * sizeof (sample_t));
break;
case CONVERT (DTS_3F, DTS_STEREO):
case CONVERT (DTS_3F, DTS_DOLBY):
mix_3to2:
mix3to2 (samples, bias);
break;
case CONVERT (DTS_2F1R, DTS_STEREO):
if (slev == 0)
break;
mix21to2 (samples, samples + 256, bias);
break;
case CONVERT (DTS_2F1R, DTS_DOLBY):
mix21toS (samples, bias);
break;
case CONVERT (DTS_3F1R, DTS_STEREO):
if (slev == 0)
goto mix_3to2;
mix31to2 (samples, bias);
break;
case CONVERT (DTS_3F1R, DTS_DOLBY):
mix31toS (samples, bias);
break;
case CONVERT (DTS_2F2R, DTS_STEREO):
if (slev == 0)
break;
mix2to1 (samples, samples + 512, bias);
mix2to1 (samples + 256, samples + 768, bias);
break;
case CONVERT (DTS_2F2R, DTS_DOLBY):
mix22toS (samples, bias);
break;
case CONVERT (DTS_3F2R, DTS_STEREO):
if (slev == 0)
goto mix_3to2;
mix32to2 (samples, bias);
break;
case CONVERT (DTS_3F2R, DTS_DOLBY):
mix32toS (samples, bias);
break;
case CONVERT (DTS_3F1R, DTS_3F):
if (slev == 0)
break;
mix21to2 (samples, samples + 512, bias);
break;
case CONVERT (DTS_3F2R, DTS_3F):
if (slev == 0)
break;
mix2to1 (samples, samples + 768, bias);
mix2to1 (samples + 512, samples + 1024, bias);
break;
case CONVERT (DTS_3F1R, DTS_2F1R):
mix3to2 (samples, bias);
memcpy (samples + 512, samples + 768, 256 * sizeof (sample_t));
break;
case CONVERT (DTS_2F2R, DTS_2F1R):
mix2to1 (samples + 512, samples + 768, bias);
break;
case CONVERT (DTS_3F2R, DTS_2F1R):
mix3to2 (samples, bias);
move2to1 (samples + 768, samples + 512, bias);
break;
case CONVERT (DTS_3F2R, DTS_3F1R):
mix2to1 (samples + 768, samples + 1024, bias);
break;
case CONVERT (DTS_2F1R, DTS_2F2R):
memcpy (samples + 768, samples + 512, 256 * sizeof (sample_t));
break;
case CONVERT (DTS_3F1R, DTS_2F2R):
mix3to2 (samples, bias);
memcpy (samples + 512, samples + 768, 256 * sizeof (sample_t));
break;
case CONVERT (DTS_3F2R, DTS_2F2R):
mix3to2 (samples, bias);
memcpy (samples + 512, samples + 768, 256 * sizeof (sample_t));
memcpy (samples + 768, samples + 1024, 256 * sizeof (sample_t));
break;
case CONVERT (DTS_3F1R, DTS_3F2R):
memcpy (samples + 1024, samples + 768, 256 * sizeof (sample_t));
break;
}
}
void dts_upmix (sample_t * samples, int acmod, int output)
{
switch (CONVERT (acmod, output & DTS_CHANNEL_MASK)) {
case CONVERT (DTS_3F2R, DTS_MONO):
zero (samples + 1024);
case CONVERT (DTS_3F1R, DTS_MONO):
case CONVERT (DTS_2F2R, DTS_MONO):
zero (samples + 768);
case CONVERT (DTS_3F, DTS_MONO):
case CONVERT (DTS_2F1R, DTS_MONO):
zero (samples + 512);
case CONVERT (DTS_CHANNEL, DTS_MONO):
case CONVERT (DTS_STEREO, DTS_MONO):
zero (samples + 256);
break;
case CONVERT (DTS_3F2R, DTS_STEREO):
case CONVERT (DTS_3F2R, DTS_DOLBY):
zero (samples + 1024);
case CONVERT (DTS_3F1R, DTS_STEREO):
case CONVERT (DTS_3F1R, DTS_DOLBY):
zero (samples + 768);
case CONVERT (DTS_3F, DTS_STEREO):
case CONVERT (DTS_3F, DTS_DOLBY):
mix_3to2:
memcpy (samples + 512, samples + 256, 256 * sizeof (sample_t));
zero (samples + 256);
break;
case CONVERT (DTS_2F2R, DTS_STEREO):
case CONVERT (DTS_2F2R, DTS_DOLBY):
zero (samples + 768);
case CONVERT (DTS_2F1R, DTS_STEREO):
case CONVERT (DTS_2F1R, DTS_DOLBY):
zero (samples + 512);
break;
case CONVERT (DTS_3F2R, DTS_3F):
zero (samples + 1024);
case CONVERT (DTS_3F1R, DTS_3F):
case CONVERT (DTS_2F2R, DTS_2F1R):
zero (samples + 768);
break;
case CONVERT (DTS_3F2R, DTS_3F1R):
zero (samples + 1024);
break;
case CONVERT (DTS_3F2R, DTS_2F1R):
zero (samples + 1024);
case CONVERT (DTS_3F1R, DTS_2F1R):
mix_31to21:
memcpy (samples + 768, samples + 512, 256 * sizeof (sample_t));
goto mix_3to2;
case CONVERT (DTS_3F2R, DTS_2F2R):
memcpy (samples + 1024, samples + 768, 256 * sizeof (sample_t));
goto mix_31to21;
}
}
|
{
"language": "Assembly"
}
|
;
; Ullrich von Bassewitz, 2011-07-10
;
; CC65 runtime: 8x16 => 24 unsigned multiplication
;
.export umul8x16r24, umul8x16r24m
.export umul8x16r16, umul8x16r16m
.include "zeropage.inc"
.macpack cpu
;---------------------------------------------------------------------------
; 8x16 => 24 unsigned multiplication routine. Because the overhead for a
; 8x16 => 16 unsigned multiplication routine is small, we will tag it with
; the matching labels, as well.
;
; routine LHS RHS result result also in
; -----------------------------------------------------------------------
; umul8x16r24 ax ptr1-low ax:sreg-low ptr1:sreg-low
; umul8x16r24m ptr3 ptr1-low ax:sreg-low ptr1:sreg-low
;
; ptr3 is left intact by the routine.
;
umul8x16r24:
umul8x16r16:
sta ptr3
stx ptr3+1
umul8x16r24m:
umul8x16r16m:
.if (.cpu .bitand ::CPU_ISET_65SC02)
stz ptr1+1
stz sreg
.else
ldx #0
stx ptr1+1
stx sreg
.endif
ldy #8 ; Number of bits
lda ptr1
ror a ; Get next bit into carry
@L0: bcc @L1
clc
tax
lda ptr3
adc ptr1+1
sta ptr1+1
lda ptr3+1
adc sreg
sta sreg
txa
@L1: ror sreg
ror ptr1+1
ror a
dey
bne @L0
sta ptr1 ; Save low byte of result
ldx ptr1+1 ; Load high byte of result
rts ; Done
|
{
"language": "Assembly"
}
|
IF @Version LT 800
ECHO MASM version 8.00 or later is strongly recommended.
ENDIF
.686
.MODEL FLAT
OPTION DOTNAME
IF @Version LT 800
.text$ SEGMENT PAGE 'CODE'
ELSE
.text$ SEGMENT ALIGN(64) 'CODE'
ENDIF
;EXTERN _OPENSSL_ia32cap_P:NEAR
ALIGN 16
_sha256_block_data_order PROC PUBLIC
$L_sha256_block_data_order_begin::
push ebp
push ebx
push esi
push edi
mov esi,DWORD PTR 20[esp]
mov edi,DWORD PTR 24[esp]
mov eax,DWORD PTR 28[esp]
mov ebx,esp
call $L000pic_point
$L000pic_point:
pop ebp
lea ebp,DWORD PTR ($L001K256-$L000pic_point)[ebp]
sub esp,16
and esp,-64
shl eax,6
add eax,edi
mov DWORD PTR [esp],esi
mov DWORD PTR 4[esp],edi
mov DWORD PTR 8[esp],eax
mov DWORD PTR 12[esp],ebx
jmp $L002loop
ALIGN 16
$L002loop:
mov eax,DWORD PTR [edi]
mov ebx,DWORD PTR 4[edi]
mov ecx,DWORD PTR 8[edi]
bswap eax
mov edx,DWORD PTR 12[edi]
bswap ebx
push eax
bswap ecx
push ebx
bswap edx
push ecx
push edx
mov eax,DWORD PTR 16[edi]
mov ebx,DWORD PTR 20[edi]
mov ecx,DWORD PTR 24[edi]
bswap eax
mov edx,DWORD PTR 28[edi]
bswap ebx
push eax
bswap ecx
push ebx
bswap edx
push ecx
push edx
mov eax,DWORD PTR 32[edi]
mov ebx,DWORD PTR 36[edi]
mov ecx,DWORD PTR 40[edi]
bswap eax
mov edx,DWORD PTR 44[edi]
bswap ebx
push eax
bswap ecx
push ebx
bswap edx
push ecx
push edx
mov eax,DWORD PTR 48[edi]
mov ebx,DWORD PTR 52[edi]
mov ecx,DWORD PTR 56[edi]
bswap eax
mov edx,DWORD PTR 60[edi]
bswap ebx
push eax
bswap ecx
push ebx
bswap edx
push ecx
push edx
add edi,64
lea esp,DWORD PTR [esp-36]
mov DWORD PTR 104[esp],edi
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov ecx,DWORD PTR 8[esi]
mov edi,DWORD PTR 12[esi]
mov DWORD PTR 8[esp],ebx
xor ebx,ecx
mov DWORD PTR 12[esp],ecx
mov DWORD PTR 16[esp],edi
mov DWORD PTR [esp],ebx
mov edx,DWORD PTR 16[esi]
mov ebx,DWORD PTR 20[esi]
mov ecx,DWORD PTR 24[esi]
mov edi,DWORD PTR 28[esi]
mov DWORD PTR 24[esp],ebx
mov DWORD PTR 28[esp],ecx
mov DWORD PTR 32[esp],edi
ALIGN 16
$L00300_15:
mov ecx,edx
mov esi,DWORD PTR 24[esp]
ror ecx,14
mov edi,DWORD PTR 28[esp]
xor ecx,edx
xor esi,edi
mov ebx,DWORD PTR 96[esp]
ror ecx,5
and esi,edx
mov DWORD PTR 20[esp],edx
xor edx,ecx
add ebx,DWORD PTR 32[esp]
xor esi,edi
ror edx,6
mov ecx,eax
add ebx,esi
ror ecx,9
add ebx,edx
mov edi,DWORD PTR 8[esp]
xor ecx,eax
mov DWORD PTR 4[esp],eax
lea esp,DWORD PTR [esp-4]
ror ecx,11
mov esi,DWORD PTR [ebp]
xor ecx,eax
mov edx,DWORD PTR 20[esp]
xor eax,edi
ror ecx,2
add ebx,esi
mov DWORD PTR [esp],eax
add edx,ebx
and eax,DWORD PTR 4[esp]
add ebx,ecx
xor eax,edi
add ebp,4
add eax,ebx
cmp esi,3248222580
jne $L00300_15
mov ecx,DWORD PTR 156[esp]
jmp $L00416_63
ALIGN 16
$L00416_63:
mov ebx,ecx
mov esi,DWORD PTR 104[esp]
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 160[esp]
shr edi,10
add ebx,DWORD PTR 124[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 24[esp]
ror ecx,14
add ebx,edi
mov edi,DWORD PTR 28[esp]
xor ecx,edx
xor esi,edi
mov DWORD PTR 96[esp],ebx
ror ecx,5
and esi,edx
mov DWORD PTR 20[esp],edx
xor edx,ecx
add ebx,DWORD PTR 32[esp]
xor esi,edi
ror edx,6
mov ecx,eax
add ebx,esi
ror ecx,9
add ebx,edx
mov edi,DWORD PTR 8[esp]
xor ecx,eax
mov DWORD PTR 4[esp],eax
lea esp,DWORD PTR [esp-4]
ror ecx,11
mov esi,DWORD PTR [ebp]
xor ecx,eax
mov edx,DWORD PTR 20[esp]
xor eax,edi
ror ecx,2
add ebx,esi
mov DWORD PTR [esp],eax
add edx,ebx
and eax,DWORD PTR 4[esp]
add ebx,ecx
xor eax,edi
mov ecx,DWORD PTR 156[esp]
add ebp,4
add eax,ebx
cmp esi,3329325298
jne $L00416_63
mov esi,DWORD PTR 356[esp]
mov ebx,DWORD PTR 8[esp]
mov ecx,DWORD PTR 16[esp]
add eax,DWORD PTR [esi]
add ebx,DWORD PTR 4[esi]
add edi,DWORD PTR 8[esi]
add ecx,DWORD PTR 12[esi]
mov DWORD PTR [esi],eax
mov DWORD PTR 4[esi],ebx
mov DWORD PTR 8[esi],edi
mov DWORD PTR 12[esi],ecx
mov eax,DWORD PTR 24[esp]
mov ebx,DWORD PTR 28[esp]
mov ecx,DWORD PTR 32[esp]
mov edi,DWORD PTR 360[esp]
add edx,DWORD PTR 16[esi]
add eax,DWORD PTR 20[esi]
add ebx,DWORD PTR 24[esi]
add ecx,DWORD PTR 28[esi]
mov DWORD PTR 16[esi],edx
mov DWORD PTR 20[esi],eax
mov DWORD PTR 24[esi],ebx
mov DWORD PTR 28[esi],ecx
lea esp,DWORD PTR 356[esp]
sub ebp,256
cmp edi,DWORD PTR 8[esp]
jb $L002loop
mov esp,DWORD PTR 12[esp]
pop edi
pop esi
pop ebx
pop ebp
ret
ALIGN 32
$L005loop_shrd:
mov eax,DWORD PTR [edi]
mov ebx,DWORD PTR 4[edi]
mov ecx,DWORD PTR 8[edi]
bswap eax
mov edx,DWORD PTR 12[edi]
bswap ebx
push eax
bswap ecx
push ebx
bswap edx
push ecx
push edx
mov eax,DWORD PTR 16[edi]
mov ebx,DWORD PTR 20[edi]
mov ecx,DWORD PTR 24[edi]
bswap eax
mov edx,DWORD PTR 28[edi]
bswap ebx
push eax
bswap ecx
push ebx
bswap edx
push ecx
push edx
mov eax,DWORD PTR 32[edi]
mov ebx,DWORD PTR 36[edi]
mov ecx,DWORD PTR 40[edi]
bswap eax
mov edx,DWORD PTR 44[edi]
bswap ebx
push eax
bswap ecx
push ebx
bswap edx
push ecx
push edx
mov eax,DWORD PTR 48[edi]
mov ebx,DWORD PTR 52[edi]
mov ecx,DWORD PTR 56[edi]
bswap eax
mov edx,DWORD PTR 60[edi]
bswap ebx
push eax
bswap ecx
push ebx
bswap edx
push ecx
push edx
add edi,64
lea esp,DWORD PTR [esp-36]
mov DWORD PTR 104[esp],edi
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov ecx,DWORD PTR 8[esi]
mov edi,DWORD PTR 12[esi]
mov DWORD PTR 8[esp],ebx
xor ebx,ecx
mov DWORD PTR 12[esp],ecx
mov DWORD PTR 16[esp],edi
mov DWORD PTR [esp],ebx
mov edx,DWORD PTR 16[esi]
mov ebx,DWORD PTR 20[esi]
mov ecx,DWORD PTR 24[esi]
mov edi,DWORD PTR 28[esi]
mov DWORD PTR 24[esp],ebx
mov DWORD PTR 28[esp],ecx
mov DWORD PTR 32[esp],edi
ALIGN 16
$L00600_15_shrd:
mov ecx,edx
mov esi,DWORD PTR 24[esp]
shrd ecx,ecx,14
mov edi,DWORD PTR 28[esp]
xor ecx,edx
xor esi,edi
mov ebx,DWORD PTR 96[esp]
shrd ecx,ecx,5
and esi,edx
mov DWORD PTR 20[esp],edx
xor edx,ecx
add ebx,DWORD PTR 32[esp]
xor esi,edi
shrd edx,edx,6
mov ecx,eax
add ebx,esi
shrd ecx,ecx,9
add ebx,edx
mov edi,DWORD PTR 8[esp]
xor ecx,eax
mov DWORD PTR 4[esp],eax
lea esp,DWORD PTR [esp-4]
shrd ecx,ecx,11
mov esi,DWORD PTR [ebp]
xor ecx,eax
mov edx,DWORD PTR 20[esp]
xor eax,edi
shrd ecx,ecx,2
add ebx,esi
mov DWORD PTR [esp],eax
add edx,ebx
and eax,DWORD PTR 4[esp]
add ebx,ecx
xor eax,edi
add ebp,4
add eax,ebx
cmp esi,3248222580
jne $L00600_15_shrd
mov ecx,DWORD PTR 156[esp]
jmp $L00716_63_shrd
ALIGN 16
$L00716_63_shrd:
mov ebx,ecx
mov esi,DWORD PTR 104[esp]
shrd ecx,ecx,11
mov edi,esi
shrd esi,esi,2
xor ecx,ebx
shr ebx,3
shrd ecx,ecx,7
xor esi,edi
xor ebx,ecx
shrd esi,esi,17
add ebx,DWORD PTR 160[esp]
shr edi,10
add ebx,DWORD PTR 124[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 24[esp]
shrd ecx,ecx,14
add ebx,edi
mov edi,DWORD PTR 28[esp]
xor ecx,edx
xor esi,edi
mov DWORD PTR 96[esp],ebx
shrd ecx,ecx,5
and esi,edx
mov DWORD PTR 20[esp],edx
xor edx,ecx
add ebx,DWORD PTR 32[esp]
xor esi,edi
shrd edx,edx,6
mov ecx,eax
add ebx,esi
shrd ecx,ecx,9
add ebx,edx
mov edi,DWORD PTR 8[esp]
xor ecx,eax
mov DWORD PTR 4[esp],eax
lea esp,DWORD PTR [esp-4]
shrd ecx,ecx,11
mov esi,DWORD PTR [ebp]
xor ecx,eax
mov edx,DWORD PTR 20[esp]
xor eax,edi
shrd ecx,ecx,2
add ebx,esi
mov DWORD PTR [esp],eax
add edx,ebx
and eax,DWORD PTR 4[esp]
add ebx,ecx
xor eax,edi
mov ecx,DWORD PTR 156[esp]
add ebp,4
add eax,ebx
cmp esi,3329325298
jne $L00716_63_shrd
mov esi,DWORD PTR 356[esp]
mov ebx,DWORD PTR 8[esp]
mov ecx,DWORD PTR 16[esp]
add eax,DWORD PTR [esi]
add ebx,DWORD PTR 4[esi]
add edi,DWORD PTR 8[esi]
add ecx,DWORD PTR 12[esi]
mov DWORD PTR [esi],eax
mov DWORD PTR 4[esi],ebx
mov DWORD PTR 8[esi],edi
mov DWORD PTR 12[esi],ecx
mov eax,DWORD PTR 24[esp]
mov ebx,DWORD PTR 28[esp]
mov ecx,DWORD PTR 32[esp]
mov edi,DWORD PTR 360[esp]
add edx,DWORD PTR 16[esi]
add eax,DWORD PTR 20[esi]
add ebx,DWORD PTR 24[esi]
add ecx,DWORD PTR 28[esi]
mov DWORD PTR 16[esi],edx
mov DWORD PTR 20[esi],eax
mov DWORD PTR 24[esi],ebx
mov DWORD PTR 28[esi],ecx
lea esp,DWORD PTR 356[esp]
sub ebp,256
cmp edi,DWORD PTR 8[esp]
jb $L005loop_shrd
mov esp,DWORD PTR 12[esp]
pop edi
pop esi
pop ebx
pop ebp
ret
ALIGN 64
$L001K256:
DD 1116352408,1899447441,3049323471,3921009573
DD 961987163,1508970993,2453635748,2870763221
DD 3624381080,310598401,607225278,1426881987
DD 1925078388,2162078206,2614888103,3248222580
DD 3835390401,4022224774,264347078,604807628
DD 770255983,1249150122,1555081692,1996064986
DD 2554220882,2821834349,2952996808,3210313671
DD 3336571891,3584528711,113926993,338241895
DD 666307205,773529912,1294757372,1396182291
DD 1695183700,1986661051,2177026350,2456956037
DD 2730485921,2820302411,3259730800,3345764771
DD 3516065817,3600352804,4094571909,275423344
DD 430227734,506948616,659060556,883997877
DD 958139571,1322822218,1537002063,1747873779
DD 1955562222,2024104815,2227730452,2361852424
DD 2428436474,2756734187,3204031479,3329325298
DD 66051,67438087,134810123,202182159
DB 83,72,65,50,53,54,32,98,108,111,99,107,32,116,114,97
DB 110,115,102,111,114,109,32,102,111,114,32,120,56,54,44,32
DB 67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97
DB 112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103
DB 62,0
ALIGN 16
$L008unrolled:
lea esp,DWORD PTR [esp-96]
mov eax,DWORD PTR [esi]
mov ebp,DWORD PTR 4[esi]
mov ecx,DWORD PTR 8[esi]
mov ebx,DWORD PTR 12[esi]
mov DWORD PTR 4[esp],ebp
xor ebp,ecx
mov DWORD PTR 8[esp],ecx
mov DWORD PTR 12[esp],ebx
mov edx,DWORD PTR 16[esi]
mov ebx,DWORD PTR 20[esi]
mov ecx,DWORD PTR 24[esi]
mov esi,DWORD PTR 28[esi]
mov DWORD PTR 20[esp],ebx
mov DWORD PTR 24[esp],ecx
mov DWORD PTR 28[esp],esi
jmp $L009grand_loop
ALIGN 16
$L009grand_loop:
mov ebx,DWORD PTR [edi]
mov ecx,DWORD PTR 4[edi]
bswap ebx
mov esi,DWORD PTR 8[edi]
bswap ecx
mov DWORD PTR 32[esp],ebx
bswap esi
mov DWORD PTR 36[esp],ecx
mov DWORD PTR 40[esp],esi
mov ebx,DWORD PTR 12[edi]
mov ecx,DWORD PTR 16[edi]
bswap ebx
mov esi,DWORD PTR 20[edi]
bswap ecx
mov DWORD PTR 44[esp],ebx
bswap esi
mov DWORD PTR 48[esp],ecx
mov DWORD PTR 52[esp],esi
mov ebx,DWORD PTR 24[edi]
mov ecx,DWORD PTR 28[edi]
bswap ebx
mov esi,DWORD PTR 32[edi]
bswap ecx
mov DWORD PTR 56[esp],ebx
bswap esi
mov DWORD PTR 60[esp],ecx
mov DWORD PTR 64[esp],esi
mov ebx,DWORD PTR 36[edi]
mov ecx,DWORD PTR 40[edi]
bswap ebx
mov esi,DWORD PTR 44[edi]
bswap ecx
mov DWORD PTR 68[esp],ebx
bswap esi
mov DWORD PTR 72[esp],ecx
mov DWORD PTR 76[esp],esi
mov ebx,DWORD PTR 48[edi]
mov ecx,DWORD PTR 52[edi]
bswap ebx
mov esi,DWORD PTR 56[edi]
bswap ecx
mov DWORD PTR 80[esp],ebx
bswap esi
mov DWORD PTR 84[esp],ecx
mov DWORD PTR 88[esp],esi
mov ebx,DWORD PTR 60[edi]
add edi,64
bswap ebx
mov DWORD PTR 100[esp],edi
mov DWORD PTR 92[esp],ebx
mov ecx,edx
mov esi,DWORD PTR 20[esp]
ror edx,14
mov edi,DWORD PTR 24[esp]
xor edx,ecx
mov ebx,DWORD PTR 32[esp]
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 16[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 28[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 4[esp]
xor ecx,eax
mov DWORD PTR [esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 1116352408[edx*1+ebx]
xor ecx,esi
xor ebp,edi
ror ecx,2
add ebp,edx
add edx,DWORD PTR 12[esp]
add ebp,ecx
mov esi,edx
mov ecx,DWORD PTR 16[esp]
ror edx,14
mov edi,DWORD PTR 20[esp]
xor edx,esi
mov ebx,DWORD PTR 36[esp]
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 12[esp],esi
xor edx,esi
add ebx,DWORD PTR 24[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR [esp]
xor esi,ebp
mov DWORD PTR 28[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1899447441[edx*1+ebx]
xor esi,ecx
xor eax,edi
ror esi,2
add eax,edx
add edx,DWORD PTR 8[esp]
add eax,esi
mov ecx,edx
mov esi,DWORD PTR 12[esp]
ror edx,14
mov edi,DWORD PTR 16[esp]
xor edx,ecx
mov ebx,DWORD PTR 40[esp]
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 8[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 20[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 28[esp]
xor ecx,eax
mov DWORD PTR 24[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 3049323471[edx*1+ebx]
xor ecx,esi
xor ebp,edi
ror ecx,2
add ebp,edx
add edx,DWORD PTR 4[esp]
add ebp,ecx
mov esi,edx
mov ecx,DWORD PTR 8[esp]
ror edx,14
mov edi,DWORD PTR 12[esp]
xor edx,esi
mov ebx,DWORD PTR 44[esp]
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 4[esp],esi
xor edx,esi
add ebx,DWORD PTR 16[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 24[esp]
xor esi,ebp
mov DWORD PTR 20[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 3921009573[edx*1+ebx]
xor esi,ecx
xor eax,edi
ror esi,2
add eax,edx
add edx,DWORD PTR [esp]
add eax,esi
mov ecx,edx
mov esi,DWORD PTR 4[esp]
ror edx,14
mov edi,DWORD PTR 8[esp]
xor edx,ecx
mov ebx,DWORD PTR 48[esp]
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR [esp],ecx
xor edx,ecx
add ebx,DWORD PTR 12[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 20[esp]
xor ecx,eax
mov DWORD PTR 16[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 961987163[edx*1+ebx]
xor ecx,esi
xor ebp,edi
ror ecx,2
add ebp,edx
add edx,DWORD PTR 28[esp]
add ebp,ecx
mov esi,edx
mov ecx,DWORD PTR [esp]
ror edx,14
mov edi,DWORD PTR 4[esp]
xor edx,esi
mov ebx,DWORD PTR 52[esp]
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 28[esp],esi
xor edx,esi
add ebx,DWORD PTR 8[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 16[esp]
xor esi,ebp
mov DWORD PTR 12[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1508970993[edx*1+ebx]
xor esi,ecx
xor eax,edi
ror esi,2
add eax,edx
add edx,DWORD PTR 24[esp]
add eax,esi
mov ecx,edx
mov esi,DWORD PTR 28[esp]
ror edx,14
mov edi,DWORD PTR [esp]
xor edx,ecx
mov ebx,DWORD PTR 56[esp]
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 24[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 4[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 12[esp]
xor ecx,eax
mov DWORD PTR 8[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 2453635748[edx*1+ebx]
xor ecx,esi
xor ebp,edi
ror ecx,2
add ebp,edx
add edx,DWORD PTR 20[esp]
add ebp,ecx
mov esi,edx
mov ecx,DWORD PTR 24[esp]
ror edx,14
mov edi,DWORD PTR 28[esp]
xor edx,esi
mov ebx,DWORD PTR 60[esp]
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 20[esp],esi
xor edx,esi
add ebx,DWORD PTR [esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 8[esp]
xor esi,ebp
mov DWORD PTR 4[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 2870763221[edx*1+ebx]
xor esi,ecx
xor eax,edi
ror esi,2
add eax,edx
add edx,DWORD PTR 16[esp]
add eax,esi
mov ecx,edx
mov esi,DWORD PTR 20[esp]
ror edx,14
mov edi,DWORD PTR 24[esp]
xor edx,ecx
mov ebx,DWORD PTR 64[esp]
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 16[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 28[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 4[esp]
xor ecx,eax
mov DWORD PTR [esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 3624381080[edx*1+ebx]
xor ecx,esi
xor ebp,edi
ror ecx,2
add ebp,edx
add edx,DWORD PTR 12[esp]
add ebp,ecx
mov esi,edx
mov ecx,DWORD PTR 16[esp]
ror edx,14
mov edi,DWORD PTR 20[esp]
xor edx,esi
mov ebx,DWORD PTR 68[esp]
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 12[esp],esi
xor edx,esi
add ebx,DWORD PTR 24[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR [esp]
xor esi,ebp
mov DWORD PTR 28[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 310598401[edx*1+ebx]
xor esi,ecx
xor eax,edi
ror esi,2
add eax,edx
add edx,DWORD PTR 8[esp]
add eax,esi
mov ecx,edx
mov esi,DWORD PTR 12[esp]
ror edx,14
mov edi,DWORD PTR 16[esp]
xor edx,ecx
mov ebx,DWORD PTR 72[esp]
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 8[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 20[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 28[esp]
xor ecx,eax
mov DWORD PTR 24[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 607225278[edx*1+ebx]
xor ecx,esi
xor ebp,edi
ror ecx,2
add ebp,edx
add edx,DWORD PTR 4[esp]
add ebp,ecx
mov esi,edx
mov ecx,DWORD PTR 8[esp]
ror edx,14
mov edi,DWORD PTR 12[esp]
xor edx,esi
mov ebx,DWORD PTR 76[esp]
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 4[esp],esi
xor edx,esi
add ebx,DWORD PTR 16[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 24[esp]
xor esi,ebp
mov DWORD PTR 20[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1426881987[edx*1+ebx]
xor esi,ecx
xor eax,edi
ror esi,2
add eax,edx
add edx,DWORD PTR [esp]
add eax,esi
mov ecx,edx
mov esi,DWORD PTR 4[esp]
ror edx,14
mov edi,DWORD PTR 8[esp]
xor edx,ecx
mov ebx,DWORD PTR 80[esp]
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR [esp],ecx
xor edx,ecx
add ebx,DWORD PTR 12[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 20[esp]
xor ecx,eax
mov DWORD PTR 16[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 1925078388[edx*1+ebx]
xor ecx,esi
xor ebp,edi
ror ecx,2
add ebp,edx
add edx,DWORD PTR 28[esp]
add ebp,ecx
mov esi,edx
mov ecx,DWORD PTR [esp]
ror edx,14
mov edi,DWORD PTR 4[esp]
xor edx,esi
mov ebx,DWORD PTR 84[esp]
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 28[esp],esi
xor edx,esi
add ebx,DWORD PTR 8[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 16[esp]
xor esi,ebp
mov DWORD PTR 12[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 2162078206[edx*1+ebx]
xor esi,ecx
xor eax,edi
ror esi,2
add eax,edx
add edx,DWORD PTR 24[esp]
add eax,esi
mov ecx,edx
mov esi,DWORD PTR 28[esp]
ror edx,14
mov edi,DWORD PTR [esp]
xor edx,ecx
mov ebx,DWORD PTR 88[esp]
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 24[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 4[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 12[esp]
xor ecx,eax
mov DWORD PTR 8[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 2614888103[edx*1+ebx]
xor ecx,esi
xor ebp,edi
ror ecx,2
add ebp,edx
add edx,DWORD PTR 20[esp]
add ebp,ecx
mov esi,edx
mov ecx,DWORD PTR 24[esp]
ror edx,14
mov edi,DWORD PTR 28[esp]
xor edx,esi
mov ebx,DWORD PTR 92[esp]
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 20[esp],esi
xor edx,esi
add ebx,DWORD PTR [esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 8[esp]
xor esi,ebp
mov DWORD PTR 4[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 3248222580[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 36[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 16[esp]
add eax,esi
mov esi,DWORD PTR 88[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 32[esp]
shr edi,10
add ebx,DWORD PTR 68[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 20[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 24[esp]
xor edx,ecx
mov DWORD PTR 32[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 16[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 28[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 4[esp]
xor ecx,eax
mov DWORD PTR [esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 3835390401[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 40[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 12[esp]
add ebp,ecx
mov ecx,DWORD PTR 92[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 36[esp]
shr edi,10
add ebx,DWORD PTR 72[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 16[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 20[esp]
xor edx,esi
mov DWORD PTR 36[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 12[esp],esi
xor edx,esi
add ebx,DWORD PTR 24[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR [esp]
xor esi,ebp
mov DWORD PTR 28[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 4022224774[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 44[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 8[esp]
add eax,esi
mov esi,DWORD PTR 32[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 40[esp]
shr edi,10
add ebx,DWORD PTR 76[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 12[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 16[esp]
xor edx,ecx
mov DWORD PTR 40[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 8[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 20[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 28[esp]
xor ecx,eax
mov DWORD PTR 24[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 264347078[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 48[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 4[esp]
add ebp,ecx
mov ecx,DWORD PTR 36[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 44[esp]
shr edi,10
add ebx,DWORD PTR 80[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 8[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 12[esp]
xor edx,esi
mov DWORD PTR 44[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 4[esp],esi
xor edx,esi
add ebx,DWORD PTR 16[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 24[esp]
xor esi,ebp
mov DWORD PTR 20[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 604807628[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 52[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR [esp]
add eax,esi
mov esi,DWORD PTR 40[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 48[esp]
shr edi,10
add ebx,DWORD PTR 84[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 4[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 8[esp]
xor edx,ecx
mov DWORD PTR 48[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR [esp],ecx
xor edx,ecx
add ebx,DWORD PTR 12[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 20[esp]
xor ecx,eax
mov DWORD PTR 16[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 770255983[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 56[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 28[esp]
add ebp,ecx
mov ecx,DWORD PTR 44[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 52[esp]
shr edi,10
add ebx,DWORD PTR 88[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR [esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 4[esp]
xor edx,esi
mov DWORD PTR 52[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 28[esp],esi
xor edx,esi
add ebx,DWORD PTR 8[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 16[esp]
xor esi,ebp
mov DWORD PTR 12[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1249150122[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 60[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 24[esp]
add eax,esi
mov esi,DWORD PTR 48[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 56[esp]
shr edi,10
add ebx,DWORD PTR 92[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 28[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR [esp]
xor edx,ecx
mov DWORD PTR 56[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 24[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 4[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 12[esp]
xor ecx,eax
mov DWORD PTR 8[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 1555081692[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 64[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 20[esp]
add ebp,ecx
mov ecx,DWORD PTR 52[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 60[esp]
shr edi,10
add ebx,DWORD PTR 32[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 24[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 28[esp]
xor edx,esi
mov DWORD PTR 60[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 20[esp],esi
xor edx,esi
add ebx,DWORD PTR [esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 8[esp]
xor esi,ebp
mov DWORD PTR 4[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1996064986[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 68[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 16[esp]
add eax,esi
mov esi,DWORD PTR 56[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 64[esp]
shr edi,10
add ebx,DWORD PTR 36[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 20[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 24[esp]
xor edx,ecx
mov DWORD PTR 64[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 16[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 28[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 4[esp]
xor ecx,eax
mov DWORD PTR [esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 2554220882[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 72[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 12[esp]
add ebp,ecx
mov ecx,DWORD PTR 60[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 68[esp]
shr edi,10
add ebx,DWORD PTR 40[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 16[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 20[esp]
xor edx,esi
mov DWORD PTR 68[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 12[esp],esi
xor edx,esi
add ebx,DWORD PTR 24[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR [esp]
xor esi,ebp
mov DWORD PTR 28[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 2821834349[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 76[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 8[esp]
add eax,esi
mov esi,DWORD PTR 64[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 72[esp]
shr edi,10
add ebx,DWORD PTR 44[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 12[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 16[esp]
xor edx,ecx
mov DWORD PTR 72[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 8[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 20[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 28[esp]
xor ecx,eax
mov DWORD PTR 24[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 2952996808[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 80[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 4[esp]
add ebp,ecx
mov ecx,DWORD PTR 68[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 76[esp]
shr edi,10
add ebx,DWORD PTR 48[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 8[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 12[esp]
xor edx,esi
mov DWORD PTR 76[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 4[esp],esi
xor edx,esi
add ebx,DWORD PTR 16[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 24[esp]
xor esi,ebp
mov DWORD PTR 20[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 3210313671[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 84[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR [esp]
add eax,esi
mov esi,DWORD PTR 72[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 80[esp]
shr edi,10
add ebx,DWORD PTR 52[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 4[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 8[esp]
xor edx,ecx
mov DWORD PTR 80[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR [esp],ecx
xor edx,ecx
add ebx,DWORD PTR 12[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 20[esp]
xor ecx,eax
mov DWORD PTR 16[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 3336571891[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 88[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 28[esp]
add ebp,ecx
mov ecx,DWORD PTR 76[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 84[esp]
shr edi,10
add ebx,DWORD PTR 56[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR [esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 4[esp]
xor edx,esi
mov DWORD PTR 84[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 28[esp],esi
xor edx,esi
add ebx,DWORD PTR 8[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 16[esp]
xor esi,ebp
mov DWORD PTR 12[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 3584528711[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 92[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 24[esp]
add eax,esi
mov esi,DWORD PTR 80[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 88[esp]
shr edi,10
add ebx,DWORD PTR 60[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 28[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR [esp]
xor edx,ecx
mov DWORD PTR 88[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 24[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 4[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 12[esp]
xor ecx,eax
mov DWORD PTR 8[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 113926993[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 32[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 20[esp]
add ebp,ecx
mov ecx,DWORD PTR 84[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 92[esp]
shr edi,10
add ebx,DWORD PTR 64[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 24[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 28[esp]
xor edx,esi
mov DWORD PTR 92[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 20[esp],esi
xor edx,esi
add ebx,DWORD PTR [esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 8[esp]
xor esi,ebp
mov DWORD PTR 4[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 338241895[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 36[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 16[esp]
add eax,esi
mov esi,DWORD PTR 88[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 32[esp]
shr edi,10
add ebx,DWORD PTR 68[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 20[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 24[esp]
xor edx,ecx
mov DWORD PTR 32[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 16[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 28[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 4[esp]
xor ecx,eax
mov DWORD PTR [esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 666307205[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 40[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 12[esp]
add ebp,ecx
mov ecx,DWORD PTR 92[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 36[esp]
shr edi,10
add ebx,DWORD PTR 72[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 16[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 20[esp]
xor edx,esi
mov DWORD PTR 36[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 12[esp],esi
xor edx,esi
add ebx,DWORD PTR 24[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR [esp]
xor esi,ebp
mov DWORD PTR 28[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 773529912[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 44[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 8[esp]
add eax,esi
mov esi,DWORD PTR 32[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 40[esp]
shr edi,10
add ebx,DWORD PTR 76[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 12[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 16[esp]
xor edx,ecx
mov DWORD PTR 40[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 8[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 20[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 28[esp]
xor ecx,eax
mov DWORD PTR 24[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 1294757372[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 48[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 4[esp]
add ebp,ecx
mov ecx,DWORD PTR 36[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 44[esp]
shr edi,10
add ebx,DWORD PTR 80[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 8[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 12[esp]
xor edx,esi
mov DWORD PTR 44[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 4[esp],esi
xor edx,esi
add ebx,DWORD PTR 16[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 24[esp]
xor esi,ebp
mov DWORD PTR 20[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1396182291[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 52[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR [esp]
add eax,esi
mov esi,DWORD PTR 40[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 48[esp]
shr edi,10
add ebx,DWORD PTR 84[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 4[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 8[esp]
xor edx,ecx
mov DWORD PTR 48[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR [esp],ecx
xor edx,ecx
add ebx,DWORD PTR 12[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 20[esp]
xor ecx,eax
mov DWORD PTR 16[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 1695183700[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 56[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 28[esp]
add ebp,ecx
mov ecx,DWORD PTR 44[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 52[esp]
shr edi,10
add ebx,DWORD PTR 88[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR [esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 4[esp]
xor edx,esi
mov DWORD PTR 52[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 28[esp],esi
xor edx,esi
add ebx,DWORD PTR 8[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 16[esp]
xor esi,ebp
mov DWORD PTR 12[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1986661051[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 60[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 24[esp]
add eax,esi
mov esi,DWORD PTR 48[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 56[esp]
shr edi,10
add ebx,DWORD PTR 92[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 28[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR [esp]
xor edx,ecx
mov DWORD PTR 56[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 24[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 4[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 12[esp]
xor ecx,eax
mov DWORD PTR 8[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 2177026350[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 64[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 20[esp]
add ebp,ecx
mov ecx,DWORD PTR 52[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 60[esp]
shr edi,10
add ebx,DWORD PTR 32[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 24[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 28[esp]
xor edx,esi
mov DWORD PTR 60[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 20[esp],esi
xor edx,esi
add ebx,DWORD PTR [esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 8[esp]
xor esi,ebp
mov DWORD PTR 4[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 2456956037[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 68[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 16[esp]
add eax,esi
mov esi,DWORD PTR 56[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 64[esp]
shr edi,10
add ebx,DWORD PTR 36[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 20[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 24[esp]
xor edx,ecx
mov DWORD PTR 64[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 16[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 28[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 4[esp]
xor ecx,eax
mov DWORD PTR [esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 2730485921[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 72[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 12[esp]
add ebp,ecx
mov ecx,DWORD PTR 60[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 68[esp]
shr edi,10
add ebx,DWORD PTR 40[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 16[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 20[esp]
xor edx,esi
mov DWORD PTR 68[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 12[esp],esi
xor edx,esi
add ebx,DWORD PTR 24[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR [esp]
xor esi,ebp
mov DWORD PTR 28[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 2820302411[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 76[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 8[esp]
add eax,esi
mov esi,DWORD PTR 64[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 72[esp]
shr edi,10
add ebx,DWORD PTR 44[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 12[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 16[esp]
xor edx,ecx
mov DWORD PTR 72[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 8[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 20[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 28[esp]
xor ecx,eax
mov DWORD PTR 24[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 3259730800[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 80[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 4[esp]
add ebp,ecx
mov ecx,DWORD PTR 68[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 76[esp]
shr edi,10
add ebx,DWORD PTR 48[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 8[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 12[esp]
xor edx,esi
mov DWORD PTR 76[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 4[esp],esi
xor edx,esi
add ebx,DWORD PTR 16[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 24[esp]
xor esi,ebp
mov DWORD PTR 20[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 3345764771[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 84[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR [esp]
add eax,esi
mov esi,DWORD PTR 72[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 80[esp]
shr edi,10
add ebx,DWORD PTR 52[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 4[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 8[esp]
xor edx,ecx
mov DWORD PTR 80[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR [esp],ecx
xor edx,ecx
add ebx,DWORD PTR 12[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 20[esp]
xor ecx,eax
mov DWORD PTR 16[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 3516065817[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 88[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 28[esp]
add ebp,ecx
mov ecx,DWORD PTR 76[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 84[esp]
shr edi,10
add ebx,DWORD PTR 56[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR [esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 4[esp]
xor edx,esi
mov DWORD PTR 84[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 28[esp],esi
xor edx,esi
add ebx,DWORD PTR 8[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 16[esp]
xor esi,ebp
mov DWORD PTR 12[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 3600352804[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 92[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 24[esp]
add eax,esi
mov esi,DWORD PTR 80[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 88[esp]
shr edi,10
add ebx,DWORD PTR 60[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 28[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR [esp]
xor edx,ecx
mov DWORD PTR 88[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 24[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 4[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 12[esp]
xor ecx,eax
mov DWORD PTR 8[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 4094571909[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 32[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 20[esp]
add ebp,ecx
mov ecx,DWORD PTR 84[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 92[esp]
shr edi,10
add ebx,DWORD PTR 64[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 24[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 28[esp]
xor edx,esi
mov DWORD PTR 92[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 20[esp],esi
xor edx,esi
add ebx,DWORD PTR [esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 8[esp]
xor esi,ebp
mov DWORD PTR 4[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 275423344[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 36[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 16[esp]
add eax,esi
mov esi,DWORD PTR 88[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 32[esp]
shr edi,10
add ebx,DWORD PTR 68[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 20[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 24[esp]
xor edx,ecx
mov DWORD PTR 32[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 16[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 28[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 4[esp]
xor ecx,eax
mov DWORD PTR [esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 430227734[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 40[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 12[esp]
add ebp,ecx
mov ecx,DWORD PTR 92[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 36[esp]
shr edi,10
add ebx,DWORD PTR 72[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 16[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 20[esp]
xor edx,esi
mov DWORD PTR 36[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 12[esp],esi
xor edx,esi
add ebx,DWORD PTR 24[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR [esp]
xor esi,ebp
mov DWORD PTR 28[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 506948616[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 44[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 8[esp]
add eax,esi
mov esi,DWORD PTR 32[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 40[esp]
shr edi,10
add ebx,DWORD PTR 76[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 12[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 16[esp]
xor edx,ecx
mov DWORD PTR 40[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 8[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 20[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 28[esp]
xor ecx,eax
mov DWORD PTR 24[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 659060556[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 48[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 4[esp]
add ebp,ecx
mov ecx,DWORD PTR 36[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 44[esp]
shr edi,10
add ebx,DWORD PTR 80[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 8[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 12[esp]
xor edx,esi
mov DWORD PTR 44[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 4[esp],esi
xor edx,esi
add ebx,DWORD PTR 16[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 24[esp]
xor esi,ebp
mov DWORD PTR 20[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 883997877[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 52[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR [esp]
add eax,esi
mov esi,DWORD PTR 40[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 48[esp]
shr edi,10
add ebx,DWORD PTR 84[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 4[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 8[esp]
xor edx,ecx
mov DWORD PTR 48[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR [esp],ecx
xor edx,ecx
add ebx,DWORD PTR 12[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 20[esp]
xor ecx,eax
mov DWORD PTR 16[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 958139571[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 56[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 28[esp]
add ebp,ecx
mov ecx,DWORD PTR 44[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 52[esp]
shr edi,10
add ebx,DWORD PTR 88[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR [esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 4[esp]
xor edx,esi
mov DWORD PTR 52[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 28[esp],esi
xor edx,esi
add ebx,DWORD PTR 8[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 16[esp]
xor esi,ebp
mov DWORD PTR 12[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1322822218[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 60[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 24[esp]
add eax,esi
mov esi,DWORD PTR 48[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 56[esp]
shr edi,10
add ebx,DWORD PTR 92[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 28[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR [esp]
xor edx,ecx
mov DWORD PTR 56[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 24[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 4[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 12[esp]
xor ecx,eax
mov DWORD PTR 8[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 1537002063[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 64[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 20[esp]
add ebp,ecx
mov ecx,DWORD PTR 52[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 60[esp]
shr edi,10
add ebx,DWORD PTR 32[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 24[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 28[esp]
xor edx,esi
mov DWORD PTR 60[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 20[esp],esi
xor edx,esi
add ebx,DWORD PTR [esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 8[esp]
xor esi,ebp
mov DWORD PTR 4[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 1747873779[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 68[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 16[esp]
add eax,esi
mov esi,DWORD PTR 56[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 64[esp]
shr edi,10
add ebx,DWORD PTR 36[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 20[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 24[esp]
xor edx,ecx
mov DWORD PTR 64[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 16[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 28[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 4[esp]
xor ecx,eax
mov DWORD PTR [esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 1955562222[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 72[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 12[esp]
add ebp,ecx
mov ecx,DWORD PTR 60[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 68[esp]
shr edi,10
add ebx,DWORD PTR 40[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 16[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 20[esp]
xor edx,esi
mov DWORD PTR 68[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 12[esp],esi
xor edx,esi
add ebx,DWORD PTR 24[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR [esp]
xor esi,ebp
mov DWORD PTR 28[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 2024104815[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 76[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 8[esp]
add eax,esi
mov esi,DWORD PTR 64[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 72[esp]
shr edi,10
add ebx,DWORD PTR 44[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 12[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 16[esp]
xor edx,ecx
mov DWORD PTR 72[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 8[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 20[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 28[esp]
xor ecx,eax
mov DWORD PTR 24[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 2227730452[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 80[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 4[esp]
add ebp,ecx
mov ecx,DWORD PTR 68[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 76[esp]
shr edi,10
add ebx,DWORD PTR 48[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 8[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 12[esp]
xor edx,esi
mov DWORD PTR 76[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 4[esp],esi
xor edx,esi
add ebx,DWORD PTR 16[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 24[esp]
xor esi,ebp
mov DWORD PTR 20[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 2361852424[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 84[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR [esp]
add eax,esi
mov esi,DWORD PTR 72[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 80[esp]
shr edi,10
add ebx,DWORD PTR 52[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 4[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 8[esp]
xor edx,ecx
mov DWORD PTR 80[esp],ebx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR [esp],ecx
xor edx,ecx
add ebx,DWORD PTR 12[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 20[esp]
xor ecx,eax
mov DWORD PTR 16[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 2428436474[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 88[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 28[esp]
add ebp,ecx
mov ecx,DWORD PTR 76[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 84[esp]
shr edi,10
add ebx,DWORD PTR 56[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR [esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 4[esp]
xor edx,esi
mov DWORD PTR 84[esp],ebx
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 28[esp],esi
xor edx,esi
add ebx,DWORD PTR 8[esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 16[esp]
xor esi,ebp
mov DWORD PTR 12[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 2756734187[edx*1+ebx]
xor esi,ecx
xor eax,edi
mov ecx,DWORD PTR 92[esp]
ror esi,2
add eax,edx
add edx,DWORD PTR 24[esp]
add eax,esi
mov esi,DWORD PTR 80[esp]
mov ebx,ecx
ror ecx,11
mov edi,esi
ror esi,2
xor ecx,ebx
shr ebx,3
ror ecx,7
xor esi,edi
xor ebx,ecx
ror esi,17
add ebx,DWORD PTR 88[esp]
shr edi,10
add ebx,DWORD PTR 60[esp]
mov ecx,edx
xor edi,esi
mov esi,DWORD PTR 28[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR [esp]
xor edx,ecx
xor esi,edi
ror edx,5
and esi,ecx
mov DWORD PTR 24[esp],ecx
xor edx,ecx
add ebx,DWORD PTR 4[esp]
xor edi,esi
ror edx,6
mov ecx,eax
add ebx,edi
ror ecx,9
mov esi,eax
mov edi,DWORD PTR 12[esp]
xor ecx,eax
mov DWORD PTR 8[esp],eax
xor eax,edi
ror ecx,11
and ebp,eax
lea edx,DWORD PTR 3204031479[edx*1+ebx]
xor ecx,esi
xor ebp,edi
mov esi,DWORD PTR 32[esp]
ror ecx,2
add ebp,edx
add edx,DWORD PTR 20[esp]
add ebp,ecx
mov ecx,DWORD PTR 84[esp]
mov ebx,esi
ror esi,11
mov edi,ecx
ror ecx,2
xor esi,ebx
shr ebx,3
ror esi,7
xor ecx,edi
xor ebx,esi
ror ecx,17
add ebx,DWORD PTR 92[esp]
shr edi,10
add ebx,DWORD PTR 64[esp]
mov esi,edx
xor edi,ecx
mov ecx,DWORD PTR 24[esp]
ror edx,14
add ebx,edi
mov edi,DWORD PTR 28[esp]
xor edx,esi
xor ecx,edi
ror edx,5
and ecx,esi
mov DWORD PTR 20[esp],esi
xor edx,esi
add ebx,DWORD PTR [esp]
xor edi,ecx
ror edx,6
mov esi,ebp
add ebx,edi
ror esi,9
mov ecx,ebp
mov edi,DWORD PTR 8[esp]
xor esi,ebp
mov DWORD PTR 4[esp],ebp
xor ebp,edi
ror esi,11
and eax,ebp
lea edx,DWORD PTR 3329325298[edx*1+ebx]
xor esi,ecx
xor eax,edi
ror esi,2
add eax,edx
add edx,DWORD PTR 16[esp]
add eax,esi
mov esi,DWORD PTR 96[esp]
xor ebp,edi
mov ecx,DWORD PTR 12[esp]
add eax,DWORD PTR [esi]
add ebp,DWORD PTR 4[esi]
add edi,DWORD PTR 8[esi]
add ecx,DWORD PTR 12[esi]
mov DWORD PTR [esi],eax
mov DWORD PTR 4[esi],ebp
mov DWORD PTR 8[esi],edi
mov DWORD PTR 12[esi],ecx
mov DWORD PTR 4[esp],ebp
xor ebp,edi
mov DWORD PTR 8[esp],edi
mov DWORD PTR 12[esp],ecx
mov edi,DWORD PTR 20[esp]
mov ebx,DWORD PTR 24[esp]
mov ecx,DWORD PTR 28[esp]
add edx,DWORD PTR 16[esi]
add edi,DWORD PTR 20[esi]
add ebx,DWORD PTR 24[esi]
add ecx,DWORD PTR 28[esi]
mov DWORD PTR 16[esi],edx
mov DWORD PTR 20[esi],edi
mov DWORD PTR 24[esi],ebx
mov DWORD PTR 28[esi],ecx
mov DWORD PTR 20[esp],edi
mov edi,DWORD PTR 100[esp]
mov DWORD PTR 24[esp],ebx
mov DWORD PTR 28[esp],ecx
cmp edi,DWORD PTR 104[esp]
jb $L009grand_loop
mov esp,DWORD PTR 108[esp]
pop edi
pop esi
pop ebx
pop ebp
ret
_sha256_block_data_order ENDP
.text$ ENDS
.bss SEGMENT 'BSS'
COMM _OPENSSL_ia32cap_P:DWORD:4
.bss ENDS
END
|
{
"language": "Assembly"
}
|
#define __SYSCALL_32BIT_ARG_BYTES 28
#include "SYS.h"
#ifndef SYS_kevent64
#error "SYS_kevent64 not defined. The header files libsyscall is building against do not match syscalls.master."
#endif
#if defined(__i386__) || defined(__x86_64__) || defined(__ppc__) || defined(__arm__) || defined(__arm64__)
__SYSCALL2(_kevent64, kevent64, 7, cerror_nocancel)
#endif
|
{
"language": "Assembly"
}
|
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for arm, Linux
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
B syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-24
BL runtime·entersyscall(SB)
MOVW trap+0(FP), R7
MOVW a1+4(FP), R0
MOVW a2+8(FP), R1
MOVW a3+12(FP), R2
MOVW $0, R3
MOVW $0, R4
MOVW $0, R5
SWI $0
MOVW R0, r1+16(FP)
MOVW $0, R0
MOVW R0, r2+20(FP)
BL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
B syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-24
MOVW trap+0(FP), R7 // syscall entry
MOVW a1+4(FP), R0
MOVW a2+8(FP), R1
MOVW a3+12(FP), R2
SWI $0
MOVW R0, r1+16(FP)
MOVW $0, R0
MOVW R0, r2+20(FP)
RET
TEXT ·seek(SB),NOSPLIT,$0-28
B syscall·seek(SB)
|
{
"language": "Assembly"
}
|
; RUN: %llvm-as -o %t %s
; RUN: %souper -check -souper-only-infer-i1 %t
; Function Attrs: nounwind readnone
declare i32 @llvm.bitreverse.i32(i32) #0
define i1 @foo(i32 %x) {
entry:
%rev = call i32 @llvm.bitreverse.i32(i32 2882343476)
%cmp = icmp eq i32 %rev, 742962133, !expected !1
ret i1 %cmp
}
!1 = !{i1 1}
|
{
"language": "Assembly"
}
|
// RUN: %target-swift-frontend -gnone -emit-ir %s | %FileCheck --check-prefix=CHECK --check-prefix=CHECK-%target-cpu %s -DINT=i%target-ptrsize
// CHECK: [[OPAQUE:%swift.opaque]] = type opaque
// CHECK: [[TYPE:%swift.type]] = type
sil_stage canonical
import Builtin
sil @generic : $@convention(thin) <T> (@in T) -> () {
bb0(%x : $*T):
%y = alloc_stack $T
copy_addr %x to [initialization] %y : $*T
destroy_addr %y : $*T
dealloc_stack %y : $*T
destroy_addr %x : $*T
%0 = tuple ()
return %0 : $()
}
// CHECK: define{{( dllexport)?}}{{( protected)?}} swiftcc void @generic([[OPAQUE]]* noalias nocapture %0, [[TYPE]]* %T) {{.*}} {
// Allocate it.
// CHECK: [[TYPE_ADDR:%.*]] = bitcast %swift.type* %T to i8***
// CHECK-NEXT: [[VWT_ADDR:%.*]] = getelementptr inbounds i8**, i8*** [[TYPE_ADDR]], {{(i32|i64)}} -1
// CHECK-NEXT: [[VWT:%.*]] = load i8**, i8*** [[VWT_ADDR]]
// CHECK-NEXT: [[VWT_CAST:%.*]] = bitcast i8** [[VWT]] to %swift.vwtable*
// CHECK-NEXT: [[SIZE_ADDR:%.*]] = getelementptr inbounds %swift.vwtable, %swift.vwtable* [[VWT_CAST]], i32 0, i32 8
// CHECK-NEXT: [[SIZE:%.*]] = load [[INT]], [[INT]]* [[SIZE_ADDR]]
// CHECK-NEXT: [[Y_ALLOCA:%.*]] = alloca i8, {{.*}} [[SIZE]], align 16
// CHECK-NEXT: call void @llvm.lifetime.start.p0i8({{(i32|i64)}} -1, i8* [[Y_ALLOCA]])
// CHECK-NEXT: [[Y_TMP:%.*]] = bitcast i8* [[Y_ALLOCA]] to %swift.opaque*
// Copy 'x' into 'y'.
// CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8*, i8** [[VWT]], i32 2
// CHECK-NEXT: [[T4:%.*]] = load i8*, i8** [[T3]], align
// CHECK-NEXT: [[INIT_WITH_COPY_FN:%.*]] = bitcast i8* [[T4]] to [[OPAQUE]]* ([[OPAQUE]]*, [[OPAQUE]]*, [[TYPE]]*)*
// CHECK-arm64e-NEXT: ptrtoint i8** [[T3]] to i64
// CHECK-arm64e-NEXT: call i64 @llvm.ptrauth.blend.i64
// CHECK-NEXT: [[Y:%.*]] = call [[OPAQUE]]* [[INIT_WITH_COPY_FN]]([[OPAQUE]]* noalias [[Y_TMP]], [[OPAQUE]]* noalias [[X:%.*]], [[TYPE]]* %T)
// Destroy 'y'.
// CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8*, i8** [[VWT]], i32 1
// CHECK-NEXT: [[T4:%.*]] = load i8*, i8** [[T3]], align
// CHECK-NEXT: [[DESTROY_FN:%.*]] = bitcast i8* [[T4]] to void ([[OPAQUE]]*, [[TYPE]]*)*
// CHECK-arm64e-NEXT: ptrtoint i8** [[T3]] to i64
// CHECK-arm64e-NEXT: call i64 @llvm.ptrauth.blend.i64
// CHECK-NEXT: call void [[DESTROY_FN]]([[OPAQUE]]* noalias [[Y_TMP]], [[TYPE]]* %T)
// Destroy 'x'.
// CHECK-NEXT: call void [[DESTROY_FN]]([[OPAQUE]]* noalias [[X]], [[TYPE]]* %T)
// CHECK-NEXT: [[YBUFLIFE:%.*]] = bitcast [[OPAQUE]]* [[Y_TMP]] to i8*
// CHECK-NEXT: call void @llvm.lifetime.end.p0i8({{(i32|i64)}} -1, i8* [[YBUFLIFE]])
// Return.
// CHECK-NEXT: ret void
sil @generic_with_reuse : $@convention(thin) <T> (@in T) -> () {
bb0(%x : $*T):
%y = alloc_stack $T
copy_addr %x to [initialization] %y : $*T
destroy_addr %y : $*T
copy_addr [take] %x to [initialization] %y : $*T
destroy_addr %y : $*T
dealloc_stack %y : $*T
%0 = tuple ()
return %0 : $()
}
// CHECK: define{{( dllexport)?}}{{( protected)?}} swiftcc void @generic_with_reuse([[OPAQUE]]* noalias nocapture %0, [[TYPE]]* %T) {{.*}} {
// Allocate it.
// CHECK: [[TYPE_ADDR:%.*]] = bitcast %swift.type* %T to i8***
// CHECK-NEXT: [[VWT_ADDR:%.*]] = getelementptr inbounds i8**, i8*** [[TYPE_ADDR]], {{(i32|i64)}} -1
// CHECK-NEXT: [[VWT:%.*]] = load i8**, i8*** [[VWT_ADDR]]
// CHECK-NEXT: [[VWT_CAST:%.*]] = bitcast i8** [[VWT]] to %swift.vwtable*
// CHECK-NEXT: [[SIZE_ADDR:%.*]] = getelementptr inbounds %swift.vwtable, %swift.vwtable* [[VWT_CAST]], i32 0, i32 8
// CHECK-NEXT: [[SIZE:%.*]] = load [[INT]], [[INT]]* [[SIZE_ADDR]]
// CHECK-NEXT: [[Y_ALLOCA:%.*]] = alloca i8, {{.*}} [[SIZE]], align 16
// CHECK-NEXT: call void @llvm.lifetime.start.p0i8({{(i32|i64)}} -1, i8* [[Y_ALLOCA]])
// CHECK-NEXT: [[Y_TMP:%.*]] = bitcast i8* [[Y_ALLOCA]] to %swift.opaque*
// Copy 'x' into 'y'.
// CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8*, i8** [[VWT]], i32 2
// CHECK-NEXT: [[T4:%.*]] = load i8*, i8** [[T3]], align
// CHECK-NEXT: [[INIT_WITH_COPY_FN:%.*]] = bitcast i8* [[T4]] to [[OPAQUE]]* ([[OPAQUE]]*, [[OPAQUE]]*, [[TYPE]]*)*
// CHECK-arm64e-NEXT: ptrtoint i8** [[T3]] to i64
// CHECK-arm64e-NEXT: call i64 @llvm.ptrauth.blend.i64
// CHECK-NEXT: [[Y:%.*]] = call [[OPAQUE]]* [[INIT_WITH_COPY_FN]]([[OPAQUE]]* noalias [[Y_TMP]], [[OPAQUE]]* noalias [[X:%.*]], [[TYPE]]* %T)
// Destroy 'y'.
// CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8*, i8** [[VWT]], i32 1
// CHECK-NEXT: [[T4:%.*]] = load i8*, i8** [[T3]], align
// CHECK-NEXT: [[DESTROY_FN:%.*]] = bitcast i8* [[T4]] to void ([[OPAQUE]]*, [[TYPE]]*)*
// CHECK-arm64e-NEXT: ptrtoint i8** [[T3]] to i64
// CHECK-arm64e-NEXT: call i64 @llvm.ptrauth.blend.i64
// CHECK-NEXT: call void [[DESTROY_FN]]([[OPAQUE]]* noalias [[Y_TMP]], [[TYPE]]* %T)
// Copy 'x' into 'y' again, this time as a take.
// CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8*, i8** [[VWT]], i32 4
// CHECK-NEXT: [[T4:%.*]] = load i8*, i8** [[T3]], align
// CHECK-NEXT: [[TAKE_FN:%.*]] = bitcast i8* [[T4]] to [[OPAQUE]]* ([[OPAQUE]]*, [[OPAQUE]]*, [[TYPE]]*)*
// CHECK-arm64e-NEXT: ptrtoint i8** [[T3]] to i64
// CHECK-arm64e-NEXT: call i64 @llvm.ptrauth.blend.i64
// CHECK-NEXT: call [[OPAQUE]]* [[TAKE_FN]]([[OPAQUE]]* noalias [[Y_TMP]], [[OPAQUE]]* noalias [[X]], [[TYPE]]* %T)
// Destroy 'y'.
// CHECK-NEXT: call void [[DESTROY_FN]]([[OPAQUE]]* noalias [[Y_TMP]], [[TYPE]]* %T)
// CHECK-NEXT: [[YBUFLIFE:%.*]] = bitcast [[OPAQUE]]* [[Y_TMP]] to i8*
// CHECK-NEXT: call void @llvm.lifetime.end.p0i8({{(i32|i64)}} -1, i8* [[YBUFLIFE]])
// Return.
// CHECK-NEXT: ret void
sil @fixed_size : $@convention(thin) (@in Builtin.Int64) -> () {
bb0(%x : $*Builtin.Int64):
%y = alloc_stack $Builtin.Int64
copy_addr %x to [initialization] %y : $*Builtin.Int64
destroy_addr %y : $*Builtin.Int64
dealloc_stack %y : $*Builtin.Int64
destroy_addr %x : $*Builtin.Int64
%0 = tuple ()
return %0 : $()
}
// CHECK-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc void @fixed_size(i64* noalias nocapture dereferenceable(8) %0)
// CHECK: [[XBUF:%.*]] = alloca i64
// CHECK-NEXT: [[XBUFLIFE:%.*]] = bitcast i64* [[XBUF]] to i8*
// CHECK-NEXT: call void @llvm.lifetime.start.p0i8({{(i32|i64)}} 8, i8* [[XBUFLIFE]])
// CHECK-NEXT: load
// CHECK-NEXT: store
// CHECK-NEXT: [[XBUFLIFE:%.*]] = bitcast i64* [[XBUF]] to i8*
// CHECK-NEXT: call void @llvm.lifetime.end.p0i8({{(i32|i64)}} 8, i8* [[XBUFLIFE]])
|
{
"language": "Assembly"
}
|
; RUN: opt -mtriple=amdgcn-amd-amdhsa -basicaa -load-store-vectorizer -S -o - %s | FileCheck %s
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
; CHECK-LABEL: @merge_v2i32_v2i32(
; CHECK: load <4 x i32>
; CHECK: store <4 x i32> zeroinitializer
define void @merge_v2i32_v2i32(<2 x i32> addrspace(1)* nocapture %a, <2 x i32> addrspace(1)* nocapture readonly %b) #0 {
entry:
%a.1 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %a, i64 1
%b.1 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %b, i64 1
%ld.c = load <2 x i32>, <2 x i32> addrspace(1)* %b, align 4
%ld.c.idx.1 = load <2 x i32>, <2 x i32> addrspace(1)* %b.1, align 4
store <2 x i32> zeroinitializer, <2 x i32> addrspace(1)* %a, align 4
store <2 x i32> zeroinitializer, <2 x i32> addrspace(1)* %a.1, align 4
ret void
}
; CHECK-LABEL: @merge_v1i32_v1i32(
; CHECK: load <2 x i32>
; CHECK: store <2 x i32> zeroinitializer
define void @merge_v1i32_v1i32(<1 x i32> addrspace(1)* nocapture %a, <1 x i32> addrspace(1)* nocapture readonly %b) #0 {
entry:
%a.1 = getelementptr inbounds <1 x i32>, <1 x i32> addrspace(1)* %a, i64 1
%b.1 = getelementptr inbounds <1 x i32>, <1 x i32> addrspace(1)* %b, i64 1
%ld.c = load <1 x i32>, <1 x i32> addrspace(1)* %b, align 4
%ld.c.idx.1 = load <1 x i32>, <1 x i32> addrspace(1)* %b.1, align 4
store <1 x i32> zeroinitializer, <1 x i32> addrspace(1)* %a, align 4
store <1 x i32> zeroinitializer, <1 x i32> addrspace(1)* %a.1, align 4
ret void
}
; CHECK-LABEL: @no_merge_v3i32_v3i32(
; CHECK: load <3 x i32>
; CHECK: load <3 x i32>
; CHECK: store <3 x i32> zeroinitializer
; CHECK: store <3 x i32> zeroinitializer
define void @no_merge_v3i32_v3i32(<3 x i32> addrspace(1)* nocapture %a, <3 x i32> addrspace(1)* nocapture readonly %b) #0 {
entry:
%a.1 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %a, i64 1
%b.1 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %b, i64 1
%ld.c = load <3 x i32>, <3 x i32> addrspace(1)* %b, align 4
%ld.c.idx.1 = load <3 x i32>, <3 x i32> addrspace(1)* %b.1, align 4
store <3 x i32> zeroinitializer, <3 x i32> addrspace(1)* %a, align 4
store <3 x i32> zeroinitializer, <3 x i32> addrspace(1)* %a.1, align 4
ret void
}
; CHECK-LABEL: @merge_v2i16_v2i16(
; CHECK: load <4 x i16>
; CHECK: store <4 x i16> zeroinitializer
define void @merge_v2i16_v2i16(<2 x i16> addrspace(1)* nocapture %a, <2 x i16> addrspace(1)* nocapture readonly %b) #0 {
entry:
%a.1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %a, i64 1
%b.1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %b, i64 1
%ld.c = load <2 x i16>, <2 x i16> addrspace(1)* %b, align 4
%ld.c.idx.1 = load <2 x i16>, <2 x i16> addrspace(1)* %b.1, align 4
store <2 x i16> zeroinitializer, <2 x i16> addrspace(1)* %a, align 4
store <2 x i16> zeroinitializer, <2 x i16> addrspace(1)* %a.1, align 4
ret void
}
; Ideally this would be merged
; CHECK-LABEL: @merge_load_i32_v2i16(
; CHECK: load i32,
; CHECK: load <2 x i16>
define void @merge_load_i32_v2i16(i32 addrspace(1)* nocapture %a) #0 {
entry:
%a.1 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 1
%a.1.cast = bitcast i32 addrspace(1)* %a.1 to <2 x i16> addrspace(1)*
%ld.0 = load i32, i32 addrspace(1)* %a
%ld.1 = load <2 x i16>, <2 x i16> addrspace(1)* %a.1.cast
ret void
}
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
|
{
"language": "Assembly"
}
|
B
20
// 0.000000
0x00
// 1.000000
0x7F
// 2.000000
0x7F
// 3.000000
0x7F
// 4.000000
0x7F
// 5.000000
0x7F
// 6.000000
0x7F
// 7.000000
0x7F
// 8.000000
0x7F
// 9.000000
0x7F
// 10.000000
0x7F
// 11.000000
0x7F
// 12.000000
0x7F
// 13.000000
0x7F
// 14.000000
0x7F
// 15.000000
0x7F
// 16.000000
0x7F
// 17.000000
0x7F
// 18.000000
0x7F
// 19.000000
0x7F
|
{
"language": "Assembly"
}
|
R1*6 r2 r2 R1*4 R1*7 r2 r2 R1*4 R1*44 r2. r4 R1*3
|
{
"language": "Assembly"
}
|
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f746xx.s
;* Author : MCD Application Team
;* Version : V1.2.0
;* Date : 30-December-2016
;* Description : STM32F746xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M7 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
{
"language": "Assembly"
}
|
dnl AMD64 mpn_hamdist -- hamming distance.
dnl Copyright 2008, 2010-2012 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C cycles/limb
C AMD K8,K9 n/a
C AMD K10 2
C Intel P4 n/a
C Intel core2 n/a
C Intel corei 2.05
C Intel atom n/a
C VIA nano n/a
C This is very straightforward 2-way unrolled code.
C TODO
C * Write something less basic. It should not be hard to reach 1.5 c/l with
C 4-way unrolling.
define(`ap', `%rdi')
define(`bp', `%rsi')
define(`n', `%rdx')
ABI_SUPPORT(DOS64)
ABI_SUPPORT(STD64)
ASM_START()
TEXT
ALIGN(32)
PROLOGUE(mpn_hamdist)
FUNC_ENTRY(3)
mov (ap), %r8
xor (bp), %r8
lea (ap,n,8), ap C point at A operand end
lea (bp,n,8), bp C point at B operand end
neg n
bt $0, R32(n)
jnc L(2)
L(1): .byte 0xf3,0x49,0x0f,0xb8,0xc0 C popcnt %r8, %rax
xor R32(%r10), R32(%r10)
add $1, n
js L(top)
FUNC_EXIT()
ret
ALIGN(16)
L(2): mov 8(ap,n,8), %r9
.byte 0xf3,0x49,0x0f,0xb8,0xc0 C popcnt %r8, %rax
xor 8(bp,n,8), %r9
.byte 0xf3,0x4d,0x0f,0xb8,0xd1 C popcnt %r9, %r10
add $2, n
js L(top)
lea (%r10, %rax), %rax
FUNC_EXIT()
ret
ALIGN(16)
L(top): mov (ap,n,8), %r8
lea (%r10, %rax), %rax
mov 8(ap,n,8), %r9
xor (bp,n,8), %r8
xor 8(bp,n,8), %r9
.byte 0xf3,0x49,0x0f,0xb8,0xc8 C popcnt %r8, %rcx
lea (%rcx, %rax), %rax
.byte 0xf3,0x4d,0x0f,0xb8,0xd1 C popcnt %r9, %r10
add $2, n
js L(top)
lea (%r10, %rax), %rax
FUNC_EXIT()
ret
EPILOGUE()
|
{
"language": "Assembly"
}
|
; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.8.0"
define i32 @insert-extract-at-zero-idx(i32 %arg, float %fl) {
;CHECK: cost of 0 {{.*}} extract
%A = extractelement <4 x float> undef, i32 0
;CHECK: cost of 1 {{.*}} extract
%B = extractelement <4 x i32> undef, i32 0
;CHECK: cost of 1 {{.*}} extract
%C = extractelement <4 x float> undef, i32 1
;CHECK: cost of 0 {{.*}} extract
%D = extractelement <8 x float> undef, i32 0
;CHECK: cost of 1 {{.*}} extract
%E = extractelement <8 x float> undef, i32 1
;CHECK: cost of 1 {{.*}} extract
%F = extractelement <8 x float> undef, i32 %arg
;CHECK: cost of 0 {{.*}} insert
%G = insertelement <4 x float> undef, float %fl, i32 0
;CHECK: cost of 1 {{.*}} insert
%H = insertelement <4 x float> undef, float %fl, i32 1
;CHECK: cost of 1 {{.*}} insert
%I = insertelement <4 x i32> undef, i32 %arg, i32 0
;CHECK: cost of 0 {{.*}} insert
%J = insertelement <4 x double> undef, double undef, i32 0
;CHECK: cost of 0 {{.*}} insert
%K = insertelement <8 x double> undef, double undef, i32 4
;CHECK: cost of 0 {{.*}} insert
%L = insertelement <16 x double> undef, double undef, i32 8
;CHECK: cost of 1 {{.*}} insert
%M = insertelement <16 x double> undef, double undef, i32 9
ret i32 0
}
|
{
"language": "Assembly"
}
|
# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s
#
# Verify that capitaizled endloops work
{ R0 = mpyi(R0,R0) } : endloop0
{ R0 = mpyi(R0,R0) } : ENDLOOP0
{ R0 = mpyi(R0,R0) }:endloop0
{ R0 = mpyi(R0,R0) } : endloop1
{ R0 = mpyi(R0,R0) } : ENDLOOP1
{ R0 = mpyi(R0,R0) }:endloop1
{ R0 = mpyi(R0,R0) } : endloop0 : endloop1
{ R0 = mpyi(R0,R0) } : ENDLOOP0 : ENDLOOP1
{ R0 = mpyi(R0,R0) }:endloop0:endloop1
# CHECK: r0 = mpyi(r0, r0)
# CHECK: :endloop0
# CHECK: :endloop0
# CHECK: :endloop0
# CHECK: :endloop1
# CHECK: :endloop1
# CHECK: :endloop1
# CHECK: :endloop0 :endloop1
# CHECK: :endloop0 :endloop1
# CHECK: :endloop0 :endloop1
|
{
"language": "Assembly"
}
|
.file "wp-mmx.s"
.text
.globl _whirlpool_block_mmx
.align 4
_whirlpool_block_mmx:
L_whirlpool_block_mmx_begin:
pushl %ebp
pushl %ebx
pushl %esi
pushl %edi
movl 20(%esp),%esi
movl 24(%esp),%edi
movl 28(%esp),%ebp
movl %esp,%eax
subl $148,%esp
andl $-64,%esp
leal 128(%esp),%ebx
movl %esi,(%ebx)
movl %edi,4(%ebx)
movl %ebp,8(%ebx)
movl %eax,16(%ebx)
call L000pic_point
L000pic_point:
popl %ebp
leal L001table-L000pic_point(%ebp),%ebp
xorl %ecx,%ecx
xorl %edx,%edx
movq (%esi),%mm0
movq 8(%esi),%mm1
movq 16(%esi),%mm2
movq 24(%esi),%mm3
movq 32(%esi),%mm4
movq 40(%esi),%mm5
movq 48(%esi),%mm6
movq 56(%esi),%mm7
L002outerloop:
movq %mm0,(%esp)
movq %mm1,8(%esp)
movq %mm2,16(%esp)
movq %mm3,24(%esp)
movq %mm4,32(%esp)
movq %mm5,40(%esp)
movq %mm6,48(%esp)
movq %mm7,56(%esp)
pxor (%edi),%mm0
pxor 8(%edi),%mm1
pxor 16(%edi),%mm2
pxor 24(%edi),%mm3
pxor 32(%edi),%mm4
pxor 40(%edi),%mm5
pxor 48(%edi),%mm6
pxor 56(%edi),%mm7
movq %mm0,64(%esp)
movq %mm1,72(%esp)
movq %mm2,80(%esp)
movq %mm3,88(%esp)
movq %mm4,96(%esp)
movq %mm5,104(%esp)
movq %mm6,112(%esp)
movq %mm7,120(%esp)
xorl %esi,%esi
movl %esi,12(%ebx)
.align 4,0x90
L003round:
movq 4096(%ebp,%esi,8),%mm0
movl (%esp),%eax
movl 4(%esp),%ebx
movzbl %al,%ecx
movzbl %ah,%edx
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm0
movq 7(%ebp,%edi,8),%mm1
movl 8(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
movq 6(%ebp,%esi,8),%mm2
movq 5(%ebp,%edi,8),%mm3
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
movq 4(%ebp,%esi,8),%mm4
movq 3(%ebp,%edi,8),%mm5
movl 12(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
movq 2(%ebp,%esi,8),%mm6
movq 1(%ebp,%edi,8),%mm7
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm1
pxor 7(%ebp,%edi,8),%mm2
movl 16(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm3
pxor 5(%ebp,%edi,8),%mm4
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm5
pxor 3(%ebp,%edi,8),%mm6
movl 20(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm7
pxor 1(%ebp,%edi,8),%mm0
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm2
pxor 7(%ebp,%edi,8),%mm3
movl 24(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm4
pxor 5(%ebp,%edi,8),%mm5
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm6
pxor 3(%ebp,%edi,8),%mm7
movl 28(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm0
pxor 1(%ebp,%edi,8),%mm1
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm3
pxor 7(%ebp,%edi,8),%mm4
movl 32(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm5
pxor 5(%ebp,%edi,8),%mm6
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm7
pxor 3(%ebp,%edi,8),%mm0
movl 36(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm1
pxor 1(%ebp,%edi,8),%mm2
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm4
pxor 7(%ebp,%edi,8),%mm5
movl 40(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm6
pxor 5(%ebp,%edi,8),%mm7
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm0
pxor 3(%ebp,%edi,8),%mm1
movl 44(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm2
pxor 1(%ebp,%edi,8),%mm3
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm5
pxor 7(%ebp,%edi,8),%mm6
movl 48(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm7
pxor 5(%ebp,%edi,8),%mm0
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm1
pxor 3(%ebp,%edi,8),%mm2
movl 52(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm3
pxor 1(%ebp,%edi,8),%mm4
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm6
pxor 7(%ebp,%edi,8),%mm7
movl 56(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm0
pxor 5(%ebp,%edi,8),%mm1
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm2
pxor 3(%ebp,%edi,8),%mm3
movl 60(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm4
pxor 1(%ebp,%edi,8),%mm5
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm7
pxor 7(%ebp,%edi,8),%mm0
movl 64(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm1
pxor 5(%ebp,%edi,8),%mm2
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm3
pxor 3(%ebp,%edi,8),%mm4
movl 68(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm5
pxor 1(%ebp,%edi,8),%mm6
movq %mm0,(%esp)
movq %mm1,8(%esp)
movq %mm2,16(%esp)
movq %mm3,24(%esp)
movq %mm4,32(%esp)
movq %mm5,40(%esp)
movq %mm6,48(%esp)
movq %mm7,56(%esp)
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm0
pxor 7(%ebp,%edi,8),%mm1
movl 72(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm2
pxor 5(%ebp,%edi,8),%mm3
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm4
pxor 3(%ebp,%edi,8),%mm5
movl 76(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm6
pxor 1(%ebp,%edi,8),%mm7
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm1
pxor 7(%ebp,%edi,8),%mm2
movl 80(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm3
pxor 5(%ebp,%edi,8),%mm4
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm5
pxor 3(%ebp,%edi,8),%mm6
movl 84(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm7
pxor 1(%ebp,%edi,8),%mm0
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm2
pxor 7(%ebp,%edi,8),%mm3
movl 88(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm4
pxor 5(%ebp,%edi,8),%mm5
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm6
pxor 3(%ebp,%edi,8),%mm7
movl 92(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm0
pxor 1(%ebp,%edi,8),%mm1
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm3
pxor 7(%ebp,%edi,8),%mm4
movl 96(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm5
pxor 5(%ebp,%edi,8),%mm6
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm7
pxor 3(%ebp,%edi,8),%mm0
movl 100(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm1
pxor 1(%ebp,%edi,8),%mm2
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm4
pxor 7(%ebp,%edi,8),%mm5
movl 104(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm6
pxor 5(%ebp,%edi,8),%mm7
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm0
pxor 3(%ebp,%edi,8),%mm1
movl 108(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm2
pxor 1(%ebp,%edi,8),%mm3
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm5
pxor 7(%ebp,%edi,8),%mm6
movl 112(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm7
pxor 5(%ebp,%edi,8),%mm0
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm1
pxor 3(%ebp,%edi,8),%mm2
movl 116(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm3
pxor 1(%ebp,%edi,8),%mm4
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm6
pxor 7(%ebp,%edi,8),%mm7
movl 120(%esp),%eax
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm0
pxor 5(%ebp,%edi,8),%mm1
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm2
pxor 3(%ebp,%edi,8),%mm3
movl 124(%esp),%ebx
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm4
pxor 1(%ebp,%edi,8),%mm5
shrl $16,%eax
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor (%ebp,%esi,8),%mm7
pxor 7(%ebp,%edi,8),%mm0
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 6(%ebp,%esi,8),%mm1
pxor 5(%ebp,%edi,8),%mm2
shrl $16,%ebx
leal (%ecx,%ecx,1),%esi
movzbl %bl,%ecx
leal (%edx,%edx,1),%edi
movzbl %bh,%edx
pxor 4(%ebp,%esi,8),%mm3
pxor 3(%ebp,%edi,8),%mm4
leal (%ecx,%ecx,1),%esi
movzbl %al,%ecx
leal (%edx,%edx,1),%edi
movzbl %ah,%edx
pxor 2(%ebp,%esi,8),%mm5
pxor 1(%ebp,%edi,8),%mm6
leal 128(%esp),%ebx
movl 12(%ebx),%esi
addl $1,%esi
cmpl $10,%esi
je L004roundsdone
movl %esi,12(%ebx)
movq %mm0,64(%esp)
movq %mm1,72(%esp)
movq %mm2,80(%esp)
movq %mm3,88(%esp)
movq %mm4,96(%esp)
movq %mm5,104(%esp)
movq %mm6,112(%esp)
movq %mm7,120(%esp)
jmp L003round
.align 4,0x90
L004roundsdone:
movl (%ebx),%esi
movl 4(%ebx),%edi
movl 8(%ebx),%eax
pxor (%edi),%mm0
pxor 8(%edi),%mm1
pxor 16(%edi),%mm2
pxor 24(%edi),%mm3
pxor 32(%edi),%mm4
pxor 40(%edi),%mm5
pxor 48(%edi),%mm6
pxor 56(%edi),%mm7
pxor (%esi),%mm0
pxor 8(%esi),%mm1
pxor 16(%esi),%mm2
pxor 24(%esi),%mm3
pxor 32(%esi),%mm4
pxor 40(%esi),%mm5
pxor 48(%esi),%mm6
pxor 56(%esi),%mm7
movq %mm0,(%esi)
movq %mm1,8(%esi)
movq %mm2,16(%esi)
movq %mm3,24(%esi)
movq %mm4,32(%esi)
movq %mm5,40(%esi)
movq %mm6,48(%esi)
movq %mm7,56(%esi)
leal 64(%edi),%edi
subl $1,%eax
jz L005alldone
movl %edi,4(%ebx)
movl %eax,8(%ebx)
jmp L002outerloop
L005alldone:
emms
movl 16(%ebx),%esp
popl %edi
popl %esi
popl %ebx
popl %ebp
ret
.align 6,0x90
L001table:
.byte 24,24,96,24,192,120,48,216
.byte 24,24,96,24,192,120,48,216
.byte 35,35,140,35,5,175,70,38
.byte 35,35,140,35,5,175,70,38
.byte 198,198,63,198,126,249,145,184
.byte 198,198,63,198,126,249,145,184
.byte 232,232,135,232,19,111,205,251
.byte 232,232,135,232,19,111,205,251
.byte 135,135,38,135,76,161,19,203
.byte 135,135,38,135,76,161,19,203
.byte 184,184,218,184,169,98,109,17
.byte 184,184,218,184,169,98,109,17
.byte 1,1,4,1,8,5,2,9
.byte 1,1,4,1,8,5,2,9
.byte 79,79,33,79,66,110,158,13
.byte 79,79,33,79,66,110,158,13
.byte 54,54,216,54,173,238,108,155
.byte 54,54,216,54,173,238,108,155
.byte 166,166,162,166,89,4,81,255
.byte 166,166,162,166,89,4,81,255
.byte 210,210,111,210,222,189,185,12
.byte 210,210,111,210,222,189,185,12
.byte 245,245,243,245,251,6,247,14
.byte 245,245,243,245,251,6,247,14
.byte 121,121,249,121,239,128,242,150
.byte 121,121,249,121,239,128,242,150
.byte 111,111,161,111,95,206,222,48
.byte 111,111,161,111,95,206,222,48
.byte 145,145,126,145,252,239,63,109
.byte 145,145,126,145,252,239,63,109
.byte 82,82,85,82,170,7,164,248
.byte 82,82,85,82,170,7,164,248
.byte 96,96,157,96,39,253,192,71
.byte 96,96,157,96,39,253,192,71
.byte 188,188,202,188,137,118,101,53
.byte 188,188,202,188,137,118,101,53
.byte 155,155,86,155,172,205,43,55
.byte 155,155,86,155,172,205,43,55
.byte 142,142,2,142,4,140,1,138
.byte 142,142,2,142,4,140,1,138
.byte 163,163,182,163,113,21,91,210
.byte 163,163,182,163,113,21,91,210
.byte 12,12,48,12,96,60,24,108
.byte 12,12,48,12,96,60,24,108
.byte 123,123,241,123,255,138,246,132
.byte 123,123,241,123,255,138,246,132
.byte 53,53,212,53,181,225,106,128
.byte 53,53,212,53,181,225,106,128
.byte 29,29,116,29,232,105,58,245
.byte 29,29,116,29,232,105,58,245
.byte 224,224,167,224,83,71,221,179
.byte 224,224,167,224,83,71,221,179
.byte 215,215,123,215,246,172,179,33
.byte 215,215,123,215,246,172,179,33
.byte 194,194,47,194,94,237,153,156
.byte 194,194,47,194,94,237,153,156
.byte 46,46,184,46,109,150,92,67
.byte 46,46,184,46,109,150,92,67
.byte 75,75,49,75,98,122,150,41
.byte 75,75,49,75,98,122,150,41
.byte 254,254,223,254,163,33,225,93
.byte 254,254,223,254,163,33,225,93
.byte 87,87,65,87,130,22,174,213
.byte 87,87,65,87,130,22,174,213
.byte 21,21,84,21,168,65,42,189
.byte 21,21,84,21,168,65,42,189
.byte 119,119,193,119,159,182,238,232
.byte 119,119,193,119,159,182,238,232
.byte 55,55,220,55,165,235,110,146
.byte 55,55,220,55,165,235,110,146
.byte 229,229,179,229,123,86,215,158
.byte 229,229,179,229,123,86,215,158
.byte 159,159,70,159,140,217,35,19
.byte 159,159,70,159,140,217,35,19
.byte 240,240,231,240,211,23,253,35
.byte 240,240,231,240,211,23,253,35
.byte 74,74,53,74,106,127,148,32
.byte 74,74,53,74,106,127,148,32
.byte 218,218,79,218,158,149,169,68
.byte 218,218,79,218,158,149,169,68
.byte 88,88,125,88,250,37,176,162
.byte 88,88,125,88,250,37,176,162
.byte 201,201,3,201,6,202,143,207
.byte 201,201,3,201,6,202,143,207
.byte 41,41,164,41,85,141,82,124
.byte 41,41,164,41,85,141,82,124
.byte 10,10,40,10,80,34,20,90
.byte 10,10,40,10,80,34,20,90
.byte 177,177,254,177,225,79,127,80
.byte 177,177,254,177,225,79,127,80
.byte 160,160,186,160,105,26,93,201
.byte 160,160,186,160,105,26,93,201
.byte 107,107,177,107,127,218,214,20
.byte 107,107,177,107,127,218,214,20
.byte 133,133,46,133,92,171,23,217
.byte 133,133,46,133,92,171,23,217
.byte 189,189,206,189,129,115,103,60
.byte 189,189,206,189,129,115,103,60
.byte 93,93,105,93,210,52,186,143
.byte 93,93,105,93,210,52,186,143
.byte 16,16,64,16,128,80,32,144
.byte 16,16,64,16,128,80,32,144
.byte 244,244,247,244,243,3,245,7
.byte 244,244,247,244,243,3,245,7
.byte 203,203,11,203,22,192,139,221
.byte 203,203,11,203,22,192,139,221
.byte 62,62,248,62,237,198,124,211
.byte 62,62,248,62,237,198,124,211
.byte 5,5,20,5,40,17,10,45
.byte 5,5,20,5,40,17,10,45
.byte 103,103,129,103,31,230,206,120
.byte 103,103,129,103,31,230,206,120
.byte 228,228,183,228,115,83,213,151
.byte 228,228,183,228,115,83,213,151
.byte 39,39,156,39,37,187,78,2
.byte 39,39,156,39,37,187,78,2
.byte 65,65,25,65,50,88,130,115
.byte 65,65,25,65,50,88,130,115
.byte 139,139,22,139,44,157,11,167
.byte 139,139,22,139,44,157,11,167
.byte 167,167,166,167,81,1,83,246
.byte 167,167,166,167,81,1,83,246
.byte 125,125,233,125,207,148,250,178
.byte 125,125,233,125,207,148,250,178
.byte 149,149,110,149,220,251,55,73
.byte 149,149,110,149,220,251,55,73
.byte 216,216,71,216,142,159,173,86
.byte 216,216,71,216,142,159,173,86
.byte 251,251,203,251,139,48,235,112
.byte 251,251,203,251,139,48,235,112
.byte 238,238,159,238,35,113,193,205
.byte 238,238,159,238,35,113,193,205
.byte 124,124,237,124,199,145,248,187
.byte 124,124,237,124,199,145,248,187
.byte 102,102,133,102,23,227,204,113
.byte 102,102,133,102,23,227,204,113
.byte 221,221,83,221,166,142,167,123
.byte 221,221,83,221,166,142,167,123
.byte 23,23,92,23,184,75,46,175
.byte 23,23,92,23,184,75,46,175
.byte 71,71,1,71,2,70,142,69
.byte 71,71,1,71,2,70,142,69
.byte 158,158,66,158,132,220,33,26
.byte 158,158,66,158,132,220,33,26
.byte 202,202,15,202,30,197,137,212
.byte 202,202,15,202,30,197,137,212
.byte 45,45,180,45,117,153,90,88
.byte 45,45,180,45,117,153,90,88
.byte 191,191,198,191,145,121,99,46
.byte 191,191,198,191,145,121,99,46
.byte 7,7,28,7,56,27,14,63
.byte 7,7,28,7,56,27,14,63
.byte 173,173,142,173,1,35,71,172
.byte 173,173,142,173,1,35,71,172
.byte 90,90,117,90,234,47,180,176
.byte 90,90,117,90,234,47,180,176
.byte 131,131,54,131,108,181,27,239
.byte 131,131,54,131,108,181,27,239
.byte 51,51,204,51,133,255,102,182
.byte 51,51,204,51,133,255,102,182
.byte 99,99,145,99,63,242,198,92
.byte 99,99,145,99,63,242,198,92
.byte 2,2,8,2,16,10,4,18
.byte 2,2,8,2,16,10,4,18
.byte 170,170,146,170,57,56,73,147
.byte 170,170,146,170,57,56,73,147
.byte 113,113,217,113,175,168,226,222
.byte 113,113,217,113,175,168,226,222
.byte 200,200,7,200,14,207,141,198
.byte 200,200,7,200,14,207,141,198
.byte 25,25,100,25,200,125,50,209
.byte 25,25,100,25,200,125,50,209
.byte 73,73,57,73,114,112,146,59
.byte 73,73,57,73,114,112,146,59
.byte 217,217,67,217,134,154,175,95
.byte 217,217,67,217,134,154,175,95
.byte 242,242,239,242,195,29,249,49
.byte 242,242,239,242,195,29,249,49
.byte 227,227,171,227,75,72,219,168
.byte 227,227,171,227,75,72,219,168
.byte 91,91,113,91,226,42,182,185
.byte 91,91,113,91,226,42,182,185
.byte 136,136,26,136,52,146,13,188
.byte 136,136,26,136,52,146,13,188
.byte 154,154,82,154,164,200,41,62
.byte 154,154,82,154,164,200,41,62
.byte 38,38,152,38,45,190,76,11
.byte 38,38,152,38,45,190,76,11
.byte 50,50,200,50,141,250,100,191
.byte 50,50,200,50,141,250,100,191
.byte 176,176,250,176,233,74,125,89
.byte 176,176,250,176,233,74,125,89
.byte 233,233,131,233,27,106,207,242
.byte 233,233,131,233,27,106,207,242
.byte 15,15,60,15,120,51,30,119
.byte 15,15,60,15,120,51,30,119
.byte 213,213,115,213,230,166,183,51
.byte 213,213,115,213,230,166,183,51
.byte 128,128,58,128,116,186,29,244
.byte 128,128,58,128,116,186,29,244
.byte 190,190,194,190,153,124,97,39
.byte 190,190,194,190,153,124,97,39
.byte 205,205,19,205,38,222,135,235
.byte 205,205,19,205,38,222,135,235
.byte 52,52,208,52,189,228,104,137
.byte 52,52,208,52,189,228,104,137
.byte 72,72,61,72,122,117,144,50
.byte 72,72,61,72,122,117,144,50
.byte 255,255,219,255,171,36,227,84
.byte 255,255,219,255,171,36,227,84
.byte 122,122,245,122,247,143,244,141
.byte 122,122,245,122,247,143,244,141
.byte 144,144,122,144,244,234,61,100
.byte 144,144,122,144,244,234,61,100
.byte 95,95,97,95,194,62,190,157
.byte 95,95,97,95,194,62,190,157
.byte 32,32,128,32,29,160,64,61
.byte 32,32,128,32,29,160,64,61
.byte 104,104,189,104,103,213,208,15
.byte 104,104,189,104,103,213,208,15
.byte 26,26,104,26,208,114,52,202
.byte 26,26,104,26,208,114,52,202
.byte 174,174,130,174,25,44,65,183
.byte 174,174,130,174,25,44,65,183
.byte 180,180,234,180,201,94,117,125
.byte 180,180,234,180,201,94,117,125
.byte 84,84,77,84,154,25,168,206
.byte 84,84,77,84,154,25,168,206
.byte 147,147,118,147,236,229,59,127
.byte 147,147,118,147,236,229,59,127
.byte 34,34,136,34,13,170,68,47
.byte 34,34,136,34,13,170,68,47
.byte 100,100,141,100,7,233,200,99
.byte 100,100,141,100,7,233,200,99
.byte 241,241,227,241,219,18,255,42
.byte 241,241,227,241,219,18,255,42
.byte 115,115,209,115,191,162,230,204
.byte 115,115,209,115,191,162,230,204
.byte 18,18,72,18,144,90,36,130
.byte 18,18,72,18,144,90,36,130
.byte 64,64,29,64,58,93,128,122
.byte 64,64,29,64,58,93,128,122
.byte 8,8,32,8,64,40,16,72
.byte 8,8,32,8,64,40,16,72
.byte 195,195,43,195,86,232,155,149
.byte 195,195,43,195,86,232,155,149
.byte 236,236,151,236,51,123,197,223
.byte 236,236,151,236,51,123,197,223
.byte 219,219,75,219,150,144,171,77
.byte 219,219,75,219,150,144,171,77
.byte 161,161,190,161,97,31,95,192
.byte 161,161,190,161,97,31,95,192
.byte 141,141,14,141,28,131,7,145
.byte 141,141,14,141,28,131,7,145
.byte 61,61,244,61,245,201,122,200
.byte 61,61,244,61,245,201,122,200
.byte 151,151,102,151,204,241,51,91
.byte 151,151,102,151,204,241,51,91
.byte 0,0,0,0,0,0,0,0
.byte 0,0,0,0,0,0,0,0
.byte 207,207,27,207,54,212,131,249
.byte 207,207,27,207,54,212,131,249
.byte 43,43,172,43,69,135,86,110
.byte 43,43,172,43,69,135,86,110
.byte 118,118,197,118,151,179,236,225
.byte 118,118,197,118,151,179,236,225
.byte 130,130,50,130,100,176,25,230
.byte 130,130,50,130,100,176,25,230
.byte 214,214,127,214,254,169,177,40
.byte 214,214,127,214,254,169,177,40
.byte 27,27,108,27,216,119,54,195
.byte 27,27,108,27,216,119,54,195
.byte 181,181,238,181,193,91,119,116
.byte 181,181,238,181,193,91,119,116
.byte 175,175,134,175,17,41,67,190
.byte 175,175,134,175,17,41,67,190
.byte 106,106,181,106,119,223,212,29
.byte 106,106,181,106,119,223,212,29
.byte 80,80,93,80,186,13,160,234
.byte 80,80,93,80,186,13,160,234
.byte 69,69,9,69,18,76,138,87
.byte 69,69,9,69,18,76,138,87
.byte 243,243,235,243,203,24,251,56
.byte 243,243,235,243,203,24,251,56
.byte 48,48,192,48,157,240,96,173
.byte 48,48,192,48,157,240,96,173
.byte 239,239,155,239,43,116,195,196
.byte 239,239,155,239,43,116,195,196
.byte 63,63,252,63,229,195,126,218
.byte 63,63,252,63,229,195,126,218
.byte 85,85,73,85,146,28,170,199
.byte 85,85,73,85,146,28,170,199
.byte 162,162,178,162,121,16,89,219
.byte 162,162,178,162,121,16,89,219
.byte 234,234,143,234,3,101,201,233
.byte 234,234,143,234,3,101,201,233
.byte 101,101,137,101,15,236,202,106
.byte 101,101,137,101,15,236,202,106
.byte 186,186,210,186,185,104,105,3
.byte 186,186,210,186,185,104,105,3
.byte 47,47,188,47,101,147,94,74
.byte 47,47,188,47,101,147,94,74
.byte 192,192,39,192,78,231,157,142
.byte 192,192,39,192,78,231,157,142
.byte 222,222,95,222,190,129,161,96
.byte 222,222,95,222,190,129,161,96
.byte 28,28,112,28,224,108,56,252
.byte 28,28,112,28,224,108,56,252
.byte 253,253,211,253,187,46,231,70
.byte 253,253,211,253,187,46,231,70
.byte 77,77,41,77,82,100,154,31
.byte 77,77,41,77,82,100,154,31
.byte 146,146,114,146,228,224,57,118
.byte 146,146,114,146,228,224,57,118
.byte 117,117,201,117,143,188,234,250
.byte 117,117,201,117,143,188,234,250
.byte 6,6,24,6,48,30,12,54
.byte 6,6,24,6,48,30,12,54
.byte 138,138,18,138,36,152,9,174
.byte 138,138,18,138,36,152,9,174
.byte 178,178,242,178,249,64,121,75
.byte 178,178,242,178,249,64,121,75
.byte 230,230,191,230,99,89,209,133
.byte 230,230,191,230,99,89,209,133
.byte 14,14,56,14,112,54,28,126
.byte 14,14,56,14,112,54,28,126
.byte 31,31,124,31,248,99,62,231
.byte 31,31,124,31,248,99,62,231
.byte 98,98,149,98,55,247,196,85
.byte 98,98,149,98,55,247,196,85
.byte 212,212,119,212,238,163,181,58
.byte 212,212,119,212,238,163,181,58
.byte 168,168,154,168,41,50,77,129
.byte 168,168,154,168,41,50,77,129
.byte 150,150,98,150,196,244,49,82
.byte 150,150,98,150,196,244,49,82
.byte 249,249,195,249,155,58,239,98
.byte 249,249,195,249,155,58,239,98
.byte 197,197,51,197,102,246,151,163
.byte 197,197,51,197,102,246,151,163
.byte 37,37,148,37,53,177,74,16
.byte 37,37,148,37,53,177,74,16
.byte 89,89,121,89,242,32,178,171
.byte 89,89,121,89,242,32,178,171
.byte 132,132,42,132,84,174,21,208
.byte 132,132,42,132,84,174,21,208
.byte 114,114,213,114,183,167,228,197
.byte 114,114,213,114,183,167,228,197
.byte 57,57,228,57,213,221,114,236
.byte 57,57,228,57,213,221,114,236
.byte 76,76,45,76,90,97,152,22
.byte 76,76,45,76,90,97,152,22
.byte 94,94,101,94,202,59,188,148
.byte 94,94,101,94,202,59,188,148
.byte 120,120,253,120,231,133,240,159
.byte 120,120,253,120,231,133,240,159
.byte 56,56,224,56,221,216,112,229
.byte 56,56,224,56,221,216,112,229
.byte 140,140,10,140,20,134,5,152
.byte 140,140,10,140,20,134,5,152
.byte 209,209,99,209,198,178,191,23
.byte 209,209,99,209,198,178,191,23
.byte 165,165,174,165,65,11,87,228
.byte 165,165,174,165,65,11,87,228
.byte 226,226,175,226,67,77,217,161
.byte 226,226,175,226,67,77,217,161
.byte 97,97,153,97,47,248,194,78
.byte 97,97,153,97,47,248,194,78
.byte 179,179,246,179,241,69,123,66
.byte 179,179,246,179,241,69,123,66
.byte 33,33,132,33,21,165,66,52
.byte 33,33,132,33,21,165,66,52
.byte 156,156,74,156,148,214,37,8
.byte 156,156,74,156,148,214,37,8
.byte 30,30,120,30,240,102,60,238
.byte 30,30,120,30,240,102,60,238
.byte 67,67,17,67,34,82,134,97
.byte 67,67,17,67,34,82,134,97
.byte 199,199,59,199,118,252,147,177
.byte 199,199,59,199,118,252,147,177
.byte 252,252,215,252,179,43,229,79
.byte 252,252,215,252,179,43,229,79
.byte 4,4,16,4,32,20,8,36
.byte 4,4,16,4,32,20,8,36
.byte 81,81,89,81,178,8,162,227
.byte 81,81,89,81,178,8,162,227
.byte 153,153,94,153,188,199,47,37
.byte 153,153,94,153,188,199,47,37
.byte 109,109,169,109,79,196,218,34
.byte 109,109,169,109,79,196,218,34
.byte 13,13,52,13,104,57,26,101
.byte 13,13,52,13,104,57,26,101
.byte 250,250,207,250,131,53,233,121
.byte 250,250,207,250,131,53,233,121
.byte 223,223,91,223,182,132,163,105
.byte 223,223,91,223,182,132,163,105
.byte 126,126,229,126,215,155,252,169
.byte 126,126,229,126,215,155,252,169
.byte 36,36,144,36,61,180,72,25
.byte 36,36,144,36,61,180,72,25
.byte 59,59,236,59,197,215,118,254
.byte 59,59,236,59,197,215,118,254
.byte 171,171,150,171,49,61,75,154
.byte 171,171,150,171,49,61,75,154
.byte 206,206,31,206,62,209,129,240
.byte 206,206,31,206,62,209,129,240
.byte 17,17,68,17,136,85,34,153
.byte 17,17,68,17,136,85,34,153
.byte 143,143,6,143,12,137,3,131
.byte 143,143,6,143,12,137,3,131
.byte 78,78,37,78,74,107,156,4
.byte 78,78,37,78,74,107,156,4
.byte 183,183,230,183,209,81,115,102
.byte 183,183,230,183,209,81,115,102
.byte 235,235,139,235,11,96,203,224
.byte 235,235,139,235,11,96,203,224
.byte 60,60,240,60,253,204,120,193
.byte 60,60,240,60,253,204,120,193
.byte 129,129,62,129,124,191,31,253
.byte 129,129,62,129,124,191,31,253
.byte 148,148,106,148,212,254,53,64
.byte 148,148,106,148,212,254,53,64
.byte 247,247,251,247,235,12,243,28
.byte 247,247,251,247,235,12,243,28
.byte 185,185,222,185,161,103,111,24
.byte 185,185,222,185,161,103,111,24
.byte 19,19,76,19,152,95,38,139
.byte 19,19,76,19,152,95,38,139
.byte 44,44,176,44,125,156,88,81
.byte 44,44,176,44,125,156,88,81
.byte 211,211,107,211,214,184,187,5
.byte 211,211,107,211,214,184,187,5
.byte 231,231,187,231,107,92,211,140
.byte 231,231,187,231,107,92,211,140
.byte 110,110,165,110,87,203,220,57
.byte 110,110,165,110,87,203,220,57
.byte 196,196,55,196,110,243,149,170
.byte 196,196,55,196,110,243,149,170
.byte 3,3,12,3,24,15,6,27
.byte 3,3,12,3,24,15,6,27
.byte 86,86,69,86,138,19,172,220
.byte 86,86,69,86,138,19,172,220
.byte 68,68,13,68,26,73,136,94
.byte 68,68,13,68,26,73,136,94
.byte 127,127,225,127,223,158,254,160
.byte 127,127,225,127,223,158,254,160
.byte 169,169,158,169,33,55,79,136
.byte 169,169,158,169,33,55,79,136
.byte 42,42,168,42,77,130,84,103
.byte 42,42,168,42,77,130,84,103
.byte 187,187,214,187,177,109,107,10
.byte 187,187,214,187,177,109,107,10
.byte 193,193,35,193,70,226,159,135
.byte 193,193,35,193,70,226,159,135
.byte 83,83,81,83,162,2,166,241
.byte 83,83,81,83,162,2,166,241
.byte 220,220,87,220,174,139,165,114
.byte 220,220,87,220,174,139,165,114
.byte 11,11,44,11,88,39,22,83
.byte 11,11,44,11,88,39,22,83
.byte 157,157,78,157,156,211,39,1
.byte 157,157,78,157,156,211,39,1
.byte 108,108,173,108,71,193,216,43
.byte 108,108,173,108,71,193,216,43
.byte 49,49,196,49,149,245,98,164
.byte 49,49,196,49,149,245,98,164
.byte 116,116,205,116,135,185,232,243
.byte 116,116,205,116,135,185,232,243
.byte 246,246,255,246,227,9,241,21
.byte 246,246,255,246,227,9,241,21
.byte 70,70,5,70,10,67,140,76
.byte 70,70,5,70,10,67,140,76
.byte 172,172,138,172,9,38,69,165
.byte 172,172,138,172,9,38,69,165
.byte 137,137,30,137,60,151,15,181
.byte 137,137,30,137,60,151,15,181
.byte 20,20,80,20,160,68,40,180
.byte 20,20,80,20,160,68,40,180
.byte 225,225,163,225,91,66,223,186
.byte 225,225,163,225,91,66,223,186
.byte 22,22,88,22,176,78,44,166
.byte 22,22,88,22,176,78,44,166
.byte 58,58,232,58,205,210,116,247
.byte 58,58,232,58,205,210,116,247
.byte 105,105,185,105,111,208,210,6
.byte 105,105,185,105,111,208,210,6
.byte 9,9,36,9,72,45,18,65
.byte 9,9,36,9,72,45,18,65
.byte 112,112,221,112,167,173,224,215
.byte 112,112,221,112,167,173,224,215
.byte 182,182,226,182,217,84,113,111
.byte 182,182,226,182,217,84,113,111
.byte 208,208,103,208,206,183,189,30
.byte 208,208,103,208,206,183,189,30
.byte 237,237,147,237,59,126,199,214
.byte 237,237,147,237,59,126,199,214
.byte 204,204,23,204,46,219,133,226
.byte 204,204,23,204,46,219,133,226
.byte 66,66,21,66,42,87,132,104
.byte 66,66,21,66,42,87,132,104
.byte 152,152,90,152,180,194,45,44
.byte 152,152,90,152,180,194,45,44
.byte 164,164,170,164,73,14,85,237
.byte 164,164,170,164,73,14,85,237
.byte 40,40,160,40,93,136,80,117
.byte 40,40,160,40,93,136,80,117
.byte 92,92,109,92,218,49,184,134
.byte 92,92,109,92,218,49,184,134
.byte 248,248,199,248,147,63,237,107
.byte 248,248,199,248,147,63,237,107
.byte 134,134,34,134,68,164,17,194
.byte 134,134,34,134,68,164,17,194
.byte 24,35,198,232,135,184,1,79
.byte 54,166,210,245,121,111,145,82
.byte 96,188,155,142,163,12,123,53
.byte 29,224,215,194,46,75,254,87
.byte 21,119,55,229,159,240,74,218
.byte 88,201,41,10,177,160,107,133
.byte 189,93,16,244,203,62,5,103
.byte 228,39,65,139,167,125,149,216
.byte 251,238,124,102,221,23,71,158
.byte 202,45,191,7,173,90,131,51
|
{
"language": "Assembly"
}
|
glabel func_80A5B61C
/* 0032C 80A5B61C 27BDFF90 */ addiu $sp, $sp, 0xFF90 ## $sp = FFFFFF90
/* 00330 80A5B620 AFB00028 */ sw $s0, 0x0028($sp)
/* 00334 80A5B624 00808025 */ or $s0, $a0, $zero ## $s0 = 00000000
/* 00338 80A5B628 AFBF002C */ sw $ra, 0x002C($sp)
/* 0033C 80A5B62C AFA50074 */ sw $a1, 0x0074($sp)
/* 00340 80A5B630 AFA60078 */ sw $a2, 0x0078($sp)
/* 00344 80A5B634 8CC40004 */ lw $a0, 0x0004($a2) ## 00000004
/* 00348 80A5B638 27A60064 */ addiu $a2, $sp, 0x0064 ## $a2 = FFFFFFF4
/* 0034C 80A5B63C 0C296D64 */ jal func_80A5B590
/* 00350 80A5B640 8E050204 */ lw $a1, 0x0204($s0) ## 00000204
/* 00354 80A5B644 8FAF0078 */ lw $t7, 0x0078($sp)
/* 00358 80A5B648 8E190204 */ lw $t9, 0x0204($s0) ## 00000204
/* 0035C 80A5B64C 27AA0040 */ addiu $t2, $sp, 0x0040 ## $t2 = FFFFFFD0
/* 00360 80A5B650 8DF80004 */ lw $t8, 0x0004($t7) ## 00000004
/* 00364 80A5B654 00194080 */ sll $t0, $t9, 2
/* 00368 80A5B658 01194021 */ addu $t0, $t0, $t9
/* 0036C 80A5B65C 00084040 */ sll $t0, $t0, 1
/* 00370 80A5B660 03084821 */ addu $t1, $t8, $t0
/* 00374 80A5B664 85250008 */ lh $a1, 0x0008($t1) ## 00000008
/* 00378 80A5B668 AFAA0010 */ sw $t2, 0x0010($sp)
/* 0037C 80A5B66C 27A40064 */ addiu $a0, $sp, 0x0064 ## $a0 = FFFFFFF4
/* 00380 80A5B670 27A60048 */ addiu $a2, $sp, 0x0048 ## $a2 = FFFFFFD8
/* 00384 80A5B674 0C033209 */ jal func_800CC824
/* 00388 80A5B678 27A70044 */ addiu $a3, $sp, 0x0044 ## $a3 = FFFFFFD4
/* 0038C 80A5B67C C6060024 */ lwc1 $f6, 0x0024($s0) ## 00000024
/* 00390 80A5B680 C7A80048 */ lwc1 $f8, 0x0048($sp)
/* 00394 80A5B684 C7B00044 */ lwc1 $f16, 0x0044($sp)
/* 00398 80A5B688 C612002C */ lwc1 $f18, 0x002C($s0) ## 0000002C
/* 0039C 80A5B68C 46083282 */ mul.s $f10, $f6, $f8
/* 003A0 80A5B690 44802000 */ mtc1 $zero, $f4 ## $f4 = 0.00
/* 003A4 80A5B694 27A60064 */ addiu $a2, $sp, 0x0064 ## $a2 = FFFFFFF4
/* 003A8 80A5B698 46128182 */ mul.s $f6, $f16, $f18
/* 003AC 80A5B69C C7B00040 */ lwc1 $f16, 0x0040($sp)
/* 003B0 80A5B6A0 46065200 */ add.s $f8, $f10, $f6
/* 003B4 80A5B6A4 46104480 */ add.s $f18, $f8, $f16
/* 003B8 80A5B6A8 4612203C */ c.lt.s $f4, $f18
/* 003BC 80A5B6AC 00000000 */ nop
/* 003C0 80A5B6B0 4502000B */ bc1fl .L80A5B6E0
/* 003C4 80A5B6B4 8FB90078 */ lw $t9, 0x0078($sp)
/* 003C8 80A5B6B8 8E0B0204 */ lw $t3, 0x0204($s0) ## 00000204
/* 003CC 80A5B6BC 256C0001 */ addiu $t4, $t3, 0x0001 ## $t4 = 00000001
/* 003D0 80A5B6C0 AE0C0204 */ sw $t4, 0x0204($s0) ## 00000204
/* 003D4 80A5B6C4 8FAE0078 */ lw $t6, 0x0078($sp)
/* 003D8 80A5B6C8 8DCF0000 */ lw $t7, 0x0000($t6) ## 00000000
/* 003DC 80A5B6CC 018F082A */ slt $at, $t4, $t7
/* 003E0 80A5B6D0 54200003 */ bnel $at, $zero, .L80A5B6E0
/* 003E4 80A5B6D4 8FB90078 */ lw $t9, 0x0078($sp)
/* 003E8 80A5B6D8 AE000204 */ sw $zero, 0x0204($s0) ## 00000204
/* 003EC 80A5B6DC 8FB90078 */ lw $t9, 0x0078($sp)
.L80A5B6E0:
/* 003F0 80A5B6E0 8E050204 */ lw $a1, 0x0204($s0) ## 00000204
/* 003F4 80A5B6E4 0C296D64 */ jal func_80A5B590
/* 003F8 80A5B6E8 8F240004 */ lw $a0, 0x0004($t9) ## 00000004
/* 003FC 80A5B6EC 8E050204 */ lw $a1, 0x0204($s0) ## 00000204
/* 00400 80A5B6F0 8FB80078 */ lw $t8, 0x0078($sp)
/* 00404 80A5B6F4 8FA80078 */ lw $t0, 0x0078($sp)
/* 00408 80A5B6F8 24A5FFFF */ addiu $a1, $a1, 0xFFFF ## $a1 = FFFFFFFF
/* 0040C 80A5B6FC 04A10003 */ bgez $a1, .L80A5B70C
/* 00410 80A5B700 27A60058 */ addiu $a2, $sp, 0x0058 ## $a2 = FFFFFFE8
/* 00414 80A5B704 8F050000 */ lw $a1, 0x0000($t8) ## 00000000
/* 00418 80A5B708 24A5FFFF */ addiu $a1, $a1, 0xFFFF ## $a1 = FFFFFFFE
.L80A5B70C:
/* 0041C 80A5B70C 0C296D64 */ jal func_80A5B590
/* 00420 80A5B710 8D040004 */ lw $a0, 0x0004($t0) ## 00000004
/* 00424 80A5B714 C7AA0064 */ lwc1 $f10, 0x0064($sp)
/* 00428 80A5B718 C7A6006C */ lwc1 $f6, 0x006C($sp)
/* 0042C 80A5B71C C60C0024 */ lwc1 $f12, 0x0024($s0) ## 00000024
/* 00430 80A5B720 C60E002C */ lwc1 $f14, 0x002C($s0) ## 0000002C
/* 00434 80A5B724 27A9003C */ addiu $t1, $sp, 0x003C ## $t1 = FFFFFFCC
/* 00438 80A5B728 AFA90018 */ sw $t1, 0x0018($sp)
/* 0043C 80A5B72C 8FA60058 */ lw $a2, 0x0058($sp)
/* 00440 80A5B730 8FA70060 */ lw $a3, 0x0060($sp)
/* 00444 80A5B734 E7AA0010 */ swc1 $f10, 0x0010($sp)
/* 00448 80A5B738 0C03392E */ jal func_800CE4B8
/* 0044C 80A5B73C E7A60014 */ swc1 $f6, 0x0014($sp)
/* 00450 80A5B740 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 00454 80A5B744 8FA50074 */ lw $a1, 0x0074($sp)
/* 00458 80A5B748 27A60064 */ addiu $a2, $sp, 0x0064 ## $a2 = FFFFFFF4
/* 0045C 80A5B74C 0C296D78 */ jal func_80A5B5E0
/* 00460 80A5B750 24070190 */ addiu $a3, $zero, 0x0190 ## $a3 = 00000190
/* 00464 80A5B754 3C0180A6 */ lui $at, %hi(D_80A66854) ## $at = 80A60000
/* 00468 80A5B758 C4306854 */ lwc1 $f16, %lo(D_80A66854)($at)
/* 0046C 80A5B75C C7A8003C */ lwc1 $f8, 0x003C($sp)
/* 00470 80A5B760 3C014302 */ lui $at, 0x4302 ## $at = 43020000
/* 00474 80A5B764 4610403C */ c.lt.s $f8, $f16
/* 00478 80A5B768 00000000 */ nop
/* 0047C 80A5B76C 4502003E */ bc1fl .L80A5B868
/* 00480 80A5B770 8FB90074 */ lw $t9, 0x0074($sp)
/* 00484 80A5B774 C6000090 */ lwc1 $f0, 0x0090($s0) ## 00000090
/* 00488 80A5B778 44812000 */ mtc1 $at, $f4 ## $f4 = 130.00
/* 0048C 80A5B77C 00000000 */ nop
/* 00490 80A5B780 4604003C */ c.lt.s $f0, $f4
/* 00494 80A5B784 00000000 */ nop
/* 00498 80A5B788 45030008 */ bc1tl .L80A5B7AC
/* 0049C 80A5B78C 860E008A */ lh $t6, 0x008A($s0) ## 0000008A
/* 004A0 80A5B790 8E0A032C */ lw $t2, 0x032C($s0) ## 0000032C
/* 004A4 80A5B794 3C014396 */ lui $at, 0x4396 ## $at = 43960000
/* 004A8 80A5B798 914B0017 */ lbu $t3, 0x0017($t2) ## 00000017
/* 004AC 80A5B79C 316C0002 */ andi $t4, $t3, 0x0002 ## $t4 = 00000000
/* 004B0 80A5B7A0 51800016 */ beql $t4, $zero, .L80A5B7FC
/* 004B4 80A5B7A4 44815000 */ mtc1 $at, $f10 ## $f10 = 300.00
/* 004B8 80A5B7A8 860E008A */ lh $t6, 0x008A($s0) ## 0000008A
.L80A5B7AC:
/* 004BC 80A5B7AC 860D0032 */ lh $t5, 0x0032($s0) ## 00000032
/* 004C0 80A5B7B0 01CD2023 */ subu $a0, $t6, $t5
/* 004C4 80A5B7B4 00042400 */ sll $a0, $a0, 16
/* 004C8 80A5B7B8 0C01DE1C */ jal Math_Sins
## sins?
/* 004CC 80A5B7BC 00042403 */ sra $a0, $a0, 16
/* 004D0 80A5B7C0 44809000 */ mtc1 $zero, $f18 ## $f18 = 0.00
/* 004D4 80A5B7C4 00000000 */ nop
/* 004D8 80A5B7C8 4600903C */ c.lt.s $f18, $f0
/* 004DC 80A5B7CC 00000000 */ nop
/* 004E0 80A5B7D0 45020006 */ bc1fl .L80A5B7EC
/* 004E4 80A5B7D4 86180032 */ lh $t8, 0x0032($s0) ## 00000032
/* 004E8 80A5B7D8 860F0032 */ lh $t7, 0x0032($s0) ## 00000032
/* 004EC 80A5B7DC 25F9FEE8 */ addiu $t9, $t7, 0xFEE8 ## $t9 = FFFFFEE8
/* 004F0 80A5B7E0 1000001E */ beq $zero, $zero, .L80A5B85C
/* 004F4 80A5B7E4 A6190032 */ sh $t9, 0x0032($s0) ## 00000032
/* 004F8 80A5B7E8 86180032 */ lh $t8, 0x0032($s0) ## 00000032
.L80A5B7EC:
/* 004FC 80A5B7EC 27080118 */ addiu $t0, $t8, 0x0118 ## $t0 = 00000118
/* 00500 80A5B7F0 1000001A */ beq $zero, $zero, .L80A5B85C
/* 00504 80A5B7F4 A6080032 */ sh $t0, 0x0032($s0) ## 00000032
/* 00508 80A5B7F8 44815000 */ mtc1 $at, $f10 ## $f10 = 0.00
.L80A5B7FC:
/* 0050C 80A5B7FC 00000000 */ nop
/* 00510 80A5B800 460A003C */ c.lt.s $f0, $f10
/* 00514 80A5B804 00000000 */ nop
/* 00518 80A5B808 45020015 */ bc1fl .L80A5B860
/* 0051C 80A5B80C 860F0032 */ lh $t7, 0x0032($s0) ## 00000032
/* 00520 80A5B810 8609008A */ lh $t1, 0x008A($s0) ## 0000008A
/* 00524 80A5B814 860A0032 */ lh $t2, 0x0032($s0) ## 00000032
/* 00528 80A5B818 012A2023 */ subu $a0, $t1, $t2
/* 0052C 80A5B81C 00042400 */ sll $a0, $a0, 16
/* 00530 80A5B820 0C01DE1C */ jal Math_Sins
## sins?
/* 00534 80A5B824 00042403 */ sra $a0, $a0, 16
/* 00538 80A5B828 44803000 */ mtc1 $zero, $f6 ## $f6 = 0.00
/* 0053C 80A5B82C 00000000 */ nop
/* 00540 80A5B830 4600303C */ c.lt.s $f6, $f0
/* 00544 80A5B834 00000000 */ nop
/* 00548 80A5B838 45020006 */ bc1fl .L80A5B854
/* 0054C 80A5B83C 860E0032 */ lh $t6, 0x0032($s0) ## 00000032
/* 00550 80A5B840 860B0032 */ lh $t3, 0x0032($s0) ## 00000032
/* 00554 80A5B844 256C0118 */ addiu $t4, $t3, 0x0118 ## $t4 = 00000118
/* 00558 80A5B848 10000004 */ beq $zero, $zero, .L80A5B85C
/* 0055C 80A5B84C A60C0032 */ sh $t4, 0x0032($s0) ## 00000032
/* 00560 80A5B850 860E0032 */ lh $t6, 0x0032($s0) ## 00000032
.L80A5B854:
/* 00564 80A5B854 25CDFEE8 */ addiu $t5, $t6, 0xFEE8 ## $t5 = FFFFFEE8
/* 00568 80A5B858 A60D0032 */ sh $t5, 0x0032($s0) ## 00000032
.L80A5B85C:
/* 0056C 80A5B85C 860F0032 */ lh $t7, 0x0032($s0) ## 00000032
.L80A5B860:
/* 00570 80A5B860 A60F00B6 */ sh $t7, 0x00B6($s0) ## 000000B6
/* 00574 80A5B864 8FB90074 */ lw $t9, 0x0074($sp)
.L80A5B868:
/* 00578 80A5B868 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 0057C 80A5B86C 0C00B6E3 */ jal func_8002DB8C
/* 00580 80A5B870 8F251C44 */ lw $a1, 0x1C44($t9) ## 00001C44
/* 00584 80A5B874 8FB80074 */ lw $t8, 0x0074($sp)
/* 00588 80A5B878 E7A00050 */ swc1 $f0, 0x0050($sp)
/* 0058C 80A5B87C 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 00590 80A5B880 0C00B69E */ jal func_8002DA78
/* 00594 80A5B884 8F051C44 */ lw $a1, 0x1C44($t8) ## 00001C44
/* 00598 80A5B888 3C014348 */ lui $at, 0x4348 ## $at = 43480000
/* 0059C 80A5B88C 44814000 */ mtc1 $at, $f8 ## $f8 = 200.00
/* 005A0 80A5B890 C7B00050 */ lwc1 $f16, 0x0050($sp)
/* 005A4 80A5B894 86080032 */ lh $t0, 0x0032($s0) ## 00000032
/* 005A8 80A5B898 4608803E */ c.le.s $f16, $f8
/* 005AC 80A5B89C 00482023 */ subu $a0, $v0, $t0
/* 005B0 80A5B8A0 00042400 */ sll $a0, $a0, 16
/* 005B4 80A5B8A4 00042403 */ sra $a0, $a0, 16
/* 005B8 80A5B8A8 45030014 */ bc1tl .L80A5B8FC
/* 005BC 80A5B8AC C6000068 */ lwc1 $f0, 0x0068($s0) ## 00000068
/* 005C0 80A5B8B0 0C01DE1C */ jal Math_Sins
## sins?
/* 005C4 80A5B8B4 A7A4004E */ sh $a0, 0x004E($sp)
/* 005C8 80A5B8B8 3C0180A6 */ lui $at, %hi(D_80A66858) ## $at = 80A60000
/* 005CC 80A5B8BC C4246858 */ lwc1 $f4, %lo(D_80A66858)($at)
/* 005D0 80A5B8C0 46000005 */ abs.s $f0, $f0
/* 005D4 80A5B8C4 87A4004E */ lh $a0, 0x004E($sp)
/* 005D8 80A5B8C8 4604003C */ c.lt.s $f0, $f4
/* 005DC 80A5B8CC 00000000 */ nop
/* 005E0 80A5B8D0 4502001D */ bc1fl .L80A5B948
/* 005E4 80A5B8D4 8FAB0078 */ lw $t3, 0x0078($sp)
/* 005E8 80A5B8D8 0C01DE0D */ jal Math_Coss
## coss?
/* 005EC 80A5B8DC 00000000 */ nop
/* 005F0 80A5B8E0 44809000 */ mtc1 $zero, $f18 ## $f18 = 0.00
/* 005F4 80A5B8E4 00000000 */ nop
/* 005F8 80A5B8E8 4600903C */ c.lt.s $f18, $f0
/* 005FC 80A5B8EC 00000000 */ nop
/* 00600 80A5B8F0 45020015 */ bc1fl .L80A5B948
/* 00604 80A5B8F4 8FAB0078 */ lw $t3, 0x0078($sp)
/* 00608 80A5B8F8 C6000068 */ lwc1 $f0, 0x0068($s0) ## 00000068
.L80A5B8FC:
/* 0060C 80A5B8FC C60A0398 */ lwc1 $f10, 0x0398($s0) ## 00000398
/* 00610 80A5B900 3C0180A6 */ lui $at, %hi(D_80A66860) ## $at = 80A60000
/* 00614 80A5B904 460A003C */ c.lt.s $f0, $f10
/* 00618 80A5B908 00000000 */ nop
/* 0061C 80A5B90C 45000006 */ bc1f .L80A5B928
/* 00620 80A5B910 00000000 */ nop
/* 00624 80A5B914 3C0180A6 */ lui $at, %hi(D_80A6685C) ## $at = 80A60000
/* 00628 80A5B918 C426685C */ lwc1 $f6, %lo(D_80A6685C)($at)
/* 0062C 80A5B91C 46060200 */ add.s $f8, $f0, $f6
/* 00630 80A5B920 10000004 */ beq $zero, $zero, .L80A5B934
/* 00634 80A5B924 E6080068 */ swc1 $f8, 0x0068($s0) ## 00000068
.L80A5B928:
/* 00638 80A5B928 C4306860 */ lwc1 $f16, %lo(D_80A66860)($at)
/* 0063C 80A5B92C 46100101 */ sub.s $f4, $f0, $f16
/* 00640 80A5B930 E6040068 */ swc1 $f4, 0x0068($s0) ## 00000068
.L80A5B934:
/* 00644 80A5B934 96090394 */ lhu $t1, 0x0394($s0) ## 00000394
/* 00648 80A5B938 352A0001 */ ori $t2, $t1, 0x0001 ## $t2 = 00000001
/* 0064C 80A5B93C 1000001D */ beq $zero, $zero, .L80A5B9B4
/* 00650 80A5B940 A60A0394 */ sh $t2, 0x0394($s0) ## 00000394
/* 00654 80A5B944 8FAB0078 */ lw $t3, 0x0078($sp)
.L80A5B948:
/* 00658 80A5B948 8E0E0204 */ lw $t6, 0x0204($s0) ## 00000204
/* 0065C 80A5B94C C6000068 */ lwc1 $f0, 0x0068($s0) ## 00000068
/* 00660 80A5B950 8D6C0004 */ lw $t4, 0x0004($t3) ## 00000004
/* 00664 80A5B954 000E6880 */ sll $t5, $t6, 2
/* 00668 80A5B958 01AE6821 */ addu $t5, $t5, $t6
/* 0066C 80A5B95C 000D6840 */ sll $t5, $t5, 1
/* 00670 80A5B960 018D7821 */ addu $t7, $t4, $t5
/* 00674 80A5B964 85F90006 */ lh $t9, 0x0006($t7) ## 00000006
/* 00678 80A5B968 3C0180A6 */ lui $at, %hi(D_80A66868) ## $at = 80A60000
/* 0067C 80A5B96C 44999000 */ mtc1 $t9, $f18 ## $f18 = 0.00
/* 00680 80A5B970 00000000 */ nop
/* 00684 80A5B974 468092A0 */ cvt.s.w $f10, $f18
/* 00688 80A5B978 460A003C */ c.lt.s $f0, $f10
/* 0068C 80A5B97C 00000000 */ nop
/* 00690 80A5B980 45000006 */ bc1f .L80A5B99C
/* 00694 80A5B984 00000000 */ nop
/* 00698 80A5B988 3C0180A6 */ lui $at, %hi(D_80A66864) ## $at = 80A60000
/* 0069C 80A5B98C C4266864 */ lwc1 $f6, %lo(D_80A66864)($at)
/* 006A0 80A5B990 46060200 */ add.s $f8, $f0, $f6
/* 006A4 80A5B994 10000004 */ beq $zero, $zero, .L80A5B9A8
/* 006A8 80A5B998 E6080068 */ swc1 $f8, 0x0068($s0) ## 00000068
.L80A5B99C:
/* 006AC 80A5B99C C4306868 */ lwc1 $f16, %lo(D_80A66868)($at)
/* 006B0 80A5B9A0 46100101 */ sub.s $f4, $f0, $f16
/* 006B4 80A5B9A4 E6040068 */ swc1 $f4, 0x0068($s0) ## 00000068
.L80A5B9A8:
/* 006B8 80A5B9A8 96180394 */ lhu $t8, 0x0394($s0) ## 00000394
/* 006BC 80A5B9AC 3308FFFE */ andi $t0, $t8, 0xFFFE ## $t0 = 00000000
/* 006C0 80A5B9B0 A6080394 */ sh $t0, 0x0394($s0) ## 00000394
.L80A5B9B4:
/* 006C4 80A5B9B4 8FBF002C */ lw $ra, 0x002C($sp)
/* 006C8 80A5B9B8 8FB00028 */ lw $s0, 0x0028($sp)
/* 006CC 80A5B9BC 27BD0070 */ addiu $sp, $sp, 0x0070 ## $sp = 00000000
/* 006D0 80A5B9C0 03E00008 */ jr $ra
/* 006D4 80A5B9C4 00000000 */ nop
|
{
"language": "Assembly"
}
|
/*++
Copyright (c) 2014 Minoca Corp.
This file is licensed under the terms of the GNU General Public License
version 3. Alternative licensing terms are available. Contact
info@minocacorp.com for details. See the LICENSE file at the root of this
project for complete licensing information.
Module Name:
commsup.S
Abstract:
This module implements assembly-based architecture support routines common
to all ARM platforms.
Author:
Chris Stevens 20-Mar-2014
Environment:
Firmware
--*/
//
// ------------------------------------------------------------------- Includes
//
#include <minoca/kernel/arm.inc>
//
// ---------------------------------------------------------------- Definitions
//
//
// ---------------------------------------------------------------------- Code
//
ASSEMBLY_FILE_HEADER
//
// VOID
// EfipInitializeExceptionStacks (
// PVOID ExceptionStacksBase,
// ULONG ExceptionStackSize
// )
//
/*++
Routine Description:
This routine initializes the stack pointer for all privileged ARM modes. It
switches into each mode and initializes the banked r13. This function
should be called with interrupts disabled and returns with interrupts
disabled.
Arguments:
ExceptionStacksBase - Supplies a pointer to the lowest address that should
be used for exception stacks. Each stack takes up 16 bytes and there are
4 modes, so at least 64 bytes are needed.
ExceptionStackSize - Supplies the size of each exception stack.
Return Value:
None.
--*/
FUNCTION EfipInitializeExceptionStacks
//
// Load R1 with an individual stack size.
//
add %r0, %r0, %r1
//
// Disable interrupts and switch into IRQ mode. Note that this also
// clobbers the flags register.
//
mov %r2, #(PSR_FLAG_IRQ | ARM_MODE_IRQ)
msr CPSR_cxsf, %r2
mov %sp, %r0
add %r0, %r0, %r1
//
// Initialize the FIQ stack.
//
mov %r2, #(PSR_FLAG_IRQ | ARM_MODE_FIQ)
msr CPSR_cxsf, %r2
mov %sp, %r0
add %r0, %r0, %r1
//
// Initialize the undefined instruction stack.
//
mov %r2, #(PSR_FLAG_IRQ | ARM_MODE_UNDEF)
msr CPSR_cxsf, %r2
mov %sp, %r0
add %r0, %r0, %r1
//
// Initialize the data fetch abort stack.
//
mov %r2, #(PSR_FLAG_IRQ | ARM_MODE_ABORT)
msr CPSR_cxsf, %r2
mov %sp, %r0
//
// Switch back to SVC mode and return.
//
mov %r2, #(PSR_FLAG_IRQ | ARM_MODE_SVC)
msr CPSR_cxsf, %r2
bx %lr
END_FUNCTION EfipInitializeExceptionStacks
//
// BOOLEAN
// EfiDisableInterrupts (
// VOID
// )
//
/*++
Routine Description:
This routine disables all interrupts on the current processor.
Arguments:
None.
Return Value:
TRUE if interrupts were previously enabled on the processor.
FALSE if interrupts were not previously enabled on the processor.
--*/
FUNCTION EfiDisableInterrupts
mrs %r1, CPSR @ Get the status register.
cpsid i @ Disable interrupts.
mov %r0, #0 @ Assume interrupts disabled.
tst %r1, #PSR_FLAG_IRQ @ AND the interrupt flag.
IT(eq) @ If the zero flag is set...
moveq %r0, #1 @ Interrupts were enabled.
bx %lr @ Return.
END_FUNCTION EfiDisableInterrupts
//
// VOID
// EfiEnableInterrupts (
// VOID
// )
//
/*++
Routine Description:
This routine enables interrupts on the current processor.
Arguments:
None.
Return Value:
None.
--*/
FUNCTION EfiEnableInterrupts
cpsie i @ Enable interrupts.
bx %lr @
END_FUNCTION EfiEnableInterrupts
//
// BOOLEAN
// EfiAreInterruptsEnabled (
// VOID
// )
//
/*++
Routine Description:
This routine determines whether or not interrupts are currently enabled
on the processor.
Arguments:
None.
Return Value:
TRUE if interrupts are enabled in the processor.
FALSE if interrupts are globally disabled.
--*/
FUNCTION EfiAreInterruptsEnabled
mrs %r1, CPSR @ Get the status register.
mov %r0, #0 @ Assume interrupts disabled.
tst %r1, #PSR_FLAG_IRQ @ AND the interrupt flag.
IT(eq) @ If the zero flag is set...
moveq %r0, #1 @ Interrupts were enabled.
bx %lr @ Return.
END_FUNCTION EfiAreInterruptsEnabled
//
// VOID
// EfipUndefinedInstructionEntry (
// VOID
// )
//
/*++
Routine Description:
This routine directly handles an exception generated by an undefined
instruction. It uses a largely separate code path from normal exceptions
to avoid recursively breaking into the debugger.
Arguments:
None.
Return Value:
None.
--*/
FUNCTION EfipUndefinedInstructionEntry
//
// Save state and create a trap frame.
//
ARM_ENTER_INTERRUPT
//
// Call the main dispatch routine routine with a pointer to the trap frame
// as the only parameter.
//
mov %r0, %sp
blx EfipDispatchUndefinedInstructionException
//
// Restore state and return.
//
ARM_EXIT_INTERRUPT
END_FUNCTION EfipUndefinedInstructionEntry
//
// VOID
// EfipSoftwareInterruptEntry (
// VOID
// )
//
/*++
Routine Description:
This routine directly handles an exception generated by a software
interrupt (a system call).
Arguments:
None.
Return Value:
None.
--*/
FUNCTION EfipSoftwareInterruptEntry
b EfipCommonInterruptEntry @ This is neither expected nor handled.
END_FUNCTION EfipSoftwareInterruptEntry
//
// VOID
// EfipPrefetchAbortEntry (
// VOID
// )
//
/*++
Routine Description:
This routine directly handles an exception generated by a prefetch abort
(page fault).
Arguments:
None.
Return Value:
None.
--*/
FUNCTION EfipPrefetchAbortEntry
sub %lr, %lr, #4 @ Prefetches go too far by 4.
//
// Save state and create a trap frame.
//
ARM_ENTER_INTERRUPT
//
// Call the main dispatch routine routine with a pointer to the trap frame
// and 1 to indicate a prefetch abort.
//
mov %r0, %sp
mov %r1, #1
blx EfipDispatchException
//
// Restore state and return.
//
ARM_EXIT_INTERRUPT
END_FUNCTION EfipPrefetchAbortEntry
//
// VOID
// EfipDataAbortEntry (
// VOID
// )
//
/*++
Routine Description:
This routine directly handles an exception generated by a data abort (page
fault).
Arguments:
None.
Return Value:
None.
--*/
FUNCTION EfipDataAbortEntry
sub %lr, %lr, #8 @ Data aborts go too far by 8.
//
// Save state and create a trap frame.
//
ARM_ENTER_INTERRUPT
//
// Call the main dispatch routine routine with a pointer to the trap frame
// and 0 to indicate a prefetch abort.
//
mov %r0, %sp
mov %r1, #0
blx EfipDispatchException
//
// Restore state and return.
//
ARM_EXIT_INTERRUPT
END_FUNCTION EfipDataAbortEntry
//
// VOID
// EfipIrqEntry (
// VOID
// )
//
/*++
Routine Description:
This routine directly handles an exception generated by an external
interrupt on the IRQ pin.
Arguments:
None.
Return Value:
None.
--*/
FUNCTION EfipIrqEntry
b EfipCommonInterruptEntry
END_FUNCTION EfipIrqEntry
//
// VOID
// EfipFiqEntry (
// VOID
// )
//
/*++
Routine Description:
This routine directly handles an exception generated by an external
interrupt on the FIQ pin.
Arguments:
None.
Return Value:
None.
--*/
FUNCTION EfipFiqEntry
b EfipCommonInterruptEntry
END_FUNCTION EfipFiqEntry
//
// VOID
// EfipCpuid (
// PARM_CPUID Features
// )
//
/*++
Routine Description:
This routine returns the set of processor features present on the current
processor.
Arguments:
Features - Supplies a pointer where the processor feature register values
will be returned.
Return Value:
None.
--*/
FUNCTION EfipCpuid
mrc p15, 0, %r1, c0, c1, 0 @ Get ID_PFR0.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c1, 1 @ Get ID_PFR1.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c1, 2 @ Get ID_DFR0.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c1, 3 @ Get ID_AFR0.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c1, 4 @ Get ID_MMFR0.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c1, 5 @ Get ID_MMFR1.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c1, 6 @ Get ID_MMFR2.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c1, 7 @ Get ID_MMFR3.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c2, 0 @ Get ID_IDAR0.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c2, 1 @ Get ID_IDAR1.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c2, 2 @ Get ID_IDAR2.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c2, 3 @ Get ID_IDAR3.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c2, 4 @ Get ID_IDAR4.
str %r1, [%r0], #4 @ Save it.
mrc p15, 0, %r1, c0, c2, 5 @ Get ID_IDAR5.
str %r1, [%r0], #4 @ Save it.
bx %lr @ Return!
END_FUNCTION EfipCpuid
//
// EFIAPI
// UINTN
// EfipArchSetJump (
// PEFI_JUMP_BUFFER JumpBuffer
// )
//
/*++
Routine Description:
This routine sets the context in the given jump buffer such that when
long jump is called, execution continues at the return value from this
routine with a non-zero return value.
Arguments:
JumpBuffer - Supplies a pointer where the architecture-specific context
will be saved.
Return Value:
0 upon the initial return from this routine.
Non-zero when returning as the target of a long jump.
--*/
FUNCTION EfipArchSetJump
mov %r3, %r13 @ Save the stack pointer.
stmia %r0, {%r3-%r12,%r14} @ Save the non-volatile registers.
eor %r0, %r0, %r0 @ Zero out the return value.
bx %lr @ Return.
END_FUNCTION EfipArchSetJump
//
// EFIAPI
// VOID
// EfipArchLongJump (
// PEFI_JUMP_BUFFER JumpBuffer,
// UINTN Value
// )
//
/*++
Routine Description:
This routine restores machine context to the state it was in when the
set jump that saved into the given jump buffer was called. The return
value will be set to the given value.
Arguments:
JumpBuffer - Supplies a pointer to the context to restore.
Value - Supplies the new return value to set from set jump. This should not
be zero, otherwise the caller of set jump will not be able to
differentiate it from its initial return.
Return Value:
This routine does not return.
--*/
FUNCTION EfipArchLongJump
ldmia %r0, {%r3-%r12,%r14} @ Restore the non-volatile registers.
mov %r13, %r3 @ Restore the stack pointer.
mov %r0, %r1 @ Move the return value into place.
bx %lr @ Return.
END_FUNCTION EfipArchLongJump
//
// ULONG
// ArGetSystemControlRegister (
// VOID
// )
//
/*++
Routine Description:
This routine returns the MMU system control register (SCTLR).
Arguments:
None.
Return Value:
Returns the current SCTLR value.
--*/
FUNCTION ArGetSystemControlRegister
mrc p15, 0, %r0, %cr1, %cr0, 0 @ Get the SCTLR.
bx %lr @ Return.
END_FUNCTION ArGetSystemControlRegister
//
// VOID
// ArSetSystemControlRegister (
// ULONG NewValue
// )
//
/*++
Routine Description:
This routine sets the MMU system control register (SCTLR).
Arguments:
NewValue - Supplies the value to set as the new MMU SCTLR.
Return Value:
None.
--*/
FUNCTION ArSetSystemControlRegister
mcr p15, 0, %r0, %cr1, %cr0, 0 @ Set the SCTLR.
bx %lr @ Return.
END_FUNCTION ArSetSystemControlRegister
//
// ULONG
// ArGetAuxiliaryControlRegister (
// VOID
// )
//
/*++
Routine Description:
This routine returns the auxiliary system control register (ACTLR).
Arguments:
None.
Return Value:
Returns the current value.
--*/
FUNCTION ArGetAuxiliaryControlRegister
mrc p15, 0, %r0, %cr1, %cr0, 1
bx %lr
END_FUNCTION ArGetAuxiliaryControlRegister
//
// VOID
// ArSetAuxiliaryControlRegister (
// ULONG NewValue
// )
//
/*++
Routine Description:
This routine sets the auxiliary system control register (ACTLR).
Arguments:
NewValue - Supplies the value to set.
Return Value:
None.
--*/
FUNCTION ArSetAuxiliaryControlRegister
mcr p15, 0, %r0, %cr1, %cr0, 1
bx %lr
END_FUNCTION ArSetAuxiliaryControlRegister
//
// PVOID
// ArGetVectorBaseAddress (
// VOID
// )
//
/*++
Routine Description:
This routine gets the vector base address register (VBAR) which determines
where the ARM exception vector table starts.
Arguments:
None.
Return Value:
Returns the current VBAR.
--*/
FUNCTION ArGetVectorBaseAddress
mrc p15, 0, %r0, c12, c0, 0
bx %lr
END_FUNCTION ArGetVectorBaseAddress
//
// VOID
// ArSetVectorBaseAddress (
// PVOID VectorBaseAddress
// )
//
/*++
Routine Description:
This routine sets the vector base address register (VBAR) which determines
where the ARM exception vector table starts.
Arguments:
VectorBaseAddress - Supplies a pointer to the ARM exception vector base
address. This value must be 32-byte aligned.
Return Value:
None.
--*/
FUNCTION ArSetVectorBaseAddress
mcr p15, 0, %r0, c12, c0, 0 @ Set VBAR.
bx %lr @ Return.
END_FUNCTION ArSetVectorBaseAddress
//
// PVOID
// ArGetDataFaultingAddress (
// VOID
// )
//
/*++
Routine Description:
This routine determines which address caused a data abort.
Arguments:
None.
Return Value:
Returns the faulting address.
--*/
FUNCTION ArGetDataFaultingAddress
mrc p15, 0, %r0, %cr6, %cr0, 0 @ Get the combined/data FAR.
bx %lr @
END_FUNCTION ArGetDataFaultingAddress
//
// VOID
// ArSetDataFaultingAddress (
// PVOID Value
// )
//
/*++
Routine Description:
This routine sets the data faulting address register (DFAR).
Arguments:
Value - Supplies the value to set.
Return Value:
None.
--*/
FUNCTION ArSetDataFaultingAddress
mcr p15, 0, %r0, %cr6, %cr0, 0
bx %lr
END_FUNCTION ArSetDataFaultingAddress
//
// PVOID
// ArGetInstructionFaultingAddress (
// VOID
// )
//
/*++
Routine Description:
This routine determines which address caused a prefetch abort.
Arguments:
None.
Return Value:
Returns the faulting address.
--*/
FUNCTION ArGetInstructionFaultingAddress
mrc p15, 0, %r0, %cr6, %cr0, 2 @ Get the IFAR.
bx %lr @
END_FUNCTION ArGetInstructionFaultingAddress
//
// VOID
// ArSetInstructionFaultingAddress (
// PVOID Value
// )
//
/*++
Routine Description:
This routine sets the instruction faulting address register (IFAR).
Arguments:
Value - Supplies the value to set.
Return Value:
None.
--*/
FUNCTION ArSetInstructionFaultingAddress
mcr p15, 0, %r0, %cr6, %cr0, 2
bx %lr
END_FUNCTION ArSetInstructionFaultingAddress
//
// ULONG
// ArGetDataFaultStatus (
// VOID
// )
//
/*++
Routine Description:
This routine determines the reason for the fault by reading the DFSR
register.
Arguments:
None.
Return Value:
Returns the contents of the Data Fault Status Register.
--*/
FUNCTION ArGetDataFaultStatus
mrc p15, 0, %r0, %cr5, %cr0, 0 @ Get the DFSR.
bx %lr @
END_FUNCTION ArGetDataFaultStatus
//
// VOID
// ArSetDataFaultStatus (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the data fault status register (DFSR).
Arguments:
Value - Supplies the value to set.
Return Value:
None.
--*/
FUNCTION ArSetDataFaultStatus
mcr p15, 0, %r0, %cr5, %cr0, 0
bx %lr
END_FUNCTION ArSetDataFaultStatus
//
// ULONG
// ArGetInstructionFaultStatus (
// VOID
// )
//
/*++
Routine Description:
This routine determines the reason for the prefetch abort by reading the
IFAR register.
Arguments:
None.
Return Value:
Returns the contents of the Instruction Fault Status Register.
--*/
FUNCTION ArGetInstructionFaultStatus
mrc p15, 0, %r0, %cr5, %cr0, 1 @ Get the IFSR.
bx %lr @
END_FUNCTION ArGetInstructionFaultStatus
//
// VOID
// ArSetInstructionFaultStatus (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the instruction fault status register (IFSR).
Arguments:
Value - Supplies the value to set.
Return Value:
None.
--*/
FUNCTION ArSetInstructionFaultStatus
mcr p15, 0, %r0, %cr5, %cr0, 1
bx %lr
END_FUNCTION ArSetInstructionFaultStatus
//
// PVOID
// ArGetProcessorBlockRegister (
// VOID
// )
//
/*++
Routine Description:
This routine gets the register used to store a pointer to the processor
block (TPIDRPRW in the ARMARM; Thread and Process ID Registers in the
ARM1176 TRM).
Arguments:
None.
Return Value:
Returns a pointer to the processor block.
--*/
FUNCTION ArGetProcessorBlockRegister
mrc p15, 0, %r0, c13, c0, 4 @ Get TPIDRPRW.
bx %lr @ Return.
END_FUNCTION ArGetProcessorBlockRegister
//
// VOID
// ArSetProcessorBlockRegister (
// PVOID ProcessorBlockRegisterValue
// )
//
/*++
Routine Description:
This routine sets the register used to store a pointer to the processor
block (TPIDRPRW in the ARMARM; Thread and Process ID Registers in the
ARM1176 TRM).
Arguments:
ProcessorBlockRegisterValue - Supplies the value to assign to the register
used to store the processor block.
Return Value:
None.
--*/
FUNCTION ArSetProcessorBlockRegister
mcr p15, 0, %r0, c13, c0, 4 @ Set TPIDRPRW.
bx %lr @ Return.
END_FUNCTION ArSetProcessorBlockRegister
//
// ULONG
// ArGetTranslationTableBaseRegister0 (
// VOID
// )
//
/*++
Routine Description:
This routine gets the translation table base register 0 (TTBR0), used as
the base for all virtual to physical memory lookups.
Arguments:
None.
Return Value:
Returns the contents of TTBR0.
--*/
FUNCTION ArGetTranslationTableBaseRegister0
mrc p15, 0, %r0, c2, c0, 0 @ Get TTBR0.
bx %lr @ Return.
END_FUNCTION ArGetTranslationTableBaseRegister0
//
// VOID
// ArSetTranslationTableBaseRegister0 (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the translation table base register 0 (TTBR0).
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetTranslationTableBaseRegister0
mcr p15, 0, %r0, c2, c0, 0
bx %lr
END_FUNCTION ArSetTranslationTableBaseRegister0
//
// ULONG
// ArGetTranslationTableBaseRegister1 (
// VOID
// )
//
/*++
Routine Description:
This routine gets the translation table base register 1 (TTBR1).
Arguments:
None.
Return Value:
Returns the contents of TTBR1.
--*/
FUNCTION ArGetTranslationTableBaseRegister1
mrc p15, 0, %r0, c2, c0, 1
bx %lr
END_FUNCTION ArGetTranslationTableBaseRegister1
//
// VOID
// ArSetTranslationTableBaseRegister1 (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the translation table base register 1 (TTBR1).
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetTranslationTableBaseRegister1
mcr p15, 0, %r0, c2, c0, 1
bx %lr
END_FUNCTION ArSetTranslationTableBaseRegister1
//
// ULONG
// ArGetPrimaryRegionRemapRegister (
// VOID
// )
//
/*++
Routine Description:
This routine gets the Primary Region Remap Register (PRRR).
Arguments:
None.
Return Value:
Returns the contents of the register.
--*/
FUNCTION ArGetPrimaryRegionRemapRegister
mrc p15, 0, %r0, c10, c2, 0
bx %lr
END_FUNCTION ArGetPrimaryRegionRemapRegister
//
// VOID
// ArSetPrimaryRegionRemapRegister (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the PRRR.
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetPrimaryRegionRemapRegister
mcr p15, 0, %r0, c10, c2, 0
bx %lr
END_FUNCTION ArSetPrimaryRegionRemapRegister
//
// ULONG
// ArGetNormalMemoryRemapRegister (
// VOID
// )
//
/*++
Routine Description:
This routine gets the Normal Memory Remap Register (NMRR).
Arguments:
None.
Return Value:
Returns the contents of the register.
--*/
FUNCTION ArGetNormalMemoryRemapRegister
mrc p15, 0, %r0, c10, c2, 1
bx %lr
END_FUNCTION ArGetNormalMemoryRemapRegister
//
// VOID
// ArSetNormalMemoryRemapRegister (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the NMRR.
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetNormalMemoryRemapRegister
mcr p15, 0, %r0, c10, c2, 1
bx %lr
END_FUNCTION ArSetNormalMemoryRemapRegister
//
// ULONG
// ArGetPhysicalAddressRegister (
// VOID
// )
//
/*++
Routine Description:
This routine gets the Physical Address Register (PAR).
Arguments:
None.
Return Value:
Returns the contents of the register.
--*/
FUNCTION ArGetPhysicalAddressRegister
mrc p15, 0, %r0, c7, c4, 0
bx %lr
END_FUNCTION ArGetPhysicalAddressRegister
//
// VOID
// ArSetPhysicalAddressRegister (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the Physical Address Register (PAR).
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetPhysicalAddressRegister
mcr p15, 0, %r0, c7, c4, 0
bx %lr
END_FUNCTION ArSetPhysicalAddressRegister
//
// VOID
// ArSetPrivilegedReadTranslateRegister (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the Privileged Read address translation command register.
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetPrivilegedReadTranslateRegister
mcr p15, 0, %r0, c7, c8, 0
bx %lr
END_FUNCTION ArSetPrivilegedReadTranslateRegister
//
// VOID
// ArSetPrivilegedWriteTranslateRegister (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the Privileged Write address translation command register.
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetPrivilegedWriteTranslateRegister
mcr p15, 0, %r0, c7, c8, 1
bx %lr
END_FUNCTION ArSetPrivilegedWriteTranslateRegister
//
// VOID
// ArSetUnprivilegedReadTranslateRegister (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the Unrivileged Read address translation command register.
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetUnprivilegedReadTranslateRegister
mcr p15, 0, %r0, c7, c8, 2
bx %lr
END_FUNCTION ArSetUnprivilegedReadTranslateRegister
//
// VOID
// ArSetUnprivilegedWriteTranslateRegister (
// ULONG Value
// )
//
/*++
Routine Description:
This routine sets the Unprivileged Write address translation command
register.
Arguments:
Value - Supplies the value to write.
Return Value:
None.
--*/
FUNCTION ArSetUnprivilegedWriteTranslateRegister
mcr p15, 0, %r0, c7, c8, 3
bx %lr
END_FUNCTION ArSetUnprivilegedWriteTranslateRegister
//
// ULONG
// ArGetCacheTypeRegister (
// VOID
// )
//
/*++
Routine Description:
This routine retrives the Cache Type Register (CTR) from the system
coprocessor.
Arguments:
None.
Return Value:
Returns the value of the CTR.
--*/
FUNCTION ArGetCacheTypeRegister
mrc p15, 0, %r0, %cr0, %cr0, 1 @ Read the CTR.
bx %lr @
END_FUNCTION ArGetCacheTypeRegister
//
// --------------------------------------------------------- Internal Functions
//
//
// This code is entered as the result of any interrupt or exception. Its job is
// to transition back to the SVC stack and then call the real interrupt
// dispatch routine.
//
FUNCTION EfipCommonInterruptEntry
//
// Save state and create a trap frame.
//
ARM_ENTER_INTERRUPT
//
// Call the main dispatch routine routine with a pointer to the trap frame
// as the only parameter.
//
mov %r0, %sp
blx EfipDispatchException
//
// Restore state and return.
//
ARM_EXIT_INTERRUPT
END_FUNCTION EfipCommonInterruptEntry
|
{
"language": "Assembly"
}
|
// AUTO-GENERATED BY gen_bench.py -- do not edit manually
#include "linker_reloc_bench_asm.h"
.data
.p2align 4
.text
.globl b_AngvirOevqtrTrgFvtanyUnaqyre
.type b_AngvirOevqtrTrgFvtanyUnaqyre,%function
b_AngvirOevqtrTrgFvtanyUnaqyre:
nop
.text
.globl b_AngvirOevqtrTrgIrefvba
.type b_AngvirOevqtrTrgIrefvba,%function
b_AngvirOevqtrTrgIrefvba:
nop
.text
.globl b_AngvirOevqtrVfFhccbegrq
.type b_AngvirOevqtrVfFhccbegrq,%function
b_AngvirOevqtrVfFhccbegrq:
nop
.text
.globl b_AngvirOevqtrYvaxAnzrfcnprf
.type b_AngvirOevqtrYvaxAnzrfcnprf,%function
b_AngvirOevqtrYvaxAnzrfcnprf:
nop
.text
.globl b_AngvirOevqtrYbnqYvoenel
.type b_AngvirOevqtrYbnqYvoenel,%function
b_AngvirOevqtrYbnqYvoenel:
nop
.text
.globl b_AngvirOevqtrYbnqYvoenelRkg
.type b_AngvirOevqtrYbnqYvoenelRkg,%function
b_AngvirOevqtrYbnqYvoenelRkg:
nop
.text
.globl b_ArrqfAngvirOevqtr
.type b_ArrqfAngvirOevqtr,%function
b_ArrqfAngvirOevqtr:
nop
.text
.globl b_CerVavgvnyvmrAngvirOevqtr
.type b_CerVavgvnyvmrAngvirOevqtr,%function
b_CerVavgvnyvmrAngvirOevqtr:
nop
.text
.globl b__MA7naqebvq30AngvirOevqtrTrgIraqbeAnzrfcnprRi
.type b__MA7naqebvq30AngvirOevqtrTrgIraqbeAnzrfcnprRi,%function
b__MA7naqebvq30AngvirOevqtrTrgIraqbeAnzrfcnprRi:
nop
.text
.globl b_VavgvnyvmrAngvirOevqtr
.type b_VavgvnyvmrAngvirOevqtr,%function
b_VavgvnyvmrAngvirOevqtr:
nop
.text
.globl b_AngvirOevqtrVavgNabalzbhfAnzrfcnpr
.type b_AngvirOevqtrVavgNabalzbhfAnzrfcnpr,%function
b_AngvirOevqtrVavgNabalzbhfAnzrfcnpr:
nop
.text
.globl b_AngvirOevqtrVfCnguFhccbegrq
.type b_AngvirOevqtrVfCnguFhccbegrq,%function
b_AngvirOevqtrVfCnguFhccbegrq:
nop
.text
.globl b_AngvirOevqtrNinvynoyr
.type b_AngvirOevqtrNinvynoyr,%function
b_AngvirOevqtrNinvynoyr:
nop
.text
.globl b_AngvirOevqtrReebe
.type b_AngvirOevqtrReebe,%function
b_AngvirOevqtrReebe:
nop
.text
.globl b_AngvirOevqtrTrgReebe
.type b_AngvirOevqtrTrgReebe,%function
b_AngvirOevqtrTrgReebe:
nop
.text
.globl b_AngvirOevqtrHaybnqYvoenel
.type b_AngvirOevqtrHaybnqYvoenel,%function
b_AngvirOevqtrHaybnqYvoenel:
nop
.text
.globl b_YbnqAngvirOevqtr
.type b_YbnqAngvirOevqtr,%function
b_YbnqAngvirOevqtr:
nop
.text
.globl b_AngvirOevqtrPerngrAnzrfcnpr
.type b_AngvirOevqtrPerngrAnzrfcnpr,%function
b_AngvirOevqtrPerngrAnzrfcnpr:
nop
.text
.globl b_AngvirOevqtrVavgvnyvmrq
.type b_AngvirOevqtrVavgvnyvmrq,%function
b_AngvirOevqtrVavgvnyvmrq:
nop
.text
.globl b_AngvirOevqtrAnzrNpprcgnoyr
.type b_AngvirOevqtrAnzrNpprcgnoyr,%function
b_AngvirOevqtrAnzrNpprcgnoyr:
nop
.text
.globl b_AngvirOevqtrTrgGenzcbyvar
.type b_AngvirOevqtrTrgGenzcbyvar,%function
b_AngvirOevqtrTrgGenzcbyvar:
nop
.text
.globl b_HaybnqAngvirOevqtr
.type b_HaybnqAngvirOevqtr,%function
b_HaybnqAngvirOevqtr:
nop
.text
CALL(__cxa_finalize)
CALL(b___pkn_thneq_npdhver)
CALL(dlsym)
CALL(b___pkn_thneq_eryrnfr)
CALL(dlopen)
.text
.data
local_label:
.space (__SIZEOF_POINTER__ * 1536)
DATA_WORD(local_label)
DATA_WORD(local_label)
DATA_WORD(local_label)
|
{
"language": "Assembly"
}
|
g17 ; do canned cycles in the XY plane
g99 ; "retract to R" mode
g90 ; absolute coordinates mode
g20 ; imperial
f10
; starting position
g0 x0 y0 z2
;
; There are six possible orderings of Z, OLD_Z, and R, but the three that
; have R < Z are rejected by LinuxCNC.
;
(number 1: Z[-1] < R[1] < OLD_Z[2])
g81 x1 y1 z-1 r1
(number 2: Z[0.5] < OLD_Z[1] < R[3])
g81 x1 y2 z0.5 r3
(number 3: OLD_Z[3] < Z[4] < R[5])
g81 x1 y3 z4 r5
;
; test with incremental motion and repeat cycles
;
(number 4: Z[-1] < R[1] < OLD_Z[2])
g90 g0 x10 y0 z2
g91 g81 x1 y1 z-2 r-1 l2
(number 5: Z[0.5] < OLD_Z[2] < R[3])
g90 g0 x20 y0 z2
g91 g81 x1 y1 z-2.5 r1 l2
(number 6: OLD_Z[2] < Z[4] < R[5])
g90 g0 x30 y0 z2
g91 g81 x1 y1 z-1 r3 l2
(done)
m2
|
{
"language": "Assembly"
}
|
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for 386, FreeBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
JMP syscall·RawSyscall6(SB)
|
{
"language": "Assembly"
}
|
# JOB-SHOP-SCHEDULING-PROBLEM
## AIMA3e
_Jobs({AddEngine1 ≺ AddWheels1 ≺ Inspect1 },_
 _{AddEngine2 ≺ AddWheels2 ≺ Inspect2 })_
_Resources(EngineHoists(1), WheelStations(1), Inspectors(2), LugNuts(500))_
_Action(AddEngine1_, DURATION: 30,
 USE: _EngineHoists(1))_
_Action(AddEngine2_, DURATION: 60,
 USE: _EngineHoists(1))_
_Action(AddWheels1_, DURATION: 30,
 CONSUME: _LugNuts(20),_ USE: _WheelStations(1))_
_Action(AddWheels2_, DURATION: 15,
 CONSUME: _LugNuts(20)_, USE: _WheelStations(1))_
_Action(Inspect<sub>i</sub>_, DURATION: 10,
 USE: _Inspectors(1))_
---
__Figure ??__ A job-shop scheduling problem for assembling two cars, with resource constraints. The
notation _A_ ≺ _B_ means that action _A_ must precede action _B_.
|
{
"language": "Assembly"
}
|
/* Test glob with GLOB_ALTDIRFUNC.
Copyright (C) 2017-2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
#define GLOB_FUNC glob
#define GLOB_TYPE glob_t
#define GLOBFREE_FUNC globfree
#define DIRENT_STRUCT dirent
#define STAT_STRUCT stat
#include "tst-gnuglob-skeleton.c"
|
{
"language": "Assembly"
}
|
*LIST_MLSD // VectorのftpサーバーはRFC違反形式
m type=cdir;modify=20090804135600;UNIX.mode=0755 /
m type=file;size=8436;modify=20120105211719;UNIX.mode=0644 ****.TXT
m type=dir;modify=20060802141522;UNIX.mode=0775 IMG
m type=dir;modify=20090111055109;UNIX.mode=0755 Java
m type=dir;modify=20060801143706;UNIX.mode=0755 JavaScript
m type=file;size=18523;modify=20110915135932;UNIX.mode=0644 ***.htm
m type=file;size=1364;modify=20110915135931;UNIX.mode=0644 ***.htm
m type=dir;modify=20060801143819;UNIX.mode=0755 css
m type=file;size=13280;modify=20120112114016;UNIX.mode=0644 ***.html
m type=file;size=6814;modify=20120104005304;UNIX.mode=0664 ***.htm
m type=dir;modify=20011021032956;UNIX.mode=0755 sasurai
m type=dir;modify=20111116204531;UNIX.mode=0775 software
m type=file;size=7809;modify=20120112204230;UNIX.mode=0664 ***.htm
m type=file;size=2155;modify=20110915135933;UNIX.mode=0664 ***.htm
*LIST_UNIX_10
0 1 2 3 4 5 6 7 8
-------------------------------------------------------
u drwxr-xr-x 15 owner group 1024 Nov 6 14:21 Linux/
u -rwxrwx--- 5 owner group 12 Nov 6 1996 test.txt
u drwxr-xr-x 15 owner group 1024 11月 6日 14:21 Linux/
u drwxr-xr-x 15 owner group 1024 11月 6日 14時21分 Linux/
u -rwxrwx--- 5 owner group 12 11月 6日 1996年 test.txt
u drwxrwxr-x 6 root sys 512 1月 26 03:10 adm
*LIST_UNIX_11
0 1 2 3 4 5 6 7
-------------------------------------------------------
u drwxr-xr-x 15 owner group 1024 11月12日 14時21分 Linux/
u -rwxrwx--- 5 owner group 12 11月12日 1996年 test.txt
*LIST_UNIX_12
0 1 2 3 4 5 6 7
-------------------------------------------------------
u drwxr-xr-x123 owner group 1024 Nov 6 14:21 Linux/
u -rwxrwx---132 owner group 12 Nov 6 1996 test.txt
u drwxr-xr-x123 owner group 1024 11月 6日 14:21 Linux/
u drwxr-xr-x123 owner group 1024 11月 6日 14時21分 Linux/
u -rwxrwx---132 owner group 12 11月 6日 1996年 test.txt
*LIST_UNIX_13
0 1 2 3 4 5 6
-------------------------------------------------------
u drwxr-xr-x123 owner group 1024 11月12日 14時21分 Linux/
u -rwxrwx---132 owner group 12 11月12日 1996年 test.txt
*LIST_UNIX_14
0 1 2 3 4 5 6 7 8 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x 15 owner group 512 2001 6月 18 audit
*LIST_UNIX_15
0 1 2 3 4 5 6 7 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x15 owner group 512 2001 6月 18 audit
*LIST_UNIX_20
0 1 2 3 4 5 6 7
-------------------------------------------------------
u drwxr-xr-x 15 owner 1024 Nov 6 14:21 Linux/
u -rwxrwx--- 5 owner 12 Nov 6 1996 test.txt
u drwxr-xr-x 15 owner 1024 11月 6日 14:21 Linux/
u drwxr-xr-x 15 owner 1024 11月 6日 14時21分 Linux/
u -rwxrwx--- 5 owner 12 11月 6日 1996年 test.txt
*LIST_UNIX_21
0 1 2 3 4 5 6
-------------------------------------------------------
u drwxr-xr-x 15 owner 1024 11月12日 14時21分 Linux/
u -rwxrwx--- 5 owner 12 11月12日 1996年 test.txt
*LIST_UNIX_22
0 1 2 3 4 5 6
-------------------------------------------------------
u drwxr-xr-x123 owner 1024 Nov 6 14:21 Linux/
u -rwxrwx---132 owner 12 Nov 6 1996 test.txt
u drwxr-xr-x123 owner 1024 11月 6日 14:21 Linux/
u drwxr-xr-x123 owner 1024 11月 6日 14時21分 Linux/
u -rwxrwx---132 owner 12 11月 6日 1996年 test.txt
*LIST_UNIX_23
0 1 2 3 4 5
-------------------------------------------------------
u drwxr-xr-x123 owner 1024 11月12日 14時21分 Linux/
u -rwxrwx---132 owner 12 11月12日 1996年 test.txt
*LIST_UNIX_24
0 1 2 3 4 5 6 7 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x 15 owner 512 2001 6月 18 audit
*LIST_UNIX_25
0 1 2 3 4 5 6 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x15 owner 512 2001 6月 18 audit
*LIST_UNIX_50
0 1 2 3 4 5 6
-------------------------------------------------------
u drwxr-xr-x owner 1024 Nov 6 14:21 Linux/
u -rwxrwx--- owner 12 Nov 6 1996 test.txt
u drwxr-xr-x owner 1024 11月 6日 14:21 Linux/
u drwxr-xr-x owner 1024 11月 6日 14時21分 Linux/
u -rwxrwx--- owner 12 11月 6日 1996年 test.txt
*LIST_UNIX_51
0 1 2 3 4 5
-------------------------------------------------------
u drwxr-xr-x owner 1024 11月12日 14時21分 Linux/
u -rwxrwx--- owner 12 11月12日 1996年 test.txt
*LIST_UNIX_54
0 1 2 3 4 5 6 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x owner 512 2001 6月 18 audit
*LIST_UNIX_60
0 1 2 3 4 5 6 7 8 9 10
-------------------------------------------------------
u drwxr-xr-x 123 owner m group g 1024 Nov 6 14:21 Linux/
u -rwxrwx--- 132 owner m group g 12 Nov 6 1996 test.txt
*LIST_UNIX_61
0 1 2 3 4 5 6 7 8 9
-------------------------------------------------------
u drwxr-xr-x 123 owner m group g 1024 11月12日 14:21 Linux/
u -rwxrwx--- 132 owner m group g 12 11月12日 1996 test.txt
*LIST_UNIX_62
0 1 2 3 4 5 6 7 8 9
-------------------------------------------------------
u drwxr-xr-x123 owner m group g 1024 Nov 6 14:21 Linux/
u -rwxrwx---132 owner m group g 12 Nov 6 1996 test.txt
*LIST_UNIX_63
0 1 2 3 4 5 6 7 8
-------------------------------------------------------
u drwxr-xr-x123 owner m group g 1024 11月12日 14:21 Linux/
u -rwxrwx---132 owner m group g 12 11月12日 1996 test.txt
*LIST_UNIX_64
0 1 2 3 4 5 6 7 8 9 10 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x 15 owner m group g 512 2001 6月 18 audit
*LIST_UNIX_65
0 1 2 3 4 5 6 7 8 9 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x15 owner m group g 512 2001 6月 18 audit
LIST_UNIX_70
0 1 2 3 4 5 6 7 8 9
-------------------------------------------------------
u drwxr-xr-x 123 owner group g 1024 Nov 6 14:21 Linux/
u -rwxrwx--- 132 owner group g 12 Nov 6 1996 test.txt
*LIST_UNIX_71
0 1 2 3 4 5 6 7 8
-------------------------------------------------------
u drwxr-xr-x 123 owner group g 1024 11月12日 14:21 Linux/
u -rwxrwx--- 132 owner group g 12 11月12日 1996 test.txt
*LIST_UNIX_72
0 1 2 3 4 5 6 7 8
-------------------------------------------------------
u drwxr-xr-x123 owner group g 1024 Nov 6 14:21 Linux/
u -rwxrwx---132 owner group g 12 Nov 6 1996 test.txt
*LIST_UNIX_73
0 1 2 3 4 5 6 7
-------------------------------------------------------
u drwxr-xr-x123 owner group g 1024 11月12日 14:21 Linux/
u -rwxrwx---132 owner group g 12 11月12日 1996 test.txt
*LIST_UNIX_74
0 1 2 3 4 5 6 7 8 9 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x 15 owner group g 512 2001 6月 18 audit
*LIST_UNIX_75
0 1 2 3 4 5 6 7 8 (月はGBコードで0xD4C2)
-------------------------------------------------------
u drwxr-xr-x15 owner group g 512 2001 6月 18 audit
*unix系で以下のような日付
0 1 2 3 4 5 6
-------------------------------------------------------
u drwxr-xr-x123 owner 1024 11/ 6 14:21 Linux/
u -rwxrwx---132 owner 12 11/13 1996 test.txt
// linux-ftpd
*LIST_UNIX_16
0 1 2 3 4 5 6 7
-------------------------------------------------------
@ 合計 12345
u drwxr-x--- 2 root root 4096 2011-12-06 23:39 .
u drwxr-x--- 3 root root 4096 2011-12-06 23:39 ..
u -rw-r----- 1 root root 251 2011-12-06 23:39 .hoge
*LIST_MELCOM
0 1 2 3 4 5 6 7 8
---------------------------------------------------------------
M - RW-RW-RW- 1 TERA 50 DEC 1 1997 AAAJ B(B)
M - RW-RW-RW- 1 TERA 1 AUG 7 1998 12345678901234B(B)
M d RWXRWXRWX 2 TERA 64 NOV 13 1997 Q2000 -
*LIST_AGILENT
0 1 2 3 4 5
---------------------------------------------------------------
a drwxrwxrwx 1 1 1 1024 system
a -rw-rw-rw- 1 1 1 1792 abc.aaa
// uClinux
*LIST_UNIX_17
0 1 2 3 4 5
-------------------------------------------------------
a -rw-r--r-- 1 0 0 100 services
a lrwxrwxrwx 1 0 0 20 resolv.conf -> /var/run/resolv.conf
a drwxr-sr-x 1 0 0 0 rc.d
a -rw-r--r-- 1 0 0 290 rc
a -rw-r--r-- 1 0 0 34 passwd
a lrwxrwxrwx 1 0 0 18 inittab -> ../var/tmp/inittab
*LIST_DOS_1
0 1 2 3
-------------------------------------------------------
d 97-10-14 03:34p <DIR> Linux
d 97-10-14 03:34p 12 test.txt
d 100-10-14 03:34p 12 test.txt
*LIST_DOS_4
0 1 2 3
-------------------------------------------------------
d 1998/07/30 15:39:02 <DIR> Linux
d 1998/07/30 15:42:19 11623 test.txt
*LIST_DOS_2
0 1 2 3
-------------------------------------------------------
d 10-14-97 03:34p <DIR> Linux
d 10-14-97 03:34p 12 test.txt
d 10-14-100 03:34p 12 test.txt
// Windows Server 2008 R2
*LIST_DOS_5
0 1 2 3
-------------------------------------------------------
d 02-05-2013 09:45AM <DIR> TEST
d 01-28-2013 03:54PM 2847 DATA.TXT
*LIST_CHAMELEON
0 1 2 3 4 5 6
-------------------------------------------------------
c Linux <DIR> Nov 6 1997 14:21 drw-
c test.txt 12 Nov 6 1886 14:21 -rwa
*LIST_DOS_3
0 1 2 3 4
-------------------------------------------------------
c Linux <DIR> 10-14-97 03:34
c test.txt 12 10-14-97 14:34 A
c test.txt 12 10-14-100 14:34 A
*LIST_OS2
0 1 2 3 4
-------------------------------------------------------
2 345 A 12-02-98 10:59 VirtualDevice.java
2 0 DIR 12-09-98 09:43 ディレクトリ
2 0 DIR 12-09-100 09:43 ディレクトリ
*LIST_ALLIED
0 1 2 3 4 5 6
---------------------------------------------------------------
b 41622 IO.SYS Tue Dec 20 06:20:00 1994
b <dir> DOS Wed Nov 24 09:35:48 1999
*LIST_SHIBASOKU
0 1 2 3 4
---------------------------------------------------------------
s 512 Jan-30-2002 14:52:04 DIRNAME <DIR>
s 61191 Aug-30-2002 17:30:38 FILENAME.C
*LIST_AS400
0 1 2 3 4 5
-------------------------------------------------------
A QSYS 18944 96/09/20 00:35:10 *DIR QOpenSys/
A QDOC 26624 70/01/01 00:00:00 *FLR QDLS/
A QSYS 0 98/09/27 10:00:04 *LIB QSYS.LIB/
A QSECOFR 0 98/05/15 16:01:15 *STMF WWWTEST.BAK
*LIST_M1800
0 1 2 3 4 5 6 (ファイル名の後ろにスペースあり）
-------------------------------------------------------
n drwx F 400 400 PO 93.10.27 COMMON.PDL.EXCEL/
n -rw- F 10000 10000 DA 97.03.04 DTSLOG1.FNA
n -rw- F 10000 ****** DA 97.03.04 DTSBRB.FNA
n drwx U ****** 6144 PO 96.12.15 IS01.TISPLOAD/
n -rw- **** ****** ****** VSAM **.**.** HICS.CMDSEQ
*LIST_GP6000
0 1 2 3 4 5 6
-------------------------------------------------------
g drwxrwxrwx 98.10.21 14:38:46 SYSG03 XSYSOPR 2048 atlib
g -rwxrwxrwx 97.10.30 11:06:04 XSYSMNGR XSYSOPR 2048 blib
*LIST_OS7_1
0 1 2 3
---------------------------------------------------------------
7 drwxrwxrwx 99/05/13 11:38:34 APL
*LIST_OS7_2
0 1 2 3 4 5
---------------------------------------------------------------
7 -rwxrwxrwx SEQ 17408 96/12/06 10:11:27 INIT_CONFIG
0 1 2 3 4 5 (ファイル名の後ろにスペースあり）
-------------------------------------------------------
7 -rwxrwxrwx SEQ 36203776 01/07/07 12:38:28 ADRS001
7 -rwxrwxrwx SEQ 70172160 01/07/07 13:59:58 ADRS002
*LIST_OS9
0 1 2 3 4 5 6
---------------------------------------------------------------
9 0.0 01/02/13 0945 d-----wr 3C0 148724 W_017
9 0.0 01/02/13 0945 ------wr C20 48828 W_017.CLG
*LIST_IBM
0 1 2 3 4 5 6 7 8 9
---------------------------------------------------------------
i JXSIB1 3390 2000/12/27 1 810 FB 240 24000 PO DIRNAME
i JXSW01 3390 2000/12/27 1 5 VBA 240 3120 PS FILENAME
*LIST_STRATUS
0 1 2 3 4 5
---------------------------------------------------------------
S Files: 15 Blocks: 29
S w 1 seq 99-06-15 13:11:39 member_srv.error
S Dirs: 74
S m 3 98-12-25 16:14:58 amano
*LIST_VMS
0 1 2 3 4
---------------------------------------------------------------
v CIM_ALL.MEM;5 2/4 21-APR-1998 11:01:17 [CIM,MIZOTE]
@ (RWED,RWED,RE,)
v MAIL.DIR;1 104/248 18-SEP-2001 16:19:39 [CIM,MIZOTE]
@ (RWE,RWE,,)
※VMSの場合一覧が複数行に別れる場合がある
*LIST_IRMX
0 1 2 3 4 5 6 7 8 9 10 11
---------------------------------------------------------------
I world DR DLAC 1 416 1,024 1 WORLD 05 FEB 98
I world DR 1 416 1,024 1 WORLD 05 FEB 98
I name.f38 DRAU 5 4,692 1,024 1 # 0 24 MAR 99
I name.f38 5 4,692 1,024 1 # 0 24 MAR 99
*LIST_TANDEM
0 1 2 3 4 5 6
---------------------------------------------------------------
@ File Code EOF Last Modification Owner RWEP
t EMSACSTM 101 146 18-Sep-00 09:03:37 170,175 "nunu"
t TACLCSTM O 101 101 4-Mar-01 23:50:06 255,255 "oooo"
*LIST_ACOS
0
-------------------------------------------------------
@ test.txt
ディレクトリなし、
|
{
"language": "Assembly"
}
|
// RUN: %clang -arch x86_64 %s -fsyntax-only -Xclang -print-stats
#ifdef __APPLE__
#include <Cocoa/Cocoa.h>
#endif
|
{
"language": "Assembly"
}
|
# NOTE: This test is only intended to be valid as long as --only-keep-debug is
# implemented as a NOP. This test should fail when that changes and you
# will need to update this test.
# RUN: yaml2obj %s > %t
# RUN: llvm-objcopy %t %t2
# RUN: llvm-objcopy --only-keep-debug %t %t3
# RUN: cmp %t2 %t3
# RUN: llvm-strip --only-keep-debug --no-strip-all %t -o %t4
# RUN: cmp %t2 %t4
!ELF
FileHeader:
Class: ELFCLASS64
Data: ELFDATA2LSB
Type: ET_EXEC
Machine: EM_X86_64
Sections:
- Name: .text
Type: SHT_PROGBITS
Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
Content: "DEADBEEF"
|
{
"language": "Assembly"
}
|
;
; Ullrich von Bassewitz, 13.09.2001
;
; void pokebsys (unsigned Addr, unsigned char Val);
; void pokewsys (unsigned Addr, unsigned Val);
.export _pokebsys, _pokewsys
.import popsreg
.importzp sreg, tmp1
.include "cbm510.inc"
; ------------------------------------------------------------------------
;
.proc _pokebsys
jsr popsreg ; Get the address
ldx IndReg
ldy #$0F
sty IndReg ; Switch to the system bank
ldy #$00
sta (sreg),y
stx IndReg
rts
.endproc
; ------------------------------------------------------------------------
;
.proc _pokewsys
stx tmp1 ; Save high byte
jsr popsreg ; Get the address
ldx IndReg
ldy #$0F
sty IndReg ; Switch to the system bank
ldy #$00
sta (sreg),y
iny
lda tmp1
sta (sreg),y
stx IndReg
rts
.endproc
|
{
"language": "Assembly"
}
|
$OpenBSD$
Index: ksysguardd/OpenBSD/memory.c
--- ksysguardd/OpenBSD/memory.c.orig
+++ ksysguardd/OpenBSD/memory.c
@@ -22,8 +22,8 @@
#include <sys/param.h>
#include <sys/sysctl.h>
-#include <sys/dkstat.h>
#include <sys/swap.h>
+#include <sys/vmmeter.h>
#include <limits.h>
#include <stdio.h>
@@ -87,6 +87,7 @@ exitMemory(void)
int
updateMemory(void)
{
+ /*
static int vmtotal_mib[] = {CTL_VM, VM_METER};
size_t size;
struct vmtotal vmtotal;
@@ -108,6 +109,7 @@ updateMemory(void)
swapmode(&SUsed, &STotal);
SFree = STotal - SUsed;
+ */
return 0;
}
|
{
"language": "Assembly"
}
|
; RUN: llvm-rc /FO %t -- %p/Inputs/tag-stringtable-basic.rc
; RUN: llvm-readobj %t | FileCheck %s
; CHECK: Resource type (int): 6
; CHECK-NEXT: Resource name (int): 1
; CHECK-NEXT: Data version: 0
; CHECK-NEXT: Memory flags: 0x1030
; CHECK-NEXT: Language ID: 1033
; CHECK-NEXT: Version (major): 0
; CHECK-NEXT: Version (minor): 32
; CHECK-NEXT: Characteristics: 50
; CHECK-NEXT: Data size: 40
; CHECK-NEXT: Data: (
; CHECK-NEXT: 0000: 01006100 01006200 01006300 01006400 |..a...b...c...d.|
; CHECK-NEXT: 0010: 00000000 00000000 00000000 00000000 |................|
; CHECK-NEXT: 0020: 00000000 00000000 |........|
; CHECK-NEXT: )
; CHECK-DAG: Resource type (int): 6
; CHECK-NEXT: Resource name (int): 2
; CHECK-NEXT: Data version: 0
; CHECK-NEXT: Memory flags: 0x1030
; CHECK-NEXT: Language ID: 1033
; CHECK-NEXT: Version (major): 0
; CHECK-NEXT: Version (minor): 0
; CHECK-NEXT: Characteristics: 0
; CHECK-NEXT: Data size: 40
; CHECK-NEXT: Data: (
; CHECK-NEXT: 0000: 02006200 62000200 63006300 00000000 |..b.b...c.c.....|
; CHECK-NEXT: 0010: 00000000 00000000 00000000 00000000 |................|
; CHECK-NEXT: 0020: 00000000 00000000 |........|
; CHECK-NEXT: )
; CHECK-DAG: Resource type (int): 6
; CHECK-NEXT: Resource name (int): 2
; CHECK-NEXT: Data version: 0
; CHECK-NEXT: Memory flags: 0x1030
; CHECK-NEXT: Language ID: 7172
; CHECK-NEXT: Version (major): 0
; CHECK-NEXT: Version (minor): 100
; CHECK-NEXT: Characteristics: 0
; CHECK-NEXT: Data size: 80
; CHECK-NEXT: Data: (
; CHECK-NEXT: 0000: 05006800 65006C00 6C006F00 05007700 |..h.e.l.l.o...w.|
; CHECK-NEXT: 0010: 6F007200 6C006400 00000000 00000000 |o.r.l.d.........|
; CHECK-NEXT: 0020: 00000E00 73006F00 6D006500 74006800 |....s.o.m.e.t.h.|
; CHECK-NEXT: 0030: 69006E00 67002000 65006C00 73006500 |i.n.g. .e.l.s.e.|
; CHECK-NEXT: 0040: 00000000 00000000 00000000 00000000 |................|
; CHECK-NEXT: )
; CHECK-DAG: Resource type (int): 6
; CHECK-NEXT: Resource name (int): 3
; CHECK-NEXT: Data version: 0
; CHECK-NEXT: Memory flags: 0x1030
; CHECK-NEXT: Language ID: 1033
; CHECK-NEXT: Version (major): 0
; CHECK-NEXT: Version (minor): 50
; CHECK-NEXT: Characteristics: 50
; CHECK-NEXT: Data size: 38
; CHECK-NEXT: Data: (
; CHECK-NEXT: 0000: 03006300 63006300 00000000 00000000 |..c.c.c.........|
; CHECK-NEXT: 0010: 00000000 00000000 00000000 00000000 |................|
; CHECK-NEXT: 0020: 00000000 0000 |......|
; CHECK-NEXT: )
; CHECK-DAG: Resource type (int): 6
; CHECK-NEXT: Resource name (int): 4096
; CHECK-NEXT: Data version: 0
; CHECK-NEXT: Memory flags: 0x1030
; CHECK-NEXT: Language ID: 7172
; CHECK-NEXT: Version (major): 0
; CHECK-NEXT: Version (minor): 101
; CHECK-NEXT: Characteristics: 0
; CHECK-NEXT: Data size: 74
; CHECK-NEXT: Data: (
; CHECK-NEXT: 0000: 00000000 00000000 00000000 00000000 |................|
; CHECK-NEXT: 0010: 00000C00 6C006100 72006700 65002000 |....l.a.r.g.e. .|
; CHECK-NEXT: 0020: 6E007500 6D006200 65007200 00000000 |n.u.m.b.e.r.....|
; CHECK-NEXT: 0030: 00000000 00000900 6D006900 6E007500 |........m.i.n.u.|
; CHECK-NEXT: 0040: 73002000 6F006E00 6500 |s. .o.n.e.|
; CHECK-NEXT: )
; RUN: llvm-rc /N /FO %t0 -- %p/Inputs/tag-stringtable-basic.rc
; RUN: llvm-readobj %t0 | FileCheck %s --check-prefix=NULL
; NULL: Resource type (int): 6
; NULL-NEXT: Resource name (int): 1
; NULL-NEXT: Data version: 0
; NULL-NEXT: Memory flags: 0x1030
; NULL-NEXT: Language ID: 1033
; NULL-NEXT: Version (major): 0
; NULL-NEXT: Version (minor): 32
; NULL-NEXT: Characteristics: 50
; NULL-NEXT: Data size: 52
; NULL-NEXT: Data: (
; NULL-NEXT: 0000: 02006100 00000200 62000000 02006300 |..a.....b.....c.|
; NULL-NEXT: 0010: 00000200 64000000 01000000 00000000 |....d...........|
; NULL-NEXT: 0020: 00000100 00000000 00000000 00000000 |................|
; NULL-NEXT: 0030: 00000000 |....|
; NULL-NEXT: )
; NULL-DAG: Resource type (int): 6
; NULL-NEXT: Resource name (int): 2
; NULL-NEXT: Data version: 0
; NULL-NEXT: Memory flags: 0x1030
; NULL-NEXT: Language ID: 1033
; NULL-NEXT: Version (major): 0
; NULL-NEXT: Version (minor): 0
; NULL-NEXT: Characteristics: 0
; NULL-NEXT: Data size: 44
; NULL-NEXT: Data: (
; NULL-NEXT: 0000: 03006200 62000000 03006300 63000000 |..b.b.....c.c...|
; NULL-NEXT: 0010: 00000000 00000000 00000000 00000000 |................|
; NULL-NEXT: 0020: 00000000 00000000 00000000 |............|
; NULL-NEXT: )
; NULL-DAG: Resource type (int): 6
; NULL-NEXT: Resource name (int): 2
; NULL-NEXT: Data version: 0
; NULL-NEXT: Memory flags: 0x1030
; NULL-NEXT: Language ID: 7172
; NULL-NEXT: Version (major): 0
; NULL-NEXT: Version (minor): 100
; NULL-NEXT: Characteristics: 0
; NULL-NEXT: Data size: 86
; NULL-NEXT: Data: (
; NULL-NEXT: 0000: 06006800 65006C00 6C006F00 00000600 |..h.e.l.l.o.....|
; NULL-NEXT: 0010: 77006F00 72006C00 64000000 00000000 |w.o.r.l.d.......|
; NULL-NEXT: 0020: 00000000 00000F00 73006F00 6D006500 |........s.o.m.e.|
; NULL-NEXT: 0030: 74006800 69006E00 67002000 65006C00 |t.h.i.n.g. .e.l.|
; NULL-NEXT: 0040: 73006500 00000000 00000000 00000000 |s.e.............|
; NULL-NEXT: 0050: 00000000 0000 |......|
; NULL-NEXT: )
; NULL-DAG: Resource type (int): 6
; NULL-NEXT: Resource name (int): 3
; NULL-NEXT: Data version: 0
; NULL-NEXT: Memory flags: 0x1030
; NULL-NEXT: Language ID: 1033
; NULL-NEXT: Version (major): 0
; NULL-NEXT: Version (minor): 50
; NULL-NEXT: Characteristics: 50
; NULL-NEXT: Data size: 40
; NULL-NEXT: Data: (
; NULL-NEXT: 0000: 04006300 63006300 00000000 00000000 |..c.c.c.........|
; NULL-NEXT: 0010: 00000000 00000000 00000000 00000000 |................|
; NULL-NEXT: 0020: 00000000 00000000 |........|
; NULL-NEXT: )
; NULL-DAG: Resource type (int): 6
; NULL-NEXT: Resource name (int): 4096
; NULL-NEXT: Data version: 0
; NULL-NEXT: Memory flags: 0x1030
; NULL-NEXT: Language ID: 7172
; NULL-NEXT: Version (major): 0
; NULL-NEXT: Version (minor): 101
; NULL-NEXT: Characteristics: 0
; NULL-NEXT: Data size: 78
; NULL-NEXT: Data: (
; NULL-NEXT: 0000: 00000000 00000000 00000000 00000000 |................|
; NULL-NEXT: 0010: 00000D00 6C006100 72006700 65002000 |....l.a.r.g.e. .|
; NULL-NEXT: 0020: 6E007500 6D006200 65007200 00000000 |n.u.m.b.e.r.....|
; NULL-NEXT: 0030: 00000000 00000000 0A006D00 69006E00 |..........m.i.n.|
; NULL-NEXT: 0040: 75007300 20006F00 6E006500 0000 |u.s. .o.n.e...|
; NULL-NEXT: )
; RUN: not llvm-rc /FO %t -- %p/Inputs/tag-stringtable-same-ids.rc 2>&1 | FileCheck %s --check-prefix SAMEIDS
; SAMEIDS: llvm-rc: Multiple STRINGTABLE strings located under ID 1
|
{
"language": "Assembly"
}
|
; RUN: llc %s -o -
;; Reference to a label that gets deleted.
define i8* @test1() nounwind {
entry:
ret i8* blockaddress(@test1b, %test_label)
}
define i32 @test1b() nounwind {
entry:
ret i32 -1
test_label:
br label %ret
ret:
ret i32 -1
}
;; Issues with referring to a label that gets RAUW'd later.
define i32 @test2a() nounwind {
entry:
%target = bitcast i8* blockaddress(@test2b, %test_label) to i8*
call i32 @test2b(i8* %target)
ret i32 0
}
define i32 @test2b(i8* %target) nounwind {
entry:
indirectbr i8* %target, [label %test_label]
test_label:
; assume some code here...
br label %ret
ret:
ret i32 -1
}
; Issues with a BB that gets RAUW'd to another one after references are
; generated.
define void @test3(i8** %P, i8** %Q) nounwind {
entry:
store i8* blockaddress(@test3b, %test_label), i8** %P
store i8* blockaddress(@test3b, %ret), i8** %Q
ret void
}
define i32 @test3b() nounwind {
entry:
br label %test_label
test_label:
br label %ret
ret:
ret i32 -1
}
; PR6673
define i64 @test4a() {
%target = bitcast i8* blockaddress(@test4b, %usermain) to i8*
%ret = call i64 @test4b(i8* %target)
ret i64 %ret
}
define i64 @test4b(i8* %Code) {
entry:
indirectbr i8* %Code, [label %usermain]
usermain:
br label %label_line_0
label_line_0:
br label %label_line_1
label_line_1:
%target = ptrtoint i8* blockaddress(@test4b, %label_line_0) to i64
ret i64 %target
}
|
{
"language": "Assembly"
}
|
/* ****** ****** */
//
// HX-2017-01:
// It is generated in CATS-parsemit
//
/* ****** ****** */
//
#include \
"catsparsemit/CATS/catsparse_all_dats.c"
//
/* ****** ****** */
/* end of [catsparse_all_dats.c] */
|
{
"language": "Assembly"
}
|
/* mpc_sub -- Subtract two complex numbers.
Copyright (C) 2002, 2009, 2011 INRIA
This file is part of GNU MPC.
GNU MPC is free software; you can redistribute it and/or modify it under
the terms of the GNU Lesser General Public License as published by the
Free Software Foundation; either version 3 of the License, or (at your
option) any later version.
GNU MPC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for
more details.
You should have received a copy of the GNU Lesser General Public License
along with this program. If not, see http://www.gnu.org/licenses/ .
*/
#include "mpc-impl.h"
int
mpc_sub (mpc_ptr a, mpc_srcptr b, mpc_srcptr c, mpc_rnd_t rnd)
{
int inex_re, inex_im;
inex_re = mpfr_sub (mpc_realref(a), mpc_realref(b), mpc_realref(c), MPC_RND_RE(rnd));
inex_im = mpfr_sub (mpc_imagref(a), mpc_imagref(b), mpc_imagref(c), MPC_RND_IM(rnd));
return MPC_INEX(inex_re, inex_im);
}
|
{
"language": "Assembly"
}
|
; RUN: llc -march=msp430 < %s | FileCheck %s
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
target triple = "msp430-generic-generic"
define i16 @mov(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: mov:
; CHECK: mov.w r14, r15
ret i16 %b
}
define i16 @add(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: add:
; CHECK: add.w r14, r15
%1 = add i16 %a, %b
ret i16 %1
}
define i16 @and(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: and:
; CHECK: and.w r14, r15
%1 = and i16 %a, %b
ret i16 %1
}
define i16 @bis(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: bis:
; CHECK: bis.w r14, r15
%1 = or i16 %a, %b
ret i16 %1
}
define i16 @bic(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: bic:
; CHECK: bic.w r14, r15
%1 = xor i16 %b, -1
%2 = and i16 %a, %1
ret i16 %2
}
define i16 @xor(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: xor:
; CHECK: xor.w r14, r15
%1 = xor i16 %a, %b
ret i16 %1
}
|
{
"language": "Assembly"
}
|
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